Introduction

Memristors are basically a resistor with varying resistance, depending upon the history of current flow through the device. Memristors find use in many applications. While realising memory was the common application of memristors, they can also used as building blocks in digital systems, analog circuits and even neuromorphic systems. Logic operation with memristors is a new field of interest. Unlike existing logic circuits which perform only logic computation, memristors based circuits can integrate computation and storage into a single device.

Memristors

The word memristor was coined by circuit theorist Leon Chua in 1971. Memristor is a two-terminal passive device that relates magnetic flux linkage and electric charge. The varying resistance of the device is termed as memristance (M). The existence of memristors was predicted from the symmetry that existed between the quantities voltage (v), charge (q), current (i) and flux (ɸ) as shown in fig. Already there existed three two-terminal devices resistor (R), capacitor (C) and inductor (L) relating these quantities. The symmetry seems complete with the definition of memristors. Unlike those three devices which are linear time- invariant (LTI), memristors are considered having dynamic nature. In other words, a linear time-invariant memristor having a constant memristance M is simply a resistor. The instantaneous resistance of the device depends upon how much electric charge has flowed through it in the past and in what direction it has flowed. The device is non-volatile capable of retaining its recent resistance value.

The work on memristors started late as shown in fig although its existence was predicted way back in 1971. It was only in 2008, a team at Hewlett Packard Labs found the missing memristor by examining the properties of thin film of titanium dioxide. The basic equations for modelling a memristor are

dx/dt = f (x, i)

v(t)= R(x, i) . i(t)

where x is an internal state variable

i(t) is the device current

v(t) is the voltage across the device

R(x, i) is the memristance

t is the time variable

There has been increasing interest in memristors after Hewlett Packard introduced its memristor. The memristors are also compatible with standard CMOS logic and CMOS technology. Memristors are fabricated in the metal layers of an integrated circuit and the memristive action occur in the oxide between the metal layers. Several memristor models have been proposed to describe its behaviour. All the models are deterministic and do not consider random switching. The threshold adaptive memristor (TEAM) model is used here. However a simple resistive slide model is enough to understand the digital logic operation of memristors.

Memristor Working

The structure of memristor is shown in fig. It consists of titanium oxide layer between two platinum electrodes. A part of titanium oxide is doped (Ti0 2) and the rest is undoped (Ti0x, x<2). The resistivity of doped region (Ti02) is very high compared to the undoped region. Hence the width of the doped region ‘w’ decides the effective resistance of the device. The length of the device is only 3nm making it suitable for area efficient circuit realisation.

Rmemristor = Rdoped + Rundoped

Rdoped >> Rundoped

Rmemristor = Rdoped

Rdoped= c*f(w)

c- Proportionality Constant

w- Width of doped Ti02

f- function relating Rdoped and w

Consider a positive voltage ‘+V’ applied to the memristor on the platinum electrode near to the undoped titanium oxide. This results in creation of more oxygen vacancies thereby decreasing the width of doped titanium oxide. The decreased width of doped region corresponds to a lower resistance ‘RON’.

Similarly consider a negative voltage ‘-V’ applied to the memristor on the platinum electrode near to the undoped titanium oxide. This results in filling of oxygen vacancies thereby increasing the width of doped titanium oxide. The increased width of doped region corresponds to a higher resistance ‘ROFF’.

RON= Rdoped (when w=wmin)

ROFF= Rdoped (when w=wmax)

The working of memristor (for digital applications) can be represented of a resistive- slide model. The slide moves down for positive voltage ‘+V’ and moves up for a negative voltage ‘-V’ changing the device resistance to RON and ROFF respectively.

Memristor polarity

Another important property of memristor is its polarity that is represented by a black thick line at its end. The black thick line or polarity is the platinum electrode near the undoped titanium oxide. The current flowing into this terminal (black thick line) is referred as current flowing into the memristor which decreases the device resistance to RON. On the other hand, current flowing out of this terminal is referred as current flowing out of the memristor which increases the device resistance to ROFF.

Memristors in LOGIC

As discussed earlier memristors are suitable for logic as they can perform storage and have good scalability. Some possible logic families with memristors include

Memristor Ratioed Logic (MRL) IMPLY Logic (Material Implication) M emristor Aided LoGIC (MAGIC)

The most simple among these is the Memristor Ratioed Logic (MRL). The MRL can be used to realize AND, OR logic gates. The MRL uses programmable resistance of memristors to do Boolean logic computation. It is a voltage based logic and can easily integrated with CMOS logic to produce hybrid CMOS/Memristor logic.

The IMPLY logic and MAGIC are logic inside a memristor based crossbar. The IMPLY can be used to realize NAND,NOR gates. The MAGIC can produce all the basic Boolean function like AND,NAND,OR and NOR. All of these gates in crossbar require a sequencer to operate and the output of the computation is available after multiple clock cycles. Hence the logic based on crossbar array are relatively slower. Also these logic families represent logic levels as resistance levels which puts a need an interpreter or sensing element to provide a voltage output. The extra circuitry reduces the efficiency of integrating CMOS with crossbar based memristor logic families. These logic gates have problem of state drift and lack signal restoring capability.

Memristor Ratioed Logic (MRL)

Memristor Ratioed Logic family is used to realize simple logic functions like AND, OR. The logic level ‘1’ and ‘0’ are represented by voltage levels ‘VDD’

and ‘Gnd’ respectively. The memristor is used as only computational element i.e., the output logical value calculated is not stored. This logic family thus does not utilize the memristor storage property thereby making it a real-time logic family. The analysis of the logic involves applying simple voltage division. The result of the computation is independent of initial state of the memristive devices. However, the computation time has dependence on the initial state of the memristor.

Both MRL AND and OR gate consist of two memristors connected together in series with opposite polarity. The output is taken from the common node of both the memristors. The signal at the remaining terminal act as input to the logic gate. Due to polarity of memrsitors used in OR gate when current flows into the input, the resistance of memristor decreases. But for an AND gate, since we use the opposite polarity, when current flows into the input the resistance of the memristor increase. The OR and AND gate respond the same when both the inputs are logically equal.

MRL AND Gate

The MRL AND gate is shown in fig consisting of two memristors. When both IN1 and IN2 are equal to VDD or Gnd there is no current flow and the input is equal to the output. Current flows through the device only when complementary inputs are applied. The current flows into one memristor but flows out of the other memresitor making the resistance of memristors RON and ROFF

respectively. The output is either VDD *RON/( RON + ROFF) or VDD *RON/( RON + ROFF). Typically the ratio ROFF/RON is 103

.

MRL OR Gate

The MRL OR gate shown in fig has similar operation. It is obtained simply by flipping the memristors used in MRL AND gate. When both the inputs are equal the output is equal to the input. For complementary inputs one of the memristor has decreased resistance RON and the other has increased resistance ROFF. The output logic level is decided by the voltage division.

POWER CONSIDERATIONS

When the input changes from (0, 1) to (1, 0) the output produces a dynamic hazard till the switching procedure is completed. Also when both memristors are initially if off condition, the settling time is very high. The power consumed during transition changes with time as the resistances of memristors become a function of time as seen in fig . The power comsumed is given by

SIGNAL DEGRADATION IN MRL

Consider the topology of MRL gates. For calculation assume VDD=1 V, RON=100 Ω and ROFF=10 kΩ. When the inputs are applied nodes A, B and C are respectively at 0.99 V, 0.01V and 0.97 V. We can infer that the logic level high is less than VDD and logic level low is greater than 0 V. This degradation happens because memristors are passive devices. The condition is worse for long logic chains.

The delay time of the gates is dependent on the applied voltage level. In long chains the memristors do not completely switch and are not able to achieve minimum or maximum resistance. So it becomes difficult to distinguish the output voltage levels.

EXTENDING THE MRL GATES The MRL logic family is based on Diode Logic. Both the logic families are non-restoring and non-inverting. Similar to the Diode Logic the number of inputs to the MRL AND, OR gates can be easily extended.

HYBRID CMOS/MEMRISTOR LOGIC

The degradation problem brings the need for amplification which can be employed using buffers and inverters. In order to provide a complete logic we need additional inverters. The CMOS logic that exhibits signal restoration can be used together to solve this issue. Using inverters not only solves degradation problem but also helps to realize NAND and NOR gates which are universal gates to realize any Boolean function.

This idea of using CMOS and Memristor logic together gives new logic called as hybrid CMOS/Memristor logic. The logic levels are still in the voltage domain. In this logic the memristor circuits are fabricated as a crossbar add-on in the die containing the CMOS logic circuits as shown in fig .The conventional MOSFET circuits are supported on the substrate whereas the crossbar add-on of memristors are supported at the top through metal via. Instead of using inverter which follows a MRL gate, it will be convenient if we use select transistors to access the memristors. This will help in realisation of crossbar based structures. Now the memristor is assumed to have three terminals T1 ,T2 and Sel as shown in fig

There are two possibilities for CMOS/Memristor crossbar structure. The difference between them lies in the use of supporting via as seen in fig

Conventional CMOS circuits

Crossbar Add-on

(Memristors)

LOGIC INSIDE THE MEMORY

It is based on memristors arranged in crossbar array. The crossbar organisation of memory structures are known for their area efficiency and circuit routing during chip realisation. This crossbar concept is new to logic circuits capable of storage i.e., memristor circuits. The memristors in this circuits perform computation and storage. The logic levels are represented by resistive levels and not voltage levels as in the case of MRL. In other words we can say that RON

corresponds to logical ‘1’ and ROFF corresponds to logical ‘0’. This logic is useful as it provides an opportunity to model advanced computer logic different from the von Neumann architecture. Under this category there are two logic families namely

1. IMPLY logic2. M emristor Aided loGIC ( MAGIC )

IMPLY LOGIC

IMPLY logic is a two input elementary Boolean function. The statement ‘P implies Q’ is logically equivalent to ‘if P then Q’. The truth table of the imply gate is shown in fig. The IMPLY function along with FALSE statement constitutes a complete logic. The IMPLY function can easily be integrated within memristor based crossbars.

IMPLY logic gate operation

The gate consists of an resistor RG (RON < RG < ROFF) and two memristors P and Q acting as switches. The input to the gate is the initial memristances p and q of the memristors. (Note that p and q represent the instantaneous memristance of the memristors P and Q respectively). The final memristance of the memristor Q is the output of the gate. The output computation can be destructive to both the inputs.

The operation involves the application of two different voltages VSET and VCOND

where |VCOND|< |VSET|. If p=1 i.e., low resistance then voltage VG is approximately VSET-VCOND and the logic state of memristor Q is maintained. When p=0 and q=1, memristor Q maintains its logic state. When p=0, q=0 the memristor Q is switched ON.

PERFORMANCE BEHAVIOUR OF IMPLY

In the case 2 and 4 , the initial and final logic state of memristor Q is logical one. In the case 1 memristor Q is initially at logical zero and after applying VSET,VCOND memristor Q switches its state to logical 1. Thus case 1 determines the duration for which the voltages VSET and VCOND have to be applied until memristor Q switches its logical state. In other words, case 1 decides the write time of the gate. In case 3, the logic state of memristor Q must remain unchanged even after applying VSET,VCOND . But the voltages tend to change the

state of memristor Q to logical one called as state drift. The problem of state drift can be solved by periodic refreshing.

Case 1 determines the time required to apply VSET and VCOND which is the write time, a vital performance parameter of the gate. If the performance of the gate is improved by altering the magnitude of VSET and VCOND, the problem of state drift increases. Hence there is always a speed-robustness tradeoff prevailing in the gate.

Logic functions based on IMPLY

The IMPLY and FASLE function together make a complete logic. Any ‘n’ variable Boolean function can be implemented by only n+3 memristors. These additional 3 memristors carry the computation. The computation requires many sequential steps to be performed. General algorithm to evaluate any Boolean function with minimum number of memristors have also been developed. But using minimum number of memristors to evaluate the Boolean expression tends to increase the computation time.

The NAND gate using IMPLY logic is shown in fig consists of 3 memristors P,Q and S to minimize computation time. The sequence of steps involved in performing NAND operation is shown in . Memristance p and q are inputs to the gate. The NAND evaluation involves one FASLE and two IMPLY operation. The sequences of steps are

FALSE (S) (P) IMPLY (S) (Q) IMPLY (S)

The table shows the voltages applied during each step of NAND computation.

The IMPLY logic gate can also be used to realise multiple input NOR gate. In the fig we use k input memristors P1, P2 .., Pk and separate output memristor Q. The NOR evaluation involves two steps. At first the memristor Q is switched to logical zero (q=0) and subsequently the voltages VSET and VCOND are applied. This extended NOR gate has the problem of low fan-in since RG has to support all possible inputs. This issue can be solved by using a modified design shown in fig where we use separate resistor for each memristor.

IMPLY LOGIC INSIDE A CROSSBAR.