VLSI/FPGAVLSI/FPGADesign and Test Flow with Design and Test Flow with Mentor Graphics CAD ToolsMentor Graphics CAD Tools
Victor P. NelsonVictor P. Nelson
Mentor Graphics CAD Tool SuitesMentor Graphics CAD Tool Suites
IC/IC/SoCSoC design flowdesign flow11
DFT/BIST/ATPG design flowDFT/BIST/ATPG design flow11
FPGA design flowFPGA design flow2,32,3
PCB design flowPCB design flow22
Digital/analog/mixedDigital/analog/mixed--signal modeling & simulationsignal modeling & simulation1,21,2
ASIC/FPGA synthesisASIC/FPGA synthesis1,21,2
VendorVendor--provided (provided (Xilinx,Altera,etcXilinx,Altera,etc.) back end tools.) back end tools22
1.1. UserUser--setup selection: setup selection: eda/mentor/ICFlow2006.1eda/mentor/ICFlow2006.12.2. UserUser--setup selection: setup selection: eda/mentor/EN2002.3eda/mentor/EN2002.33.3. UserUser--setup selection:setup selection: edaeda/mentor/FPGA/mentor/FPGA
Mentor Graphics CAD Tools Mentor Graphics CAD Tools (select (select ““edaeda/mentor/mentor”” in userin user--setup on the Sun network*)setup on the Sun network*)
ICFlow2006.1ICFlow2006.1–– For custom & standard cell IC designsFor custom & standard cell IC designs–– IC flow toolsIC flow tools (Design Architect(Design Architect--IC, IC Station, IC, IC Station, CalibreCalibre))–– Digital/analog/mixed simulation Digital/analog/mixed simulation ((Modelsim,ADVanceModelsim,ADVance MS,Eldo,MachTAMS,Eldo,MachTA))–– HDL SynthesisHDL Synthesis (Leonardo)(Leonardo)–– ATPG/DFT/BIST toolsATPG/DFT/BIST tools (DFT Advisor, (DFT Advisor, FlextestFlextest, , FastscanFastscan))–– Limited access to Limited access to QuicksimQuicksim II II (some technologies)(some technologies)
EN2002u3 EN2002u3 –– For FPGA For FPGA ““front endfront end”” design & printed circuit boardsdesign & printed circuit boards–– Design Architect, Design Architect, QuicksimQuicksim II, II, QuicksimQuicksim Pro Pro (Schematic/Simulation)(Schematic/Simulation)–– ModelSimModelSim & Leonardo & Leonardo (HDL Simulation/Synthesis)(HDL Simulation/Synthesis)–– Xilinx ISE & Xilinx ISE & AlteraAltera ““QuartusQuartus”” tools tools (Back end design)(Back end design)
FPGAFPGA (FPGA Advantage, (FPGA Advantage, ModelsimModelsim, Leonardo), Leonardo)
*Only one of the above three groups may be selected at a time*Only one of the above three groups may be selected at a time
Mentor Graphics ASIC Design Kit (ADK)Mentor Graphics ASIC Design Kit (ADK)Technology files & standard cell librariesTechnology files & standard cell libraries–– AMI: ami12, ami05 AMI: ami12, ami05 (1.2, 0.5 (1.2, 0.5 μμm)m)–– TSMC: tsmc035, tsmc025, tsmc018 TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 (0.35, 0.25, 0.18 μμm)m)
IC flow & DFT tool support files:IC flow & DFT tool support files:–– Simulation Simulation
VHDL/VHDL/VerilogVerilog/Mixed/Mixed--Signal modelsSignal models ((Modelsim/ADVanceModelsim/ADVance MS)MS)Analog (SPICE) modelsAnalog (SPICE) models ((Eldo/AccusimEldo/Accusim))PostPost--layout timing layout timing (Mach TA)(Mach TA)Digital schematic Digital schematic ((QuicksimQuicksim II, II, QuicksimQuicksim Pro)Pro) (exc. tsmc025,tsmc018)(exc. tsmc025,tsmc018)
–– Synthesis to std. cells Synthesis to std. cells ((LeonardoSpectrumLeonardoSpectrum))–– Design for test & ATPG Design for test & ATPG (DFT Advisor, (DFT Advisor, Flextest/FastscanFlextest/Fastscan))–– Schematic capture Schematic capture (Design Architect(Design Architect--IC)IC)–– IC physical design (standard cell & custom) IC physical design (standard cell & custom)
FloorplanFloorplan, place & route , place & route (IC Station)(IC Station)Design rule check, layout Design rule check, layout vsvs schematic, parameter extraction schematic, parameter extraction ((CalibreCalibre))
Xilinx/Xilinx/AlteraAltera FPGA/CPLD DesignFPGA/CPLD DesignTechnology files & libraries for frontTechnology files & libraries for front--end design with end design with Mentor Graphics toolsMentor Graphics tools–– Schematic symbols for Schematic symbols for Design ArchitectDesign Architect–– Simulation models forSimulation models for QuicksimQuicksim II, II, QuicksimQuicksim ProPro–– Synthesis library for Synthesis library for LeonardoLeonardo
Vendor tools for backVendor tools for back--end design end design (map, place, route, configure, timing)(map, place, route, configure, timing)
–– Xilinx Xilinx Integrated Software EnvironmentIntegrated Software Environment (ISE)(ISE)Xilinx XST can synthesize the design from VHDL or Xilinx XST can synthesize the design from VHDL or VerilogVerilog (instead (instead of Leonardo)of Leonardo)
–– AlteraAltera QuartusQuartus II & Max+Plus2II & Max+Plus2
ASIC Design FlowASIC Design FlowBehavioral
ModelVHDL/Verilog
Gate-LevelNetlist
Transistor-LevelNetlist
PhysicalLayout
Map/Place/Route
DFT/BIST& ATPG
VerifyFunction
VerifyFunction
Verify Function& Timing
Verify Timing
DRC & LVSVerification
IC Mask Data/FPGA Configuration File
Standard Cell IC & FPGA/CPLD
Synthesis
Test vectors Full-custom IC
Behavioral Design & VerificationBehavioral Design & Verification(mostly technology(mostly technology--independent)independent)
Create Behavioral/RTL HDL Model(s)
Simulate to VerifyFunctionality
Synthesize Gate-LevelCircuit
LeonardoSpectrum(digital)
ModelSim(digital)
VHDL-AMSVerilog-A
ADVance MS (analog/mixed signal)
VHDLVerilog
SystemC
Technology LibrariesPost-Layout Simulation,
Technology-Specific Netlistto Back-End Tools
ADVanceADVance MS Simulation SystemMS Simulation System
ADVanceADVance MS MS ““kernelkernel”” supports:supports:–– VHDL & VHDL & VerilogVerilog: digital : digital (via (via ModelSimModelSim))–– VHDLVHDL--AMS & AMS & VerilogVerilog--A: analog/mixed signalA: analog/mixed signal–– EldoEldo/SPICE: analog /SPICE: analog (via (via EldoEldo))–– EldoEldo RF/SPICE: analog RF RF/SPICE: analog RF (via (via EldoEldo RF)RF)–– Mach TA/SPICE: highMach TA/SPICE: high--speed analog/timingspeed analog/timing
Invoke standInvoke stand--alone or from Design Architectalone or from Design Architect--ICIC
Mentor Graphics Mentor Graphics ““LegacyLegacy”” Simulators Simulators (PCB design)(PCB design)–– QuicksimQuicksim II, II, QuicksimQuicksim Pro (digital)Pro (digital)–– ASIC: ASIC: adk_quicksimadk_quicksim–– FPGA/PLD: Xilinx: FPGA/PLD: Xilinx: pld_quicksimpld_quicksim, , AlteraAltera: : max2_quicksimmax2_quicksim–– AccusimAccusim (analog): (analog): adk_accusimadk_accusim
ADVanceADVance MSMSDigital, Analog, MixedDigital, Analog, Mixed--Signal SimulationSignal Simulation
ADVance MS
WorkingLibrary
Design_1Design_2
VITAL
IEEE 1164 ResourceLibraries
SimulationSetup
EZwaveor Xelga
InputStimuli
VHDL,Verilog,VHDL-AMS, Verilog-A,
SPICE Netlists
Eldo,Eldo RF ModelSim
View ResultsMach TAMach PA
Analog(SPICE) Digital
(VHDL,Verilog)
Mixed Signal(VHDL-AMS,
Verilog-A)
SPICEmodels
Example: 4Example: 4--bit binary counterbit binary counter
VHDL modelVHDL model (count4.vhd)(count4.vhd)–– Create working library: Create working library: vlibvlib workwork
vmapvmap work work workwork–– Compile: Compile: vcomvcom count4.vhdcount4.vhd–– Simulate: Simulate: vsimvsim count4(rtl)count4(rtl)ModelSimModelSim simulationsimulation--control inputscontrol inputs–– ModelSimModelSim ““MacroMacro”” (count4_rtl.do)(count4_rtl.do)–– OR, VHDL OR, VHDL testbenchtestbenchModelSimModelSim resultsresults–– listinglisting or or waveformwaveform
---- count4.vhd 4count4.vhd 4--bit parallelbit parallel--load synchronous counterload synchronous counterLIBRARY LIBRARY ieeeieee;;USE ieee.std_logic_1164.all; USE USE ieee.std_logic_1164.all; USE ieee.numeric_std.allieee.numeric_std.all;;
ENTITY count4 ISENTITY count4 ISPORT (PORT (clock,clear,enable,load_countclock,clear,enable,load_count : IN STD_LOGIC;: IN STD_LOGIC;
D: IN unsigned(3 D: IN unsigned(3 downtodownto 0);0);Q: OUT unsigned(3 Q: OUT unsigned(3 downtodownto 0));0));
END count4;END count4;
ARCHITECTURE ARCHITECTURE rtlrtl OF count4 ISOF count4 ISSIGNAL SIGNAL intint : unsigned(3 : unsigned(3 downtodownto 0);0);BEGINBEGIN
PROCESS(clearPROCESS(clear, clock, enable), clock, enable)BEGIN BEGIN
IF (clear = '1') THEN IF (clear = '1') THEN intint <= "0000";<= "0000";
ELSIF (ELSIF (clock'EVENTclock'EVENT AND clock='1') THEN AND clock='1') THEN IF (enable = '1') THEN IF (enable = '1') THEN
IF (IF (load_countload_count = '1') THEN= '1') THENintint <= D;<= D;
ELSEELSEintint <= <= intint + "01";+ "01";
END IF;END IF;END IF;END IF;
END IF;END IF;END PROCESS; END PROCESS; Q <= Q <= intint;;
END END rtlrtl;;
Test stimulus:Test stimulus:ModelsimModelsim ““dodo”” file: count4_rtl.dofile: count4_rtl.do
add wave /clock /clear /enable /add wave /clock /clear /enable /load_countload_count /D /Q/D /Qadd list /clock /clear /enable /add list /clock /clear /enable /load_countload_count /D /Q/D /Qforce /clock 0 0, 1 10 force /clock 0 0, 1 10 --repeat 20repeat 20force /clear 0 0, 1 5, 0 10force /clear 0 0, 1 5, 0 10force /enable 0 0, 1 25force /enable 0 0, 1 25force /force /load_countload_count 0 0, 1 20, 0 35, 1 330, 0 3500 0, 1 20, 0 35, 1 330, 0 350force /D 10#5 0, 10#9 300force /D 10#5 0, 10#9 300run 400run 400
TestbenchTestbench: count4_bench.vhd: count4_bench.vhdLIBRARY LIBRARY ieeeieee; USE ieee.std_logic_1164.all; USE ; USE ieee.std_logic_1164.all; USE ieee.numeric_std.allieee.numeric_std.all;;
ENTITY count4_bench is end count4_bench;ENTITY count4_bench is end count4_bench;ARCHITECTURE test of count4_bench isARCHITECTURE test of count4_bench is
component count4component count4PORT (PORT (clock,clear,enable,load_countclock,clear,enable,load_count : IN STD_LOGIC;: IN STD_LOGIC;
D: IN unsigned(3 D: IN unsigned(3 downtodownto 0);0);Q: OUT unsigned(3 Q: OUT unsigned(3 downtodownto 0));0));
end component;end component;for all: count4 use entity work.count4(behavior);for all: count4 use entity work.count4(behavior);signal signal clkclk : STD_LOGIC := '0';: STD_LOGIC := '0';signal signal clrclr, en, ld: STD_LOGIC;, en, ld: STD_LOGIC;signal din, signal din, qoutqout: unsigned(3 : unsigned(3 downtodownto 0);0);
beginbeginUUT: count4 port UUT: count4 port map(clk,clr,en,ld,din,qoutmap(clk,clr,en,ld,din,qout););clkclk <= not <= not clkclk after 10 ns;after 10 ns;P1: processP1: process
beginbegindin <= "0101"; din <= "0101"; clrclr <= '1'; en <= '1'; ld <= '1';<= '1'; en <= '1'; ld <= '1';wait for 10 ns;wait for 10 ns;clrclr <= '0'; <= '0';
wait for 20 ns;wait for 20 ns;ld <= '0';ld <= '0';wait for 200 ns;wait for 200 ns;
end process;end process;end;end;
Alternative to “do” file
Could also check results &“assert” error messages
Count4 Count4 –– Simulation waveformSimulation waveform
ParallelLoad
CountingClear
ADVanceADVance MS : mixedMS : mixed--signal simulationsignal simulation
A/D converter
digital
analogVHDL-AMS
ADVanceADVance MS: mixed MS: mixed VerilogVerilog--SPICESPICE
SPICEsubcircuit
Verilog top(test bench)
Automated Synthesis with Automated Synthesis with Leonardo SpectrumLeonardo Spectrum
Leonardo Spectrum(Level 3)
VHDL/VerilogBehavioral/RTL Models
FPGA
ASIC
TechnologySynthesis Libraries
Technology-SpecificNetlist
DesignConstraints
VHDL, Verilog, SDF,EDIF, XNF
Level 1 – FPGALevel 2 – FPGA + Timing
ADKAMI 0.5, 1.2TSMC 0.35, 0.25
Leonardo Leonardo –– ASIC Synthesis FlowASIC Synthesis Flow
Leonardo synthesis procedureLeonardo synthesis procedure
1.1. Invoke Invoke leonardoleonardo2.2. Select & load a technology library Select & load a technology library (ASIC or FPGA)(ASIC or FPGA)
–– ASIC > ADK > TSMC 0.35 micronASIC > ADK > TSMC 0.35 micron3.3. Read input VHDL/Read input VHDL/VerilogVerilog file(sfile(s): ): count4.vhdcount4.vhd4.4. Enter any constraints (clock freq, delays, etc.)Enter any constraints (clock freq, delays, etc.)5.5. Optimize for area/delay/effort levelOptimize for area/delay/effort level6.6. Write output Write output file(sfile(s))
–– count4_0.vhdcount4_0.vhd -- VHDL VHDL netlistnetlist–– count4.vcount4.v -- VerilogVerilog netlistnetlist (for IC layout)(for IC layout)–– count4.sdf count4.sdf -- Standard delay format file Standard delay format file (for timing)(for timing)–– count4.edf count4.edf -- EDIF EDIF netlistnetlist (for Xilinx/(for Xilinx/AlteraAltera FPGA)FPGA)
LeonardoLeonardo--synthesized synthesized netlistnetlist count4_0.vhdcount4_0.vhdlibrary IEEE; use IEEE.STD_LOGIC_1164.all;library IEEE; use IEEE.STD_LOGIC_1164.all;library library adkadk; use ; use adk.adk_components.alladk.adk_components.all; ; ---- ADDED BY VPNADDED BY VPNentity count4 isentity count4 is
port (port (clock : IN clock : IN std_logicstd_logic ; clear : IN ; clear : IN std_logicstd_logic ; enable : IN ; enable : IN std_logicstd_logic ; ; load_countload_count : IN : IN std_logicstd_logic ;;D : IN D : IN std_logic_vectorstd_logic_vector (3 DOWNTO 0) ; Q : OUT (3 DOWNTO 0) ; Q : OUT std_logic_vectorstd_logic_vector (3 DOWNTO 0)) ;(3 DOWNTO 0)) ;
end count4 ;end count4 ;
architecturearchitecture netlistnetlist of count4 isof count4 is ---- rtlrtl changed to changed to netlistnetlist by VPNby VPNsignal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nsignal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, x14, nx22,
nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx169, nx181, nx183, nx185, nx187, nx189: nx183, nx185, nx187, nx189: std_logicstd_logic ;;
beginbeginQ(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLQ(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ;R ; Q(0) <= Q_0_EXMPLR ;Q_0_EXMPLR_EXMPLR : Q_0_EXMPLR_EXMPLR : dffrdffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>cport map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear);lear);ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable );, S0=>enable );ix9 : oai21 port map ( Y=>nx8, A0=>ix9 : oai21 port map ( Y=>nx8, A0=>load_countload_count, A1=>Q_0_EXMPLR, B0=>nx169 );, A1=>Q_0_EXMPLR, B0=>nx169 );ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_countload_count););Q_1_EXMPLR_EXMPLR : Q_1_EXMPLR_EXMPLR : dffrdffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock,port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear);R=>clear);ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx2ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> enable);8, S0=> enable);ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_countload_count, B0=>nx14, B1=> nx22);, B0=>nx14, B1=> nx22);ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);PLR);ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> MPLR, B0=> load_countload_count););Q_2_EXMPLR_EXMPLR : Q_2_EXMPLR_EXMPLR : dffrdffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear);clear);ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx4ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> enable);8, S0=> enable);ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189);nx189);ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR);MPLR, B0=> Q_2_EXMPLR);ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187);ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187);ix186 : inv01 port map ( Y=>nx185, A=>ix186 : inv01 port map ( Y=>nx185, A=>load_countload_count););ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_Eix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR);XMPLR, A2=> Q_0_EXMPLR);ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_countload_count););Q_3_EXMPLR_EXMPLR : Q_3_EXMPLR_EXMPLR : dffrdffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clport map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear);ear);ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx6ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> enable);2, S0=> enable);ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>>load_countload_count););ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187)ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);;
end end netlistnetlist ;;
// // VerilogVerilog description for cell count4, description for cell count4, LeonardoSpectrumLeonardoSpectrum Level 3, 2005a.82 Level 3, 2005a.82 module count4 ( clock, clear, enable, module count4 ( clock, clear, enable, load_countload_count, D, Q ) ;, D, Q ) ;
input clock ;input clock ;input clear ;input clear ;input enable ;input enable ;input input load_countload_count ;;input [3:0]D ;input [3:0]D ;output [3:0]Q ;output [3:0]Q ;
wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189;nx189;
wire [3:0] wire [3:0] \\$dummy ;$dummy ;
dffrdffr Q_0__rename_rename (.Q (Q[0]), .QB (Q_0__rename_rename (.Q (Q[0]), .QB (\\$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enabmux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) ;le)) ;oai21 ix9 (.Y (nx8), .A0 (oai21 ix9 (.Y (nx8), .A0 (load_countload_count), .A1 (Q[0]), .B0 (nx169)) ;), .A1 (Q[0]), .B0 (nx169)) ;nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_countload_count)) ;)) ;dffrdffr Q_1__rename_rename (.Q (Q[1]), .QB (Q_1__rename_rename (.Q (Q[1]), .QB (\\$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enamux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable)) ;ble)) ;ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_countload_count), .B0 (nx14), .B1 (nx22) ) ;), .B0 (nx14), .B1 (nx22) ) ;or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_countload_count)) ;)) ;dffrdffr Q_2__rename_rename (.Q (Q[2]), .QB (Q_2__rename_rename (.Q (Q[2]), .QB (\\$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enamux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable)) ;ble)) ;oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) ;) ;aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2]))aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ;;nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;inv01 ix186 (.Y (nx185), .A (inv01 ix186 (.Y (nx185), .A (load_countload_count)) ;)) ;nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) ;) ;nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_countload_count)) ;)) ;dffrdffr Q_3__rename_rename (.Q (Q[3]), .QB (Q_3__rename_rename (.Q (Q[3]), .QB (\\$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enamux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable)) ;ble)) ;mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_countload_count)) ;)) ;xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;
endmoduleendmodule
PostPost--synthesis simulationsynthesis simulation((LeonardoLeonardo--generated generated netlistnetlist))
Verify synthesized Verify synthesized netlistnetlist matches behavioral matches behavioral modelmodelCreate simulation primitives library for std cells:Create simulation primitives library for std cells:
>>vlibvlib adkadk>>vcomvcom $ADK/technology/$ADK/technology/adk.vhdadk.vhd>>vcomvcom $ADK/technology/$ADK/technology/adk_comp.vhdadk_comp.vhd
Insert library/package declaration into Insert library/package declaration into netlistnetlistlibrary library adkadk;;use use adk.adk_components.alladk.adk_components.all;;
Simulate in Simulate in ModelsimModelsim, using , using ““do filedo file”” or test bench from or test bench from original behavioral simulation original behavioral simulation –– results should matchresults should match
VITALmodels of all ADK std cells
PostPost--synthesis timing analysissynthesis timing analysisLeonardo can generate SDF (std. delay format) file with Leonardo can generate SDF (std. delay format) file with technologytechnology--specific, VITALspecific, VITAL--compliant timing parameters.compliant timing parameters.
(CELLTYPE "(CELLTYPE "dffrdffr")")(INSTANCE Q_0_EXMPLR_EXMPLR)(INSTANCE Q_0_EXMPLR_EXMPLR)(DELAY(DELAY
(ABSOLUTE(ABSOLUTE(PORT D (::0.00) (::0.00))(PORT D (::0.00) (::0.00))(PORT CLK (::0.00) (::0.00))(PORT CLK (::0.00) (::0.00))(PORT R (::0.00) (::0.00))(PORT R (::0.00) (::0.00))(IOPATH CLK Q (::0.40) (::0.47))(IOPATH CLK Q (::0.40) (::0.47))(IOPATH R Q (::0.00) (::0.55))(IOPATH R Q (::0.00) (::0.55))(IOPATH CLK QB (::0.45) (::0.36))(IOPATH CLK QB (::0.45) (::0.36))(IOPATH R QB (::0.53) (::0.00))))(IOPATH R QB (::0.53) (::0.00))))
(TIMINGCHECK(TIMINGCHECK(SETUP D ((SETUP D (posedgeposedge CLK) (0.47))CLK) (0.47))(HOLD D ((HOLD D (posedgeposedge CLK) (CLK) (--0.06))))0.06))))
Design for test & test generationDesign for test & test generation
Consider test during the Consider test during the designdesign phasephase–– Test design more difficult after design frozenTest design more difficult after design frozen
Basic steps:Basic steps:–– Design for test (DFT) Design for test (DFT) –– insert test points, scan insert test points, scan
chains, etc. to improve testabilitychains, etc. to improve testability–– Insert builtInsert built--in selfin self--test (BIST) circuitstest (BIST) circuits–– Generate test patterns (ATPG)Generate test patterns (ATPG)–– Determine fault coverage (Fault Simulation)Determine fault coverage (Fault Simulation)
DFT & test design flowDFT & test design flow
Memory& LogicBIST Boundary
Scan
InternalScan Design
ATPG
DFTadvisor/FastScanDFTadvisor/FastScan Design FlowDesign Flow
Source: FlexTest Manual
DFT/ATPGLibrary:adk.atpg
count4.vhd
count4_0.vhdcount4.v
count4_scan.v
ASIC DFT FlowASIC DFT Flow
Insert Internal Scan Circuitry
Generate/VerifyTest Vectors
Synthesized VHDL/Verilog Netlist
adk.atpg
ATPG Library
DFT Advisor
Fastscan/Flextest
VHDL/VerilogNetlist With
Scan Elements
Test Pattern File
Example Example DFTadvisorDFTadvisor sessionsessionInvoke: Invoke: –– dftadvisordftadvisor ––verilogverilog count4.v count4.v ––lib $ADK/technology/lib $ADK/technology/adk.atpgadk.atpg
Implement scan with defaults:Implement scan with defaults:(full scan, (full scan, muxmux--DFF scan elements)DFF scan elements)
–– set system mode setupset system mode setup–– analyze control signals analyze control signals ––autoauto–– set system mode set system mode dftdft–– runrun–– insert test logicinsert test logic–– write write netlistnetlist count4_scan.v count4_scan.v ––verilogverilog–– write write atpgatpg setup count4_scan setup count4_scan
(creates count4_scan.dofile for ATPG in (creates count4_scan.dofile for ATPG in FastscanFastscan))
count4 count4 –– without scan designwithout scan design
count4 count4 –– scan inserted by scan inserted by DFTadvisorDFTadvisor
ATPG with ATPG with FastScanFastScan(full(full--scan circuit)scan circuit)
Invoke: Invoke: –– fastscanfastscan ––verilogverilog count4.v count4.v ––lib $ADK/technology/lib $ADK/technology/adk.atpgadk.atpg
Generate test pattern file:Generate test pattern file:–– dofiledofile count4_scan.dofile count4_scan.dofile (defines scan path & procedure)(defines scan path & procedure)–– set system mode set system mode atpgatpg–– create patterns create patterns ––auto auto (generate test patterns)(generate test patterns)–– save patternssave patterns
Note: “count4_scan.dofile” created by DFTadvisor
Test file: scan chain definition and Test file: scan chain definition and load/unload proceduresload/unload procedures
scan_groupscan_group "grp1" ="grp1" =scan_chainscan_chain "chain1" ="chain1" =
scan_inscan_in = "/scan_in1";= "/scan_in1";scan_outscan_out = "/output[3]";= "/output[3]";length = 4;length = 4;
end;end;procedure shift "grp1_load_shift" =procedure shift "grp1_load_shift" =
force_sciforce_sci "chain1" 0;"chain1" 0;force "/clock" 1 20;force "/clock" 1 20;force "/clock" 0 30;force "/clock" 0 30;period 40;period 40;
end;end;procedure shift "grp1_unload_shift" =procedure shift "grp1_unload_shift" =
measure_scomeasure_sco "chain1" 10;"chain1" 10;force "/clock" 1 20;force "/clock" 1 20;force "/clock" 0 30;force "/clock" 0 30;period 40;period 40;
end;end;
procedure load "grp1_load" =procedure load "grp1_load" =force "/clear" 0 0;force "/clear" 0 0;force "/clock" 0 0;force "/clock" 0 0;force "/force "/scan_enscan_en" 1 0;" 1 0;apply "grp1_load_shift" 4 40;apply "grp1_load_shift" 4 40;
end;end;procedure unload "grp1_unload" =procedure unload "grp1_unload" =
force "/clear" 0 0;force "/clear" 0 0;force "/clock" 0 0;force "/clock" 0 0;force "/force "/scan_enscan_en" 1 0;" 1 0;apply "grp1_unload_shift" 4 40;apply "grp1_unload_shift" 4 40;
end;end;end;end;
Generated scanGenerated scan--based testbased test// send a pattern through the scan chain// send a pattern through the scan chainCHAIN_TEST =CHAIN_TEST =
pattern = 0;pattern = 0;apply "grp1_load" 0 = apply "grp1_load" 0 = (use grp1_load procedure)(use grp1_load procedure)
chain "chain1" = "0011"; chain "chain1" = "0011"; (pattern to scan in)(pattern to scan in)end;end;apply "grp1_unload" 1 = apply "grp1_unload" 1 = (use grp1_unload procedure)(use grp1_unload procedure)
chain "chain1" = "1100"; chain "chain1" = "1100"; (pattern scanned out)(pattern scanned out)end;end;
end;end;// one of 14 patterns for the counter circuit// one of 14 patterns for the counter circuitpattern = 0; pattern = 0; (pattern #)(pattern #)
apply "grp1_load" 0 = apply "grp1_load" 0 = (load scan chain)(load scan chain)chain "chain1" = "1000"; chain "chain1" = "1000"; (scan(scan--in pattern)in pattern)
end;end;force "PI" "00110" 1; force "PI" "00110" 1; (PI pattern)(PI pattern)measure "PO" "0010" 2; measure "PO" "0010" 2; (expected POs)(expected POs)pulse "/clock" 3; pulse "/clock" 3; (normal op. cycle)(normal op. cycle)apply "grp1_unload" 4 = apply "grp1_unload" 4 = (read scan chain)(read scan chain)
chain "chain1" = "0110"; chain "chain1" = "0110"; (expected pattern)(expected pattern)end;end;
ASIC Physical Design (Standard Cell)ASIC Physical Design (Standard Cell)(can also do full custom layout)(can also do full custom layout)
FloorplanChip/Block
Place & RouteStd. Cells
Component-Level Netlist (EDDM format)
IC Mask Data
Design RuleCheck
Std. CellLayouts
Mentor Graphics“IC Station”
(adk_ic)
Mach TA/Eldo Simulation Model
BackannotateSchematic
GenerateMask Data
Layout vs.Schematic
Check
Design Rules
Process Data
Libraries
Calibre Calibre Calibre
ICblocks
CellCell--Based ICBased IC
CellCell--Based BlockBased Block
Source: Weste “CMOS VLSI Design”
Basic standardCell layout
Preparation for LayoutPreparation for Layout1.1. Use Design ArchitectUse Design Architect--IC to convert IC to convert VerilogVerilog netlistnetlist to to
Mentor Graphics EDDM Mentor Graphics EDDM netlistnetlist formatformat–– Invoke Design ArchitectInvoke Design Architect--IC IC ((adk_daicadk_daic))–– On menu bar, select On menu bar, select File > Import File > Import VerilogVerilog
NetlistNetlist file: file: count4.v count4.v (the (the VerilogVerilog netlistnetlist))Output directory: Output directory: count4count4 (for the EDDM (for the EDDM netlistnetlist))Mapping file Mapping file $ADK/technology/$ADK/technology/adk_map.vmpadk_map.vmp
2.2. Open the generated schematic for viewingOpen the generated schematic for viewing–– Click Click SchematicSchematic in DAin DA--IC palette IC palette –– Select schematic in directory named above Select schematic in directory named above (see next slide)(see next slide)–– Click Click Update LVS Update LVS in the schematic palette to create a in the schematic palette to create a netlistnetlist to to
be used later by be used later by ““CalibreCalibre””3.3. Create design viewpoints for Create design viewpoints for ICstationICstation toolstools
–– adk_dveadk_dve count4 count4 ––t tsmc035 t tsmc035 ((V.PV.P’’ss: layout, : layout, lvslvs, , sdlsdl, tsmc035), tsmc035)Can also create gate/transistor schematics directly in Can also create gate/transistor schematics directly in DADA--IC using components from the ADK libraryIC using components from the ADK library
DADA--IC generated schematicIC generated schematic
EldoEldo simulation from DAsimulation from DA--ICIC
Run simulations from within DARun simulations from within DA--ICIC–– EldoEldo, , ADVanceADVance MSMS, , Mach TAMach TA
DADA--IC invokes a IC invokes a ““netlisternetlister”” to create a to create a circuit model from the schematiccircuit model from the schematic–– SPICE model for SPICE model for EldoEldo & & Mach TAMach TA
EldoEldo analyses, forces, probes, etc. same analyses, forces, probes, etc. same as SPICEas SPICEView results in View results in EZwaveEZwave or or XelgaXelga
EldoEldo input and output filesinput and output files
-Netlist-Simulation cmds-Stimulus
SPICE netlist for modulo7 counterSPICE “circuit” file generated by DA-IC
Force values (created interactively)
From ADKlibrary
EldoEldo simulation of modulo7 countersimulation of modulo7 counter(transient analysis)(transient analysis)
Create a stdCreate a std--cell based logic block cell based logic block in IC Stationin IC Station
Invoke: Invoke: adk_icadk_icIn IC Station palette, select:In IC Station palette, select: Create CellCreate Cell–– Cell name: Cell name: count4count4–– Attach library: Attach library: $ADK/technology/ic/process/tsmc035$ADK/technology/ic/process/tsmc035–– Process: Process: $ADK/technology/ic/process/tsmc035$ADK/technology/ic/process/tsmc035–– Rules file: Rules file: $ADK/technology/ic/process/tsmc035.rules$ADK/technology/ic/process/tsmc035.rules–– Angle mode: Angle mode: 4545–– Cell type: Cell type: blockblock–– Select Select With connectivityWith connectivity–– EDDM schematic viewpoint:EDDM schematic viewpoint: count4/layoutcount4/layout–– Logic loading options:Logic loading options: flatflat
Create Cell dialog boxCreate Cell dialog box
AutoAuto--””floorplanfloorplan”” the blockthe blockplace & route > place & route > autofpautofp
AutoAuto--place the std cellsplace the std cellsAutoplcAutoplc > > StdCelStdCel
AutoAuto--place place ““portsports”” ((AutoplcAutoplc > Ports)> Ports)Signal connections on cell boundariesSignal connections on cell boundaries
AutoRoute all netsAutoRoute all nets(hand(hand--route any route any unroutedunrouted ““overflowsoverflows””))
Then: Add > Port Text to copy port names from schematic – for Calibre
Layout design rule check (DRC)Layout design rule check (DRC)
TechnologyTechnology--specific design rules specify specific design rules specify minimum sizes, spacing, etc. of features minimum sizes, spacing, etc. of features to ensure reliable fabricationto ensure reliable fabrication–– Design rules file specified at startupDesign rules file specified at startup
Ex. Ex. tsmc035.rulestsmc035.rulesFrom main palette, select From main palette, select ICrulesICrules–– Click Click Check Check and thenand then OK OK in prompt boxin prompt box
(can optionally select a specific area to check)(can optionally select a specific area to check)
–– Rules checked in numeric orderRules checked in numeric order
Common errors detected by DRCCommon errors detected by DRC
To fix, click on To fix, click on FirstFirst in palette to highlight first in palette to highlight first error error –– Error is highlighted in the layoutError is highlighted in the layout–– Click Click ViewView to zoom in to the error (see next)to zoom in to the error (see next)–– Example: DRC9_2: Metal2 spacing = 3LExample: DRC9_2: Metal2 spacing = 3L–– Fix by drawing a rectangle of metal2 to fill in the gap Fix by drawing a rectangle of metal2 to fill in the gap
between contacts that should be connectedbetween contacts that should be connectedClick Click NextNext to go to next error, until all are fixedto go to next error, until all are fixed
NOTE: There can be no DRC errors if MOSIS is to NOTE: There can be no DRC errors if MOSIS is to fabricate the chip fabricate the chip –– they will run their own DRC.they will run their own DRC.
Error: DRC9_2 metal2 spacing = 3LError: DRC9_2 metal2 spacing = 3L
Draw rectangleof metal2to fill gap
It also called contact-to-contact metal 2 spacing DRC9 2 error
Layout Layout vsvs schematic checkschematic checkCalibreCalibre Interactive LVSInteractive LVS
From From ICstationICstation menu: menu: CalibreCalibre > Run LVS> Run LVS–– In popup, In popup, CalibreCalibre location: location: $MGC_HOME/../$MGC_HOME/../CalibreCalibre–– Rules: Rules: $ADK/technology/ic/process/tsmc035.calibre.rules$ADK/technology/ic/process/tsmc035.calibre.rules–– Input: Input: count4.src.net count4.src.net (previously created in DA(previously created in DA--IC)IC)–– HH--cells: cells: $ADK/technology/$ADK/technology/adk.hcelladk.hcell (hierarchical cells)(hierarchical cells)–– Extracted file: Extracted file: count4.lay.netcount4.lay.net
Compares extracted transistorCompares extracted transistor--level level netlistnetlist vs. vs. netlistnetlist saved in DAsaved in DA--ICIC
PostPost--layout parameter extractionlayout parameter extractionCalibreCalibre Interactive PEXInteractive PEX
Extract Spice Extract Spice netlistnetlist, including parasitic RC, including parasitic RC–– Simulate in Simulate in EldoEldo or or MachTAMachTAICstationICstation menu: menu: CalibreCalibre>Run PEX>Run PEX–– Options similar to Options similar to CalibreCalibre LVSLVS–– Extraction options:Extraction options:
lumped C + coupling caplumped C + coupling cap’’ssdistributed RCdistributed RCdistributed RC + coupling capdistributed RC + coupling cap’’ss
–– Output file: count4.pex.netlistOutput file: count4.pex.netlist
PostPost--layout simulation with layout simulation with MachTAMachTA
MachTAMachTA is an accelerated Spice simulatoris an accelerated Spice simulator–– Digital & mixedDigital & mixed--signal circuitssignal circuits–– Analyze timing effects preAnalyze timing effects pre-- and postand post--layoutlayout
SPICE SPICE netlistsnetlists with parasitic R/Cwith parasitic R/C
–– Execute test vector file to verify functionalityExecute test vector file to verify functionality
Algorithms support large designs Algorithms support large designs –– Partition design, simulate only partitions with changesPartition design, simulate only partitions with changes–– Combine timeCombine time--driven & eventdriven & event--driven operationdriven operation– Solves linearized models using a proprietary high-
performance, graph-theory based, matrix solution algorithm
Mach TA flow diagramMach TA flow diagram
SPICEnetlist
$ADK/technology/mta/tsmc035
PostPost--layout simulation with Mach TAlayout simulation with Mach TA((netlistnetlist extracted by extracted by CalibreCalibre PEX)PEX)
Prepare Prepare netlistnetlist (remove (remove subcircuitssubcircuits for Mach TA)for Mach TA)–– Extracted Extracted netlistnetlist = = count4.pex.netlistcount4.pex.netlist–– Command: Command: $ADK/bin/$ADK/bin/mta_prepmta_prep count4count4–– Creates SPICE file: Creates SPICE file: count4.spcount4.sp
Invoke Mach TA:Invoke Mach TA:anaana -- command file to initialize command file to initialize AnacadAnacad SWSWmtamta ––ezwezw ––t $ADK/technology/mta/tsmc035 count4.spt $ADK/technology/mta/tsmc035 count4.sp
Mach PA (mpa) does current & power analysis
Sample Mach TA Sample Mach TA ““dofiledofile””(transient analysis)(transient analysis)
plot plot v(clkv(clk) v(q[2]) v(q[1]) v(q[0])) v(q[2]) v(q[1]) v(q[0])measure rising TRIG measure rising TRIG v(clkv(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5vl loadl loadl resetl reseth counth countl l clkclkrun 5 nsrun 5 nsh reseth reseth h clkclkrun 5 nsrun 5 nsl l clkclkrun 5 nsrun 5 nsh h clkclkrun 5 nsrun 5 ns
Signals to observe in EZwave
Measure time from rising edge of clk (TRIGger)to 1st rising edge of q[0] (TARGet) - voltages
Drive signals low/high (Lsim format)
Simulate for 5 ns
Command to execute: dofile file.do
EZwaveEZwave waveform viewerwaveform viewer(results for previous (results for previous dofiledofile))
Double-clicksignal nameto display.
Alternative Mach TA Alternative Mach TA ““dofiledofile””(same result as previous example)(same result as previous example)
plot plot v(clkv(clk) v(q[2]) v(q[1]) v(q[0])) v(q[2]) v(q[1]) v(q[0])measure rising TRIG measure rising TRIG v(clkv(clk) VAL=2.5v RISE=1 TARG v(q[0]) ) VAL=2.5v RISE=1 TARG v(q[0])
VAL=2.5vVAL=2.5vvpulsevpulse VclkVclk clkclk 0 pulse(0 3.3 10n .05n 0 pulse(0 3.3 10n .05n .05n.05n 10n 20n)10n 20n)l loadl loadl resetl reseth counth countrun 5 nsrun 5 nsh reseth resetrun 200 nsrun 200 ns
Voltage source name
Nodes to whichsource connected
v-levels delay rise fall width period
Periodic pulses
Mach TA Mach TA –– test vector filetest vector file
Verify design functionality/behaviorVerify design functionality/behavior–– apply test vectorsapply test vectors–– capture outputscapture outputs–– compare outputs to expected resultcompare outputs to expected result–– vectors/outputs from behavioral simulationvectors/outputs from behavioral simulation
Command to execute a test vector file:Command to execute a test vector file:run run ––tvendtvend tvfile.tvtvfile.tv
test vector file (next slide)
Test vector file formatTest vector file format# Test vector file for modulo7 counter# Test vector file for modulo7 counterCODEFILECODEFILEUNITS UNITS pspsRISE_TIME 50RISE_TIME 50FALL_TIME 50FALL_TIME 50INPUTS clk,reset,load,count,i[2],i[1],i[0];INPUTS clk,reset,load,count,i[2],i[1],i[0];OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);CODING(ROM)CODING(ROM)RADIX <11113>3;RADIX <11113>3;@0 <01105>X;@0 <01105>X;@2000 <00105>0;@2000 <00105>0;@7000 <01105>0;@7000 <01105>0;@10000 <11105>5;@10000 <11105>5;@20000 <01015>5;@20000 <01015>5;@30000 <11015>6;@30000 <11015>6;@40000 <01015>6;@40000 <01015>6;@50000 <11015>0;@50000 <11015>0;@60000 <01015>0;@60000 <01015>0;……....ENDEND
Header
Vectors: @time <input_vector>expected_output
Sample 5 fs before next vector
signal order within vectors
Test vectors derived from behavioral simulation results
Vector format
Behavioral simulation listing Corresponding Mach TA test vector file
Alternate test vector fileAlternate test vector file(clock generated separately by voltage source)(clock generated separately by voltage source)
vpulse vclk clk 0 pulse(0 3.3 10n .5n .5n 10n 20n)
Can mix other simulationcommands with test vectorapplication.
Physical Design Physical Design -- FPGAFPGA
Map to FPGA LUTs, FFs, IOBs
Place & Route
Component-Level Netlist
Configuration File
Generate Programming
Data
Xilinx “ISE”Altera “Max Plus 2”
FPGA/PLD Technology
FilesUser-SpecifiedConstraints
Simulation Model
Generate Timing Model
Xilinx/Xilinx/AlteraAltera FPGA/CPLD DesignFPGA/CPLD DesignTechnology files & libraries for frontTechnology files & libraries for front--end design with end design with Mentor Graphics toolsMentor Graphics tools–– Schematic symbols for Schematic symbols for Design ArchitectDesign Architect–– Simulation models forSimulation models for QuicksimQuicksim II, II, QuicksimQuicksim ProPro–– Synthesis library for Synthesis library for LeonardoLeonardo
Vendor tools for backVendor tools for back--end design end design (map, place, route, configure, timing)(map, place, route, configure, timing)
–– Xilinx Xilinx Integrated Software EnvironmentIntegrated Software Environment (ISE)(ISE)–– AlteraAltera QuartusQuartus II & Max+Plus2II & Max+Plus2