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By-Abhinav VishnoiAssistant Professor

Lovely Professional University

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Whenever there are setup and hold time violations in any flip-flop, it

enters a state where its output is unpredictable: this state is known asmetastable state(quasi stable state).

Metastability can occur, if the setup (tSU), hold time (tH), or clock pulsewidth (tPW) of a flip-flop is not met.

A problem for asynchronous systems or events.

Three possible symptoms:

Increased CLK Q delay.

Output a non-logic level

Output switching and then returning to its original state.

Theoretically the amount of time a device stays in the metastable statemay be infinite.

At the end of metastable state, the flip-flop settles down to either '1' or'0'.

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metastable happen when two inputs such as dataand clock orclock and reset are changing at about the same time

The only safe way:

use a synchronizer

3

clk

d

Q (output)Meta-stable data

Setup & hold violation

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Reason for Metastability whenever setup and hold time violation

When the input signal is an asynchronous signal.

When the clock skew is too much (rise and fall time are more than thetolerable values).

When interfacing two domains operating at two different frequencies or atthe same frequency but with different phase.

When the combinational delay is such that flip-flop data input changes in the

critical window (setup+hold window).

To Avoid MetastabilityMake sure the clock period is long enough to allow for the result outTo add one or more successive synchronizing flip-flops to the synchronizer.

This approach allows for an entire clock period for metastable events in thefirst synchronizing flip-flop to resolve thems elvesion of quasi-stable states

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MTBF is Mean time between failure, Well MTBF gives us informationon how often a particular element will fail or in other words, it givesthe average time interval between two successive failures.

MTBF is a figure of merit related to metastability

Fin:Data FrequencyFclk:Clock FrequencyTd:Flip Flop critical time window (tsu+th)

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MTBF gives us information on how often a particular element will fail or it

gives the average time interval between two successive failures

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A flip-flop uses to synchronize two signals in this application cannot expectthe maximum delays stated in the data sheets

it is necessary to know how long to wait after the clock pulse before the datacan be evaluated.

A special test circuit is needed to determine the MTBF and the time (tx)

The clock signal (fCLK2) delayed by the time (tx) by delay line DL2

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it is possible to

determine thetime betweentwo failures asa function ofthe time (tx)

Semi-Logrithmicgraph

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Higher the frequency the lower is the probability that a metastablestate will occur the probability increases for lower frequencies

Metastable response of a component for any frequencies

settling time

Td and T describe the metastable response of the circuit

Constant T determines the slope of the lines

exp( * )

* *

T txMTBF

fclk fin td

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Family T/ns TdStd-TTL

0.74

2.9*10^-4

LS 0.7

4

4.8*10^-3

S 0.36

1.3*10^-9

ALS 1.0 8.7*10^-6

AS 4.0 1.4*10^3

F 9.2 1.9*10^8

BCT 1.51

1.14*10^-6

ABT 3.6

1

33*10^-3

HC 0.5 1.46*10^-6

Type of flip-flop SN74ALS74fin = 10 kHz / fclk = 25 MHz / tsu= 15 nsTd = 8.7 us

error rate is too much high

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To reduce MTBF use circuit that exhibit a much shorter settling timethat leave the metastable state faster. For SN74AS series in which theconstant (T) is high

fin = 10 kHz / fclk = 25 MHz / tsu = 15 ns / Td =1.4*10^3 / T= 4.0

exp(4* 25 )

25 *10 *1.4*10 ^ 3

nsMTBF

MHz KHz

mean time between two failures (MTBF) is 2.4 x 10^21years

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Adding a second Flip Flop to the design will reduce the chance of theoutput going Metastable.

The output from the first flip flop may go valid before the second flipflop is clocked.

It connect asynchronousinput to the rest of system

Whenever there is signal transfer between two systems operating atdifferent frequencies or same frequency with different phases,synchronizer is used as an interface so that signal from transmitterblock is reliably interpreted by the receiver.

This block ensures that there is no metastability for a target MTBF.There are two inputs the clock C and theasynchronous signal D and one outputthe synchronised signal D.The two input signals interactasynchronously modelled roughly byoperating frequencies f1 and f2

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A simple synchronizer comprises two flip-flops in serieswithout any combinational circuitry between them. Thisdesign ensures that the first flip-flop exits its metastablestate and its output settles before the second flip-flopsamples it

The synchroniser is expected to provide a defined logic level(0 or l within a bounded decision time after D otherwise asynchronisation failure has occured.

http://photos1.blogger.com/blogger/6758/632/1600/clip_image002.gif

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The second flip-flop receives the output signal of the first stage after oneclock period and can go into a metastable state only if its input conditionsare violated.

the output of the first flip-flop is still metastable during its setup and holdtime. So the critical input frequency fin(2) of the second stage is calculated

from the reciprocal of the mean time between two failures of the first stage:

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one SN74ALS74 flip-flop, the MTBF was 54 minutes. Again, assumingthat the second flip-flop is sampled after 25 ns

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Mean Time Between Failure (MTBF) of a particular flip-flop in the context of a

given clock rate and input transition rate is 33.33 seconds then the MTBF oftwo such flip-flops used to synchronize the input would be (33.33* 33.33) =18.514 Minutes