Method of Implementation (MOI) MIPI C-PHY v2.0 HS-TX/RX ......TX) - [HS-RX] Differential Return Loss...

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Method of Implementation (MOI) MIPI C-PHY v2.0 HS-TX/RX Interface Conformance Tests Using Keysight Network Analyzer with Enhanced TDR App

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Table of Contents

1. Revision History ............................................................................................................................................ 3

2. Configuration Requirements ......................................................................................................................... 3

3. Test Procedure .............................................................................................................................................. 4

3.1 Test Flow Chart ...................................................................................................................................... 4

3.2 Test Port Cable and DUT Connection .................................................................................................... 5

3.3 Description of Measurement Window ..................................................................................................... 5

4. Measurement Setups .................................................................................................................................... 6

4.1 Recalling a State File .............................................................................................................................. 6

4.2 Perform Calibration Setup ...................................................................................................................... 8

4.2.1. ECal Calibration and De-embedding .............................................................................................. 8

5. Measurement and Data Analysis ................................................................................................................ 12

5.1. [HS-TX] Differential Return Loss (SddTX) ............................................................................................ 12

5.2. [HS-TX] Common-Mode Return Loss (SccTX) ..................................................................................... 13

5.3. [HS-TX] Single-Ended Output Impedance (ZOS).................................................................................. 13

5.4. [HS-TX] Single-Ended Output Impedance Mismatch (ΔZOS) ............................................................... 14

5.5. [HS-RX] Differential Return Loss (SddRX) ............................................................................................ 14

5.6. [HS-RX] Common-Mode Return Loss (SccRX) .................................................................................... 15

5.7. [HS-RX] Mode Conversion Limits (SDC11) ......................................................................................... 16

5.8. [HS-RX] Differential Input Impedance (ZID) ......................................................................................... 16

5.9. [HS-TX] Differential Input Impedance Mismatch (ΔZID) ....................................................................... 17

5.10. [HS-TX] Single-Ended Output Impedance Unterminated (ZOS(UT)) .................................................... 17

5.11. [HS-TX] Single-Ended Output Impedance Mismatch Unterminated (ΔZOS(UT)) ................................. 18

6. Manual Setup .............................................................................................................................................. 19

6.1. Defining Limit Line Tables ................................................................................................................... 19

Web Resources .............................................................................................................................................. 20

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1. Revision History

Revision Comments Date

1.0 First draft for E5080B series 5-Aug-2020

Reference Documents

1. Conformance Test Suite for C-PHY Specification v2.0, CTS Version 1.0 Release 03

2. Configuration Requirements

Description Test Equipment Qty

Network Analyzer Keysight Network Analyzer:

• E5080B-2x0/4x0: 2-port or 4-port test set, 9 kHz

to 6.5, 9, 14 or 20 GHz1

Note: Ensure that E5080B firmware revision is

at least version A.14.10 or above.

1 ea.

Software S96011B Enhanced time-domain analysis with TDR 1 ea.

ECal or Mechanical

Cal Kit

N4431D-010 or N4433D-010/0DC 4-Ports Electronic

Calibration (ECal) Module or 85052D Economy

Mechanical Calibration Kit

1 ea.

Adapter • 3.5mm(f)-Type N(m) adapters (Keysight 1250-

1744) for E5080B with type-N(f) connectors.

• SMA(f)-SMA(f) adapters (Keysight 1250-1666)

for E5080B with 3.5-mm(m) connectors.

4 ea.

RF cable 3.5 mm or SMA cables of 6 GHz bandwidth or more 4 ea.

1. Note: The required max frequency is 6 GHz for frequency-domain measurements (ex. Sdd11). Rise

time and BW should be sufficient to perform the time-domain (impedance) measurements, so higher

frequency options of E5080B are recommended for better time-domain resolutions.

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3. Test Procedure

3.1 Test Flow Chart

Note:

1. Hard Keys are displayed in Blue color and Bold. (Example: Avg, Analysis)

2. Soft keys (Keys on the screen) are displayed in Bold. (Example: S11, Real, Transform)

3. Buttons (in the TDR) are displayed in Green color and Bold. (Example: Trace, Rise Time)

4. Tabs (in the TDR) are displayed in Brown color and Bold. (Example: Setup, Trace Control)

1Set measurement conditions by recalling a state file or manual setup.

2Connect matched 3.5 mm or SMA cables to the test ports of the instrument.

3

For Time Domain Measurements, perform Electronic Calibration (ECal) or Deskew & Loss Compensation and adjust the rise time on each trace.

4

For Frequency Domain Measurements, perform Electronic Calibration (ECal) at the 3.5 mm or SMA cables for port 1 and port 2.

5

Perform Time Domain Measurements

- [HS-TX] Single-Ended Output Impedance (ZOS)

- [HS-TX] Single-Ended Output Impedance Mismatch (ΔZOS)

- [HS-RX] Differential Input Impedance (ZID)

- [HS-RX] Differential Input Impedance Mismatch (ΔZID)

- [HS-TX] Single-Ended Output Impedance Unterminated (ZOS(UT))

- [HS-TX] Single-Ended Output Impedance Mismatch Unterminated (ΔZOS(UT))

6

Perform Frequency Domain Measurements

- [HS-TX] Differential Return Loss (SddTX)

- [HS-TX] Common-Mode Return Loss (SccTX)

- [HS-RX] Differential Return Loss (SddRX)

- [HS-RX] Common-Mode Return Loss (SccRX)

- [HS-RX] Mode Conversion Limits (SDC11)

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3.2 Test Port Cable and DUT Connection

Test cables are connected with the test port 1 & 2 of the E5080B, and the DUT’s interface.

3.3 Description of Measurement Window

The following figure is the description of the measurement window.

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Actual measurement windows in the state file

4. Measurement Setups

4.1 Recalling a State File

This section describes how to recall a state file for Time Domain and Frequency Domain settings.

A state file can be downloaded from Keysight.com at the following URL.

www.keysight.com/find/ena-tdr_compliance

If you use your local PC to download, save the state file to a USB mass storage device in order to move it

to the VNA unit. Connect the USB mass storage device into the front USB port of the VNA unit.

For manual measurement settings, refer to Chapter 6.0 Appendix for manual setup procedure.

1. Click Setup > Main > Meas Class… to launch measurement class setup dialog box

2. Select TDR and click OK.

http://www.keysight.com/find/ena-tdr_compliance

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3. Select Close and confirm with Yes to close the setup wizard.

4. Select Click Advanced Mode of TDR software and Click Yes to enter the advanced mode.

5. Click File > Recall State. Select the state file (*.tdr) and click Open to recall.

6. The windows will launch pre-define state file configuration for MIPI C-PHY Conformance test.

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7. All the measurement settings including calibration information can be saved.

Click File > Save State and save TDR state file (*.tdr) with measurement settings.

4.2 Perform Calibration Setup

The purpose of this step is to calibrate the RF effects such as delay, loss or mismatch of RF cables and

test fixture traces before measurements. In order to remove the fixture trace effect, the de-embedding

function is available with the VNA firmware.

4.2.1. ECal Calibration and De-embedding

Full calibration is performed by using the 2- or 4-port ECal Module (i.e. N4433D) at the end of RF cables

connected to the VNA’s test ports. The effect of the fixture is removed by de-embedding the fixture traces

with S-parameter Touchstone files.

Time-Domain Calibration - ECal calibration and de-embedding for time-domain measurements are

performed by the TDR software.

ECal Calibration on Time Domain:

1. Press Channel > Channel 1-8 > Channel 1 o select Channel 1.

2. Click Setup tab.

3. Click ECal to launch the TDR Setup Wizard.

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4. Connect the VNA ports (port 1 to 2) to the ECal module with RF cables.

5. Click Calibrate to perform ECal Calibration.

6. Click Next > to proceed

7. Click Finish to complete the ECal.

De-embedding on Time Domain:

1. Click Adv Waveform tab > De-embedding to launch Advanced Waveform wizard.

2. Click De embedding box to set the Touchstone file. 2 port files (*.s2p) for single ended lines or 4 port

files (*.s4p) for differential lines can be selected for the de embedding function.

3. Load the Touchstone file.

4. Enable the de-embedding function and Click OK.

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Note: For more details about the de-embedding function, refer to the VNA help below.

http://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#dee

mbed

Frequency-Domain Calibration- ECal calibration and de-embedding for frequency-domain

measurements are performed by the VNA firmware.

ECal Calibration on Frequency Domain:

1. Press Channel > Channel 1-8 > Channel 2 to select Channel 2.

2. Connect the VNA ports (Port 1 to 2) to the ECal module with RF cables.

3. Press Cal > Main > Other ECal > Ecal… > select 2-Port ECal and click Next to proceed

De-embedding on Frequency Domain (For 2-Ports File):

1. Press Cal > Fixtures > Fixture Setup > 2-port DeEmbed…and check on Enable De-embedding

(all ports) to de-embed fixture trace.

2. Select User S2P File and specify a 2-port de-embedding file (*.s2p).

3. Continue the same for the other ports of the VNA.


2-Port De-embedding -

http://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#deembed

http://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#deembedhttp://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#deembedhttp://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#deembed

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De-embedding on Frequency Domain (For 4-Ports File):

1. Press Cal > Fixtures > Fixture Setup > N-port DeEmbed…and check on Enable De-embedding

(all ports) to de-embed fixture trace.

2. Select Topology > A.

3. Select User S2P File and specify a 4-port de-embedding file (*.s2p).


4/6/8-Port De-embedding -

http://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#4-

PortEmbed

http://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#4-PortEmbedhttp://ena.support.keysight.com/e5080/manuals/webhelp/eng/index.htm#S3_Cals/Fixturing.htm#4-PortEmbed

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5. Measurement and Data Analysis

1. Connect the DUT to the test port cables from port 1 and port 2. 2. Press Channel > Channel 1-8 key on the instrument front panel to select Channel 1 (Time Domain

measurements) or Channel 2 (Frequency Domain measurements). 3. Click Stop Single for Time Domain measurements. 4. Press Trigger > Single for Frequency Domain measurements.

5.1. [HS-TX] Differential Return Loss (SddTX)

This test ensures that the Differential Return Loss of the DUT’s HS transmitters exceeds the minimum

conformance limits.

1. Power on and configure the DUT to force its HS-TX into a fixed HS state, transmitting a continuous

HS pattern on all Lanes. Set the signaling rate to the maximum symbol rate supported by the DUT.

2. Connect the DUT’s Lane 0 transmitter to the Test System (A-B pair).

3. Press Channel > Channel 1-8 > Channel 2 to select Channel 2.

4. Press Trace > Trace 8-15 > Trace 9 to select Trace 9.

5. Double-click on the instrument’s screen to enlarge the trace.

6. Press Trigger > Single.

7. Run and confirm the measured values are below the minimum limit shown below.

fLP, MAX fh fMAX

SddTX (dB): 2.5 Gsps and 4.5 Gsps -15 -1 -0.5

Where

• fMAX = 3/4 * symbol rate

• fh = fundamental frequency of the operating symbol rate (ex. fh= 500 MHz for a 1 Gsps symbol rate)

• fLP, MAX = 10 MHz

8. Repeat the previous steps for the B-C and C-A pairs.

9. Repeat the previous steps for all other Lanes.

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5.2. [HS-TX] Common-Mode Return Loss (SccTX)

This test ensures that the Common-Mode Return Loss of the DUT’s HS transmitters exceeds the minimum

conformance limits.

1. Obtain the value of fMAX for the DUT that was used in 5.1.


HS pattern on all Lanes. Set the signaling rate to the maximum symbol rate supported by the DUT.


4. Press Channel > Channel 1-8 > Channel 2 select Channel 2.

5. Press Trace > Trace 8-15 > Trace 10 to select Trace 10.



8. Run and confirm the measured values is less than -0.5 dB from fLP,MAX (=10 MHz) up to fMAX.



5.3. [HS-TX] Single-Ended Output Impedance (ZOS)

This test ensures the Single-Ended Output Impedance (ZOS) of the DUT’s HS transmitters is within the

conformance limits.


HS pattern on all Lanes. Set the signaling rate to 500 Msps or below.

2. Connect the DUT’s Lane 0 transmitter to the Test System.


4. Select Trace 1 (T11).


6. Click Stop Single

7. Measure ZOS for the VA pin. Read the marker value (impedance in ohm) on upper right corner of the

window.

Note: The marker is placed at 4 nsec by default. If the DUT response is not stable around the marker

at 4 nsec, adjust the marker position and horizontal scale.

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8. Repeat the previous steps for the VB and Vc pins.

9. Repeat the previous steps for all other Lanes. For all Lanes, verify the ZOS is between 40 and 60

ohms for the VA, VB and Vc pins.

5.4. [HS-TX] Single-Ended Output Impedance Mismatch (ΔZOS)

This test ensures the Single-Ended Output Impedance Mismatch (ΔZOS) of the DUT’s HS transmitter is

within the conformance limits. ΔZOS is the mismatch of the single ended output impedances at the A, B

and C pins, denoted by ZOS_A, ZOS_B and ZOS_C, respectively. This mismatch is defined as the ratio of the

difference between the largest and smallest value of ZOS_A, ZOS_B and ZOS_C and the average of those

impedances:

ΔZOS is computed for each Lane from the measured ZOS values obtained in 5.3. For all Lanes, a

computed ΔZOS value less than 10% is conformant.

1. Obtain the ZOS values for each Lane from 5.3. Click Marker Search and select Max or Min to search

for the largest or smallest impedance value of ZOS_A, ZOS_B or ZOS_C.

2. For each Lane, compute ΔZOS and verify that ΔZOS is less than 10%.

5.5. [HS-RX] Differential Return Loss (SddRX)

This test ensures that the Differential Return Loss of the DUT’s HS receivers exceeds the minimum

conformance limits.


2. Power on and configure the DUT to force its RX into fixed state where the HS-RX termination is

enabled.

3. Connect the DUT’s Lane 0 receiver to the Test System (A-B pair).


5. Press Trace > Trace 8-15 > Trace 9 to select Trace 9 (Sdd11).



8. Run and confirm the measured values are below the minimum limit shown below.

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0 fLP, MAX fh fMAX

SddRX (dB): 2.5 Gsps and 4.5 Gsps -15 -15 -2.8 -1.5

Where

• fMAX = 3/4 * symbol rate

• fh = fundamental frequency of the operating symbol rate (ex. fh= 500 MHz for a 1 Gsps symbol rate)

• fLP, MAX = 10 MHz



5.6. [HS-RX] Common-Mode Return Loss (SccRX)

This test ensures that the Common-Mode Return Loss of the DUT’s HS receivers exceeds the minimum

conformance limits.


2. Power on and configure the DUT to force its RX into a fixed state where the HS-RX termination is

enabled.



5. Press Trace > Trace 8-15 > Trace 10 to select Trace 10 (Scc11).



8. Run and confirm the measured Scc11 values are below the minimum limit shown below.

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0 ¼ fINT,MIN fINT,MIN fMAX

SccRX (dB): 2.5 Gsps and 4.5 Gsps 0 0 -6 -1.5

Note: The value of FINT,MIN is specified as a fixed value of 450 MHz.



5.7. [HS-RX] Mode Conversion Limits (SDC11)

This test ensures that the Mode Conversion S-parameters of the DUT’s HS receivers exceed the

minimum conformance limits.


2. Power on and configure the DUT to force its RX into a fixed state where the HS-RX termination is

enabled.



5. Press Trace > Trace 8-15 > Trace 11 to select Trace 11 (Sdc11).



8. Run and confirm the measured Sdc11 values are lower than -26 dB over the frequency range from

minimum frequency up to fMAX.



5.8. [HS-RX] Differential Input Impedance (ZID)

This test ensures that Differential Input Impedance (ZID) of the DUT’s HS-RX line termination is within the

conformance limits.

1. Power on and configure the DUT to force its RX into fixed state where the HS-RX termination is

enabled.

2. Connect the DUT’s Lane 0 transmitter to the Test System (pair A-B).


4. Select Trace 3 (Tdd11).



7. Measure ZID. The value of ZID is measured as the final, settled value of the differential impedance

profile. Read the marker value (impedance in ohm) on upper right corner of the window.

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8. Repeat the previous steps for the B-C and C-A pairs to measure ZID_BC and ZID_CA.

9. Repeat the previous steps for all other Lanes. For all Lanes, verify the ZID_AB, ZID_BC and ZID_CA are in

the range of 80 to 120 ohms.

5.9. [HS-TX] Differential Input Impedance Mismatch (ΔZID)

This test ensures the Differential Input Impedance Mismatch (ΔZID) of the DUT’s HS receiver is within the

conformance limits. ΔZID is the mismatch of the differential input impedances of the receiver for A-B, B-C

and C-A pairs, denoted by ZID_AB, ZID_BA and ZID_CA, respectively. This mismatch is defined as the ratio of

the difference between the largest and smallest value of ZID_AB, ZID_BC and ZID_CA and the average of those

impedances:

ΔZID is computed for each Lane from the measured ZID values obtained in 5.8. For all Lanes, a computed

ΔZID value less than 10% is conformant.

1. Obtain the ZID values for each Lane from 5.8. Click Marker Search and select Max or Min to search

for the largest or smallest impedance value of ZID_AB, ZID_BC or ZID_CA.

2. For each Lane, compute ΔZID and verify that ΔZID is less than 10%.

5.10. [HS-TX] Single-Ended Output Impedance Unterminated (ZOS(UT))

This test ensures the Single-Ended Output Impedance in HS Unterminated Mode (ZOS(UT)) of the DUT’s

HS transmitters is within the conformance limits.

Note that the test is applicable for the HS Unterminated Mode. This test should be performed only on

DUTs that have implemented the HS Unterminated Mode.


HS pattern on all Lanes.

2. Connect the DUT’s Lane 0 transmitter to the Test System.


4. Select Trace 1 (T11).



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7. Measure ZOS(UT) for the VA pin. Read the marker value (impedance in ohm) on upper right corner of

the window.

Note: The marker is placed at 4 nsec by default. If the DUT response is not stable around the marker

at 4 nsec, adjust the marker position and horizontal scale.

8. Repeat the previous steps for the VB and Vc pins.

9. Repeat the previous steps for all other Lanes. For all Lanes, verify the ZOS(UT) is between 40 and 60

ohms for the VA, VB and Vc pins.

5.11. [HS-TX] Single-Ended Output Impedance Mismatch Unterminated (ΔZOS(UT))

This test ensures the Single-Ended Output Impedance Mismatch Unterminated (ΔZOS(UT)) of the DUT’s

HS transmitter is within the conformance limits. ΔZOS(UT) is a device’s High-Speed Single-Ended Output

Impedance Mismatch in HS Unterminated Mode. The definition of ΔZOS(UT) in the Tx HS Unterminated

Mode is the same as ΔZOS (of 5.4) in the normal terminated mode of operation. The only difference is the

termination at the receiver.

The mismatch of the single ended output impedances at the A, B and C pins, denoted by ZOS_A, ZOS_B and

ZOS_C, respectively. This mismatch is defined as the ratio of the difference between the largest and

smallest value of ZOS_A, ZOS_B and ZOS_C and the average of those impedances:

ΔZOS(UT) is computed for each Lane from the measured ZOS(UT) values obtained in 5.10. For all Lanes, a

computed ΔZOS value less than 10% is conformant.

Note that this test is applicable for the HS Unterminated Mode. This test should be performed only on

DUTs that have implemented the HS Unterminated Mode.

1. Obtain the ZOS(UT) values for each Lane from 5.10. Click Marker Search and select Max or Min to

search for the largest or smallest impedance value of ZOS_A, ZOS_B or ZOS_C.

2. For each Lane, compute ΔZOS(UT) and verify that ΔZOS(UT) is less than 10%.

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6. Manual Setup

The procedures of manual setup for time-domain and frequency domain measurements are introduced in

this section for reference.

6.1. Defining Limit Line Tables

1. Press Trace to select trace to set the limit line table.

2. Press Math> Analysis > Limit Table > to edit the limit table.

3. Press Math> Analysis > Limit… > to launch Limit Test Setup window.

4. Select to turn on “Limit Test ON” and “Limit Line ON”, optional to turn on “Sound ON Fail”.

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Learn more at: www.keysight.com

For more information on Keysight Technologies’ products, applications or services,

please contact your local Keysight office. The complete list is available at:

www.keysight.com/find/contactus

This information is subject to change without notice. © Keysight Technologies, 2020, Published in USA, August 19, 3120 -1455.EN

Web Resources

www.keysight.com/find/ena-tdr_compliance

www.keysight.com/find/usb-vna

www.keysight.com/find/na

www.keysight.com/find/vnasoftware

www.keysight.com/find/ecal
http://www.keysight.com/find/ena-tdr_compliancehttp://www.keysight.com/find/ena-tdr_compliancehttp://www.keysight.com/find/usb-vnahttp://www.keysight.com/find/nahttp://www.keysight.com/find/vnasoftwarehttp://www.keysight.com/find/ecal

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