Compiler is a quite complex software packageCompilers must be particularly reliableTranslation of source code into machine independent intermediate representation (IR)Design requires separation into multiple phasesCompiler is followed by Assembler, LinkerBackend: mapping machine indepent IR to machine dependent asm + machine dependent optimizations
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RetargetableRetargetable CompilersCompilers
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RetargetableRetargetable Compilers Compilers –– Main GoalsMain Goals
Adapt to new processors having a single tool for an entire class of target machinesSupport for design space exploration by editing the target processor model Tradeoff retargetability/code quality: Realistic retargetable compilers focus on a specific class of processor architectures
Def.: A compiler is called retargetable, if it can be modified to generate assembly code for different architectures, while reusing the largest part of the compiler source code.
Main goals:provide a semi-automatic platform for reconfigurable computing. support the entire design process (rather than isolated parts).targets uni-processor architectures with reconfigurable units (the current version exploit a PPC core processor augmented with an FPGA)
These require the development of:programming models (MOLEN)a retargetable compilers for reconfigurable platforms.introduction of hardware software co-design speculations.CAD and design space exploration.
The ISA is extended with 8 instructions6 instructions are required for controlling the reconfigurable hardware2 instructions are required for controlling the reconfigurable hardware
This mean that to call a FPGA function the compiler must insert code to:
SET the function“send” input parameters to the FPGAcall the EXECUTE on the FPGA“move” output values back from exchange registers
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Re-targeted
Compiler
BinaryCode SimpleScalar
PerformanceStatistics
FPGA
…
…
Code
int fact(int n){if(n<1) return nelsereturn(n*fact(n-1));}
f(.)
Human Directives
call f(.) HDL
Architecture
REVISE
HDL
C2C
NO
Part I
Part II
Part III
Delft WorkbenchDelft WorkbenchWorkflowWorkflow
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Generating executable code: Once a function f(.) is identified, the code containing the f(.) logic is eliminated from the source code and replaced by an appropriate FPGA call, together with the appropriate instructions for setting up the FPGA and to start its computation.
Delft WorkbenchDelft WorkbenchThe The retargetableretargetable compilercompiler
The basic idea is to postpone the decision of whether executing a task in HW or in SW moving it at run-time
This will be done not for every task, because of code memory overhead, but only where is not possible to take a wise choice at design or compile-time
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LimboWARELimboWARE: : WhenWhen -- WhereWhere
Compile-time Unbounded number of executionIf n is a number known only at run-time. The limbo choice is wiser than the corresponding one done at compile time (without this information)for(i=0; i<n; i++){
function();
}
Execution trace dependent choice between HW and µ-code
Functionality already in HW (past)Functionality that in this branch will be used many times (constrained future)
If the path is 1-3-5-6 the predicate P is TRUE, is executed in HW and the relative µ-code for the SW execution is skipped, by branching after If the path is 2-4-5-6, the predicate P is FALSE, HW_CALL and JMP are not executed and the µ-code for is executed
Integrating and adapting HW/SW codesign methodology to reconfigurable HW scenario Integration of the DRESD reconfigurable HW architecture (YaRA)Introduction of LimboWare mechanismsDevelopment of a retargetable compiler for reconfigurable hardware
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VIRGIL: VIRGIL: MainMain stepssteps
HW/SW partitioning
LimboWare code analysis
Compile the source code including special LimboWaredirectives
Synthesis and Mapping of the HDL (generated in the first 2 steps) to the Reconfigurable Hardware
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VIRGIL: VIRGIL: WorkflowWorkflow
HLR
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VIRGIL: The VIRGIL: The CompilerCompiler
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VIRGIL: The architectureVIRGIL: The architectureYaRA YaRA -- FPGA LayersFPGA Layers
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VIRGIL: VIRGIL: NeedsNeeds
Development of a retargetable compiler for reconfigurable HW integrating LW functionalities.Integrating and tailoring HW/SW codesignmethodologies to reconfigurable hw and LW.Identification of LimboWare and critical function detectionWHAT in the code will be translated -> metricsDefinition of metrics of source code for SW/LW partitioning and development of the relative tools.
