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MICE CM18 June 07 Jean-Sébastien Graulich Slide 1
Detector DAQ StatusDetector DAQ Status
o Since CM17
o Detector DAQ software
o Front End Electronics
o Schedule Milestones
o Summary
Jean-Sebastien Graulich, Geneva
MICE CM18 June 07 Jean-Sébastien Graulich Slide 2
Since CM17Since CM17
DAQ architecture revisionDAQ architecture revision DAQ Software Development: DATE is DAQ Software Development: DATE is
runningrunning Readout code for TDC V1290 and Trigger Receiver
(V977) Test bench is taking TDC V1290 data in multi-
event mode with faked spill structure
Shaper production prototypeShaper production prototype Assembled in Sofia Tested in Geneva
Splitter prototype testedSplitter prototype tested
MICE CM18 June 07 Jean-Sébastien Graulich Slide 3
DAQ Architecture DAQ Architecture revisionrevision
Local Storage (3 TB) Local Storage (3 TB)
inside the Event Builderinside the Event Builder
RAL Net
MICE Main 1GB Switch
Control & Monitoring
100 MB Switch
MICE DAQ 1GB Switch
User PCs and Wi-Fiin Local Control Room
EPICS network for MICEControl and Monitoring (MCM)
Trigger distribution
Trackers EMCal TOF Trigger + Ckovs
Event Builder(GDC)
Run Control
Dedicated Link to Remote Mass Storage
VME Crates
Optical links
Linux PCs(LDCs)
MCMReadout
Data Saver
Online Monitoring
MICE Private Subnet
RAL Net
MICE Main 1GB Switch
Control & Monitoring
100 MB Switch
MICE DAQ 1GB Switch
User PCs and Wi-Fiin Local Control Room
EPICS network for MICEControl and Monitoring (MCM)
Trigger distribution
Trackers EMCal TOF Trigger + Ckovs
Event Builder(GDC)
Run Control
Dedicated Link to Remote Mass Storage
VME Crates
Optical links
Linux PCs(LDCs)
MCMReadout
Data Saver
Online Monitoring
MICE Private Subnet
All the hardware for All the hardware for
stage I in handstage I in hand
MICE CM18 June 07 Jean-Sébastien Graulich Slide 4
DATE VocabularyDATE Vocabulary
LDC : Local Data ConcentratorLDC : Local Data Concentrator The PC connected to the VME crate via the PC-VME
Interface GDC : Global Data CollectorGDC : Global Data Collector
Event Builder Trigger ReceiverTrigger Receiver
IO Register (with several inputs), present in each VME crate, receiving the signal informing the LDCs that something has happened, e.g the spill is finished and the data should be readout (= Physics Trigger). It also handles busy signals.
Event TypeEvent Type Tag attached to the event depending on which trigger
receiver‘s input has received a signal EventEvent
DATE Event == DAQ Event !!! A Physics Event contains data for several Particle Events (about 600)
MICE CM18 June 07 Jean-Sébastien Graulich Slide 5
Particle Trigger Particle Trigger RevisionRevision
The timing of the trigger should be given by the The timing of the trigger should be given by the burstburst
Delay TOF0, TOF1 TOF2 such that they arrive approximately at the same time in the trigger logic
Make the TOF logic pulses ~200 ns long Make the Burst Gate narrow and Delay it such that it arrives
more than 100 ns after the TOF signals
All single raw time distribution will be ~ 100 ns All single raw time distribution will be ~ 100 ns widewide
TOF1
Burst Gate
TOF0
TOF0 TOF1 Burst Gate
200 ns
17 -Twisted PairsFlat cable, 96 OhmsSingle ended
RC shaper16 channels
Special Flat cable Only ten pairs connectedon a 17-pairs connector
TOF_0_L0
TOF_0_L9 TOF_0_U0
TOF_0_U5 Lecroy 4415Discriminator16 channels
17 -Twisted PairsFlat cable to Tdc
. .
. .
. .
. .
16 x ~6 ns special cablesto Flash ADC
17 -Twisted PairsFlat cable, 96 OhmsSingle ended
RC shaper16 channels
TOF_0_R0
TOF_0_R9 TOF_0_D0
TOF_0_D5
Lecroy 4415Discriminator16 channels
17 -Twisted PairsFlat cable to Tdc
. .
. .
.16 x ~6 ns special cablesto Flash ADC
Lecroy Logic unit
A
B
Same picture for TOF_2_L and TOF_2_R
ECL
ECL
Simplified picture for the 5th Splitter for the remaining channels of TOF0 and TOF2 (No Logic board)
Similar picture for TOF_1_L and TOF_1_R (only 14 channels used)
NIM logic from here
LEFT Pmts
RIGHT Pmts
2 by 2 coincidence
OR of 10 slabs
UP and DOWN Pmts are not used
for the trigger
MICE CM18 June 07 Jean-Sébastien Graulich Slide 7
Selection of Particle Selection of Particle Trigger ConditionTrigger Condition
Example: Example: Oreg1-4 = 0 : Clock trigger
Oreg1-4 = 1 : Burst Gate TOF0 TOF1 TOF2 DS Burst Gate
SW Controlled Clock
OReg4
TOF0
TOF1
TOF2 Particle TriggerRequest
FEEBusy
Particle Trigger
Downscale
1/128OReg3
Burst Gate
OReg0
OReg1
OReg2
DT-Gate
MICE CM18 June 07 Jean-Sébastien Graulich Slide 8
DAQ Trigger DesignDAQ Trigger Design
DAQ is designed to allow sub-detectors DAQ is designed to allow sub-detectors to take local Calibration Events in to take local Calibration Events in between spillsbetween spills
Double care is taken to keep Double care is taken to keep synchronization between LDCssynchronization between LDCs
Possible cause for de-synchronization DAQ trigger arrives while one LDC is still busy
with the readout of the previous (quite easy to avoid)
One DAQ trigger is lost in transmission (unpredictable)
Design such that any misalignment is Design such that any misalignment is detected right awaydetected right away
MICE Ready
Target Ready
RF Ready
DAQ Ready
Gated Machine Start
Spill Request
Target Trigger
Protons on target
RF Trigger
RF Power
DT Gate
DAQ Trigger
Target Delay
RF Delay
DT Delay
20 ms Extraction
Validated Machine Start
MICE Systems synchronization MICE Systems synchronization (Updated)(Updated)
MICE CM18 June 07 Jean-Sébastien Graulich Slide 10
Flexibility Flexibility requirementrequirement
There should be a safe way to There should be a safe way to bypass the synchronization bypass the synchronization procedure. E.g.procedure. E.g.
DAQ running without beam Target tests when DAQ is off Etc
The bypass mechanism should be The bypass mechanism should be under central controlunder central control
MICE CM18 June 07 Jean-Sébastien Graulich Slide 11
Bypass Logic Bypass Logic SchemeScheme
DAQ Ready
RF Ready
Target Ready
OReg5
OReg6
OReg7
MCM ReadyOReg8
GMS
Start of Spill Trigger
Target Trigger
RF Trigger
A small stand alone application will allow setting A small stand alone application will allow setting OReg5-9 of the trigger selection module in the central OReg5-9 of the trigger selection module in the central Trigger VME crateTrigger VME crate
At Start of Run, the DAQ will check these registers and At Start of Run, the DAQ will check these registers and send warnings if one is setsend warnings if one is set
VMS Target System
OReg9
1Hz Clock
Delay
Fixed delay ~ few ms
Fixed delay
Software Check: No overlap with SOS busy (otherwise stop with error)
Depends on Data Size ~ 1 s
VMS
Particle Triggers
Fixed width ~ 1 ms
Physics Event DAQ Trigger
Fan out to LDCs
Fan out to LDCs
Fan out to LDCs
EOS Trigger
SOS Trigger
DAQ Idle = DAQ Ready
DAQ trigger distributionDAQ trigger distribution
Target Trg
Trigger ReceiverConnections
V977
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Common toall LDCs
Central trigger only
All PE Busy
All CALIB Busy
All SOS Busy
All EOS Busy
DT Gate
PE DAQ Trigger
CALIB Trigger
SOS trigger
EOS Trigger
PE Local Busy
CALIB Local Busy
SOS Local Busy
EOS Local Busy
DAQ Idle
2 spares
In Out
Ireg0
Oreg0 = Ireg1
Oreg1
Reset by software as soon as the trigger is seen
Reset by software as soon as the readout is done
CAEN V977
Channels 0-7 configured as Flip-Flop, reset by software
MICE CM18 June 07 Jean-Sébastien Graulich Slide 14
Front End Front End ElectronicsElectronics
Shaper Production prototypeShaper Production prototype 1 PCB board designed, drawn and produced in
Sofia Fully equipped manually in Sofia
4 channels with 4 stages of filtering 12 channels with 2 stages of filtering Different gains A jumper allow choosing Single-ended (for TOF) or
differential (for EMCal) inputs
All channels fully operationalAll channels fully operational Tested for Tested for
Internal Noise OK (~ 400 V RMS) Gain stability OK Impedance Matching (120 Ohms) OK Offset Stability OK (< 500 V over several days) Cross talk: ~ 22 Db between adjacent channels
mainly do to induction at the input minor design change to reduce it further
Main contribution from Ilko Rusinov and
Andrey Marinov (shaper)Pierre Bene (splitter)
MICE CM18 June 07 Jean-Sébastien Graulich Slide 16
Shaper Test Shaper Test OutcomesOutcomes
Shaper design is validatedShaper design is validated The 4-stages version is more The 4-stages version is more
appropriateappropriate Larger signal rise time for identical full width
better for time measurement for EMCal Not significantly more noisy
EMCal and TOF have different dynamic EMCal and TOF have different dynamic range and need different gainsrange and need different gains
A jumper will be added to select low gain for EMCal or larger gain for TOF
Splitter needs a second iterationSplitter needs a second iteration Gain matching is fine Pick up noise is too large :-(mainly 50 Hz)
MICE CM18 June 07 Jean-Sébastien Graulich Slide 17
Shaper optimizationShaper optimization There was a long discussion about dynamic There was a long discussion about dynamic
range and gain issuesrange and gain issues Output range of the shaper is limited by the power
supply voltage provided by the NIM crate +/- 6V -> Maximum 2 Volts output range +/- 12V -> Maximum 8 Volts output range
We can’t use +/- 12V for all the channels because the current is limited to 3A and we need 700 mA per board
EMCal input signal range is ~5V TOF input signal range is ~2V Input range of the CAEN flash ADC is either
2.25V or 10 V. Which version should we ask for ? We will start with the small input range We will start with the small input range
version of the fADC version of the fADC shaper’s gain of 0.5 for EMCal and 1.0 for TOF Power supply voltage will also be selectable by a
switch
MICE CM18 June 07 Jean-Sébastien Graulich Slide 18
Schedule MilestonesSchedule Milestones
DAQ Test bench including Event builder: DAQ Test bench including Event builder: Feb 2007Feb 2007 Still not completely passed Significant progress done with the single PC test bench
Order Hardware for Stage 1: Order Hardware for Stage 1: March 2007March 2007 done in May but everything is already delivered Shaper production process launched
Launch Shaper ProductionLaunch Shaper Production June 2007June 2007 Move DDAQ system to RAL: Move DDAQ system to RAL: July 15 2007July 15 2007 First batch of 6 Shaper Boards (96 ch)First batch of 6 Shaper Boards (96 ch) September September
20072007 Production of 8 Splitter boardsProduction of 8 Splitter boards September 15 2007September 15 2007
MICE CM18 June 07 Jean-Sébastien Graulich Slide 19
SummarySummary
DDAQ Architecture has been revised DDAQ Architecture has been revised All the hardware for Stage I is in All the hardware for Stage I is in
handhand DAQ test bench is so late that it’s DAQ test bench is so late that it’s
becoming obsolete…becoming obsolete… Particle and DAQ Trigger designs are Particle and DAQ Trigger designs are
now maturenow mature Shaper is in good shape…Shaper is in good shape… DAQ system will be installed at RAL DAQ system will be installed at RAL
in Julyin July
MICE CM18 June 07 Jean-Sébastien Graulich Slide 20
Questions & Questions & suggestion after the suggestion after the
talktalk Trigger condition: Add downscaled Trigger condition: Add downscaled
TOF 0 in OR TOF 0 in OR Send actual condition used to issue Send actual condition used to issue
the trigger into IRthe trigger into IR Use TOF vertical counters in OR with Use TOF vertical counters in OR with
the Horizontal the Horizontal A list of requirements should be A list of requirements should be
issuedissued