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Microarchitecture
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Outline
• Architecture vs. Microarchitecture • Components• MIPS Datapath
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Architecture vs. Microarchitecture
• Architecture• What the CPU does
• Microarchitecture• How the CPU does it
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Architecture
• What the CPU does
• CPU is a black box• Only care about what goes in / comes out
• Only need to know what instructions the CPU can execute• Instruction set architecture (ISA)
• Realm of computer scientists• Don’t really care how it works under the hood
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Microarchitecture
• How the CPU does it
• Electrical mechanisms that allow CPU to execute instructions• Control paths, adder(s), multiplexors, memory units, etc.
• Many possible microarchitectures for single architecture
• Domain of computer and electrical engineers
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Architecture vs. Microarchitecture
• Analogy: factory that produces auto parts
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Architecture vs. Microarchitecture
• Architecture: don’t care about “how” factory runs, as long as the parts are good
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Architecture vs. Microarchitecture
• Microarchitecture: care about “how” the factory runs
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Architecture vs. Microarchitecture
• Microarchitecture: care about “how” the factory runs
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Architecture vs. Microarchitecture
Intel Pentium IV AMD Bobcat
x86 Architecture
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Outline
• Architecture vs. Microarchitecture • Components• MIPS Datapath
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Von Neumann Model (basic structure of computer)
MEMORY
INPUT OUTPUT
PROCESSING UNIT
CONTROL UNIT
PC IR
MAR MDR
TEMPALU
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Components: Memory
MEMORY
INPUT OUTPUT
PROCESSING UNIT
CONTROL UNIT
PC IR
MAR MDR
TEMPALU
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Components: Memory
• 2k × m array of stored bits• E.g., 24 × 8
• Address• Unique (k-bit) identifier of location
• Contents• m-bit value stored in location
• Basic operations• STORE: write a value to memory location• LOAD: read a value from memory location
MEMORY
MAR MDR
0000
0001
0010
0110 1111
0011
…
1101
1110
1111
0001 0110
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• Result of “LOAD 0010”?
Components: Memory MEMORY
MAR MDR
0000
0001
0010
0110 1111
0011
…
1101
1110
1111
0001 0110
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• Result of “LOAD 0010”? 0110 1111
Components: Memory
0000
0001
0010
0110 1111
0011
…
1101
1110
1111
0001 0110
MEMORY
MAR MDR
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Components: Memory
• How to read data to/from memory?• MAR: Memory Address Register• MDR: Memory Data Register
• LOAD data from memory (address A)1. Write the address (A) into MAR2. Send a “read” signal to memory unit
(memory unit will go get bytes, put into MDR)
3. Read the data from MDR
MEMORY
MAR MDR
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Components: Memory
• How to read data to/from memory?• MAR: Memory Address Register• MDR: Memory Data Register
• STORE data X in memory B1. Write the data (X) into MDR2. Write the address (B) into MAR3. Send a “write” signal to memory
(memory unit will do its thing to write X in location B)
MEMORY
MAR MDR
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Components: Memory
• What is controlling Memory?• The CONTROL UNIT of course!!
• CONTROL UNIT sends signals • Instructs the other components
• How does it know what signals (instructions) to send?
MEMORY
CONTROL UNIT
PC IR
MAR MDR
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Components
MEMORY
PROCESSING UNIT
CONTROL UNIT
PC IR
MAR MDR
TEMPALU
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CONTROL UNITComponents: Control Unit
• How does CONTROL UNIT know what to do?• Well, it doesn’t “know”..
• Control Unit follows command in the Instruction Register (IR)
• Program Counter (PC) register holds memory address of the current instruction
• What types of instructions do you think are available?• LOAD? STORE? ADD? SUBTRACT? OTHERS?
PC IR
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CONTROL UNITComponents: Control Unit
• Control Unit decodes instruction stored in IR
• Sends signals to components based on decoded instruction
• For example, perhaps the following instruction is in the IR
PC IR
0 0 0 1 1 0 0 1
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CONTROL UNITComponents: Control Unit
• In this simplified example, the instruction is decoded as:
PC IR
0 0 0 1 1 0 0 1
first two bits:00 means
LOAD
next four bits:memory address
to read from (0110)
last two bits:01 refer to
MDR
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CONTROL UNITComponents: Control Unit
• Based on this instruction, the Control Unit will activate the corresponding circuitry to signal the memory unit to get data• This circuitry goes beyond the scope of this course
• Consists of finite state machines of multiplexors, system clock, bus etc.
PC IR
0 0 0 1 1 0 0 1
first two bits:00 means
LOADnext four bits:
memory address to read from
(0110)
last two bits:01 refer to
MDR
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CONTROL UNITComponents: Control Unit
• If the instruction in the IR contains logic or arithmetic, the Processing Unit gets involved
PC IR
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Components
MEMORY
PROCESSING UNIT
CONTROL UNIT
PC IR
MAR MDR
TEMPALU
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Components: Processing Unit
• Contains ALU• Arithmetic Logic Unit
• Also contains temporary registers (TEMP)• Used for arithmetic operands• Used to store intermediate results of arithmetic operations
• May also contain other functional units• Special purpose arithmetic: e.g., multiply, divide, etc.
PROCESSING UNIT
TEMPALU
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Components: Processing Unit
• How does Processing Unit know what to do?
• Again, Control Unit sends electric signals that correspond to the appropriate instruction (e.g., ADD, SUBTRACT)
PROCESSING UNIT
TEMPALU
CONTROL UNIT
PC IR
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Components: Processing Unit
• Processing Unit gets data from Memory Unit• Processing Unit puts data into Memory Unit
MEMORY
PROCESSING UNIT
MAR MDR
TEMPALU
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Components: Processing Unit ALU
• ALU has its own inputs and output• A is m-bit binary (input)• B is m-bit binary (input)• control tells ALU what to do (input)
• E.g., add, subtract, divide, etc.• Usually control pins (high / low)
• C is m-bit result (output)
PROCESSING UNIT
TEMPALU
control
A B
C
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Break Time!!
... wish I was there!!!
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Outline
• Architecture vs. Microarchitecture • Components• MIPS Datapath
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MIPS Datapath
• MIPS• Microprocessor without Interlocked Pipeline Stages• RISC Architecture: Reduced Instruction Set Computer
• Microarchitecture of single-cycle MIPS processor…
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MIPS Single-Cycle Microarchitecture
• We are going to “build” a single-cycle MIPS CPU
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MIPS Single-Cycle Microarchitecture
• System clock• An oscillator that produces a square wave• E.g., 2.4 GHz processor- means 2.4 billion square waves per second• Components of CPU (memory, ALU, bus, etc.) synchronized to clock
• Actions occur on “rising” or “falling” edge
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MIPS Single-Cycle Microarchitecture
• Single-cycle CPU: • Executes an entire instruction in one clock cycle• Clock cycle time limited by slowest instruction
one cycle
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MIPS Single-Cycle Microarchitecture
• Overview of components used in diagram
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MIPS Single-Cycle Microarchitecture
• PC: Program Counter• 32-bit register• Input (PC’): next instruction• Output (PC): current instruction• CLK: system clock
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MIPS Single-Cycle Microarchitecture
• Instruction Memory• Single read port• Input: 32-bit instruction address (A)• Output: 32-bit data (i.e., instruction) (RD)
• Note: this is an oversimplification that assumes the instruction memory is ROM (read only memory)• In reality, the instruction memory is writable; the OS can load new
programs into memory
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MIPS Single-Cycle Microarchitecture
• Register File (32 registers, 32-bits each)• Inputs:
• A1: 5-bit address specifying a register (to read)• A2: 5-bit address specifying a register (to read)• A3: 5-bit address specifying a register (to write)• WD3: 32-bit data to write to register• CLK: system clock• WE3: write enable (single bit)
• Outputs:• RD1: 32-bit register value specified by 5-bit address A1• RD2: 32-bit register value specified by 5-bit address A2
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MIPS Single-Cycle Microarchitecture
• Data Memory• If WE (Write Enable) is 1,
• Writes data WD into address A on rising edge of clock (CLK)
• If WE is 0,• Reads address A onto RD on rising edge of clock (CLK)
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MIPS Single-Cycle Microarchitecture
• Start by building the datapath• First step, connect PC to Instruction Memory
• PC register contains address of instruction• Instruction Memory fetches instruction (instr) from memory
PC instr
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MIPS Single-Cycle Microarchitecture
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MIPS Single-Cycle Microarchitecture
• Next step, things start to get more complicated• The instruction (instr) gets decoded by the control unit
• The appropriates pins (e.g., write enable) get set• The 5-bit register addresses (in the Register File) get specified
• (Things get “set up” for execution)
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MIPS Single-Cycle Microarchitecture
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MIPS Single-Cycle Microarchitecture
• Next, execution occurs (based on instruction)
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MIPS Single-Cycle Microarchitecture
• Then, the result of execution interacts with memory (somehow)
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MIPS Single-Cycle Microarchitecture
• The process then starts over…
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MIPS Single-Cycle Microarchitecture
• Let’s look at the datapath for a concrete example• MIPS assembly instruction lw (stands for “Load Word”)
• lw loads 32-bits of data from a memory address to a register
• Please keep in mind that we will NOT use MIPS assembly, we will use x86• This is for demonstration purposes only, x86 datapath is more complex
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MIPS Single-Cycle Microarchitecture: lw example
• Step 1: fetch the instruction
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MIPS Single-Cycle Microarchitecture: lw example
• Step 2: decode the instruction• In this case, read source operands from register file
• Source operands come from the instruction itself• Says what registers to get information from
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MIPS Single-Cycle Microarchitecture: lw example
• Step 3: sign-extend the immediate result (decode)• This has to do with the “offset” of the memory address• This is a mechanism to make the “offset” 32-bits long • Don’t worry about this..
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MIPS Single-Cycle Microarchitecture: lw example
• Step 4: Compute the memory address (execute)• ALUControl2:0 is from the control unit, tells ALU to add• SrcA is “base”• SrcB is “offset”
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MIPS Single-Cycle Microarchitecture: lw example
• Step 5: Read data from memory, write back to Register File• RegWrite is command from Control Unit• 20:16 is part of instruction: 5-bit register address to load word
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MIPS Single-Cycle Microarchitecture: lw example
• Step 6: Increment the Program Counter (PC)• PC will point to next instruction• 32-bit instruction width = 4 bytes (hence PC + 4)
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MIPS Single-Cycle Microarchitecture
• The datapath depends on the instruction…
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Next Time…
• Execution Cycle• Big vs. Little Endian• CPU execution time..