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Microelectronics Packaging

Microsystems Packaging

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Integration of IC, Packaging and System

Packaging Hierarchy

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System Packaging Technologies

Summary of Microsystems Packaging

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Moore’s Law

Evolution of the Microprocessor

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IC Packaging Requirements

•Protect circuit from external environment•Mechanical interface to PCB•Interface for production testing•Good signal transfer between chip and

PCB•Good power supply to IC•Cooling

Through-hole and Surface Mount Packages

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Integrated Circuit Packaging

Different applications have differentrequirements–Logic (Microprocessors, ASIC’s)

•High power, I/O count•Small number per board (ok if bigger)•Relatively high Average Selling Price (ASP)

–Memory (DRAM, Flash)•Lower power and fewer I/O’s per die•Large number per board

IC Package Types

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Traditional IC Package Types

Dual-in-line (DIP)

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Quad Flat Pack (QFP)

Wire Bond packageLeads are coplanar fanning

into die - higher coupling

New IC Package Types

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Ball Grid Array (BGA)

Most popular ASIC package–Basically a small printed circuit board–Create a 2-D array of pins under the package

Multiple planes available in package–Possible to route larger numbers of signals–Better signal integrity

Chip Scale Packages (CSP)

Packages is same size as die–Very space efficient

Very short leads –good electrical propertiesBack side of die exposed –good thermal propertiesPossible to fabricate at wafer level

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New IC Package Types

Number of I/Os in a Package

pKMN

N: number of pins or terminalsK: average number of terminals per

logic circuitM: number of circuits/gatesP: Rent’s constant

Rent’s Rule

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Rent’s Constants

1.4

82

0.63

0.25

High Speed Computer

Chip/module level

Board / System level

1.90.50Gate Array

0.820.45Microprocessor

60.12Static Memory

KPSystem or Chip Type

Terminals vs Number of Circuits

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I/Os of a Chip

For a 64MB Static RAM chip, signalI/Os of this chip is

52)1064(6 12.06 SRAMN

13450009.1 5.0 gatearrayN

For a gate array chip with 5000 gates,signal I/Os of this chip is

Packaging Trend

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IC Packaging Efficiency

Technology Trend in IC Packaging

Source: ERSO/ITRI

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Bottlenecks & Break Through Solutions

Source: ERSO/ITRI

SHARP’s 3-D System in Package

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Multi-chip Module (MCM)

Multi-chip Module (Cont.)

SP5MX1 Pentium Module (43mm x 43mm)

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Schematic Overview of SP5MX1

Cooling for MCM

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Thermal Conduction Module (TCM)

Source: IBM

Three Types of MCM

MCM-DMCM-CMCM-L

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MCM-L

Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63

MCM-C

Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63

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MCM-D

Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63

Signal and Power Distribution for MCM

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Fabrication of MCM-C

Fabrication of MCM-D

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MCM-L Substrate Structure

drilled via (buried)

metal 3

metal 4

prepregscore (FR4/5)

metal 1

metal 2

Ni/Ausolder resist

micro via

Source: Cork Institute of Technology

PCB Laminate Materials

Nonwoven glass core and wovenglass surface, similar to FR-4,longer drill life

Woven glassand glass

matte

EpoxyCEM-3

Paper core and glass surface, self-extinguishing, excellent punching,longer drill life and minimal dust.

Paper andglass

EpoxyCEM-1

Flame resistant, low capacitanceor high impact applications

Glass mattePolyesterFR-6

Flame resistant, higher Tg, betterthermal

Woven glassEpoxyFR-5

Flame resistance, Tg ~ 130CWoven glassEpoxyFR-4

Flame resistant, high insulationresistance

PaperEpoxyFR-3

Punchable, flame resistantPaperPhenolicFR-2

DescriptionReinforcementResinSystem

NEMA Grade

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Comparison of MCM

Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63

Chip Scale Package (CSP)

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System in Package (SIP)

Wireless (RF) Market is the Key Driver–Motorola, Philips

LTCC is the Substrate of Choice–CBGA Package

SiP is not SOC (System On Chip)

System In Package (Cont.)

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Advantages of SIP over SOC

RF ICRF IC’’s Typically Take 3s Typically Take 3--5 Manufacturing Passes5 Manufacturing Passes––Total Cost of Up To 5 Million DollarsTotal Cost of Up To 5 Million Dollars––6 Month Impact to Schedule6 Month Impact to Schedule

SIP on LTCCSIP on LTCC––Total Cost Less Than 500K for 3Total Cost Less Than 500K for 3--5 Manufacturing5 Manufacturing

PassesPasses––6 Week Impact to Schedule6 Week Impact to Schedule

Mixed Technology SupportMixed Technology Support––CMOS,CMOS, GaAsGaAs,, SiGeSiGe all on One Substrateall on One Substrate––Flexible Design PartitioningFlexible Design Partitioning

Bluetooth Standard PlatformBluetooth Standard Platform

LTCC Process

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Applications for LTCC

(a) Wire bonding

(b) Flip-chip bonding

(c) Tape-automatedbonding

Bonding Methodologies

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Wire Bonding

Pads are placed in one or two rows–Logic devices –Around periphery of die

•1 row: 70μ pitch•2 rows: 40-50μ staggered pitch

–Memory (DRAM) –in a line at center of die•1 row: 100-150μ pitch

Wire Bonding

Oldest attachment method and still dominantfor ICs

Au or Al wires are attached between pads andsubstrate using–Thermocompression bonding–Ultrasonic bonding–Thermosonic bonding

The process is time-consuming since eachwire must be attached individually

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Wire Bonding (Cont.)

Used in Lead Frame, PGA and BGAOver 80% of Packages are WirebondedTypically Gold Wire

– Also Copper, Aluminum– Wire length- 1-5 mm– Wire diameter- 25-35 µm– Inexpensive, Reliable

Source: Cadence

Thermocompression Bonding

(a) Gold wire (15-75 mm diameter) fedfrom a spool through a capillary

(b) Electric spark melts end of wire,forming a ball

(c) Ball is positioned over the chipbonding pad, capillary is lowered,and ball deforms into a "nail head"

(d) Capillary raised and wire fed fromspool and positioned over substrate;bond to package is a wedgeproduced by deforming the wire withthe edge of the capillary

(e) Capillary is raised and wire is brokennear the edge of the bond

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Ultrasonic Bonding

Problems with thermocompression– Oxidation of Al makes it difficult to

form a good ball– Epoxies can’t withstand high

temperatures Ultrasonic is a lower temperature

alternative Relies on pressure and rapid

mechanical vibration to form bonds Ultrasonic vibration at 20-60 kHz

causes the metal to deform and flow

Thermosonic Bonding

Combination ofthermocompression andultrasonic

Temperature maintained at ~150oC

Ultrasonic vibration and pressureused to cause metal to flow toform weld

Capable of producing 5-10bonds/sec

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Pros and Cons of Wire Bonding

Pros–Cost: cheapest packages use wire bonding–Allows ready access to front side of die for probing

Cons–Relatively high inductance connections

•Bond wires are 1nH/mm•Bond wire length is typically 3-5mm

–Number of bonds is proportional to square root ofdie area•Not great for distributing large amounts of power•Not great for large numbers of I/O’s

Tape-Automated Bonding

Developed in early 1970s ICs first mounted on flexible polymer tape (usually

polyimide) with Cu interconnection Cu leads defined by lithography and etching After aligning IC pads to metal interconnection on

the tape, attachment occurs by thermocompression Au bumps formed on either side of the die or tape

used to bond die to the leads

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Pros and Cons of TAB Process

Prosall bonds formed simultaneously, improving throughput

Cons– Requires solder bumps with complex metallurgy– A particular tape can only be used for a chip

Flip-Chip Process

IC is mounted upside-down onto module or PCBConnections made via solder bumps located over the

surface of ICOwing to shorter interconnect lengths, signal

inductance is reduced

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Flip-Chip Bonding

Chips are placed face down on the substrates so that I/O pads onthe chip are aligned with those on the substrates

Solder reflow process is used to form all the required connections Drawback: bump fabrication process is fairly complex and capital

intensive Solderless flip-chip technology is another alternative; involves

stencil printing of organic polymer onto an IC

Two Methods of Bumping the Chip

RDL- Re-Distribution Layer Direct Bumping (UBM)

Source: Cadence

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Solder Bumping Structure

Under Bump Metallurgy (UBM)Adhesion layer: Ti, Cr, TiWWetting layer: Ni, Mo, CuProtective layer: Au

SolderHigh lead solder: 5Sn/95Pb, 3Sn/97PbEutectic solder: 63Sn/37PbNonlead solder

Under Bump Metallization (UBM)

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Metallization of Solder Bumping

Under Bump MetallurgyEvaporationSputtering

Solder BumpEvaporation: High resolutionElectro platingStencil printing: Low cost, High throughput

Fabrication of Solder Bump

Wafer cleanDeposition of BLMP/R coatingEtchingSolder paste printingReflow and ball formation

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Solder Bumping Process

Source: Advanpack Solutions Pte Ltd

Pros and Cons of Flip Chip

Pros–Large number of connections

•1cm x 1cm wire bond chip @ 50μ staggered pitch: 800pads

•1cm x 1cm flip chip @ 250μ centers: 1600 pads–Better power distribution

•Flip chip: current flows through 20μ thick power planerouting

•Wire bond: Current flows through 1μ thick top layer metal

Cons–Cost–Debug

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Current Trends for IC Packaging

3D Packaging- Stacked DieBuild-Up Substrates“Green”Manufacturing

–Removing Lead (Pb)–New Materials (tin, silver, copper) for Die

Attach, plating, solder balls

3D Packaging- Stacked Die

Definition: Packaging technology with 2 or more DIE stacked in a single package ormultiple packages stacked together

Supports– Wirebond– Flip chip– Hybrid- combination of flip-chip and wirebond

Packaging Applications– CSP (most common)– PBGA, BGA, TSOP, TQFP

Benefits of 3D Packaging– Smaller, thinner and lighter Packages– Reduced packaging costs and components– Reduced system level cost for system in package (SiP) and system on chip (SoC) approach– System level size reduction due to smaller footprints and decrease component count

Common for wireless handsets, handheld electronics and memory intensiverequirements

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Increasing Package Density

Large memory systems, density is keyFor portable electronics, space is keyReduce required package size

–Stack die on top of one another

3-D Packaging

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Amkor 3D Packaging Roadmap

Source: Amkor

3D Packaging Platform Technologies

Design rules and infrastructure for thinner,high density substrate technologies

Advanced wafer thinning and handlingsystems

Thinner die attach and die stacking processesHigh density and low loop wire bondingPb free and environmentally "Green" material

setsFlip chip plus wire bonding mixed technology

stacking

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Build-Up Substrates

Sequential lamination is used to make high-performance, multi-layer PCBs for mountinghigh pin packages

Build-up structure is used to make high-density PCBs for mounting fine pin pitchpackages closely together,

High-densityDesign flexibilityLayer reductionCost Reduction

Build-Up Substrates (Cont.)

Source: Fujitsu

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Green Packaging

All the electrical and electronicequipment with lead cannot beproduced in and shipped to the EUCountries after July 1, 2006Seeks to increase recycling and

recovery of waste equipment

Green Packaging (Cont.)

Elimination of certain elements andcompoundsRecycling of products at "end of life"

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Green Packaging Banned Materials

Lead (Pb)–Lead mainly destroys body’s nerve system,

blood circulation and kidney function

Cadmium (Cd)–Cadmium-containing compound is a very

harmful substance to human’s health, whichis mainly in kidney

Green Packaging Banned Materials

Mercury (Hg)–When inorganic mercury disperses into

water, then becomes harmful to human’sbrain

–Organic mercury inflicts relatively less harmto human body

Hexavalent Chromium (Cr+6)–Cr+6 can easily enter cell through cell

membrane and can destroy DNA

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Green Packaging Banned Materials

PBB and PBDE–Polybrominated Biphenyls (PBB)–Polybrominated Diphenyl Ethers (PBDE)–difficult to recycle plastics–PBDE will produce cancer-incurring PBDD

and PBDF in extrusion process

Green Packaging Materials

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Lead-free Solder Alloys in Japan

The lead-free solder alloys used by someJapanese noticeable companies areMatsushita: SnAgBiIn, SnCuSony: SnAgBiCu and Sn2Ag4Bi0.5Cu0.1GeToshiba: SnAgCuHitachi: SnAgBi, SnAgCu, SnAgCuInNEC: SnZn, SnCu, SnZnBi, SnAgCuThese companies are all focusing on SnAgCu

Solutions for the Elimination of Lead

Solder AlloysTernary Sn/Ag/Cu alloys contain 3 - 4% silver, 0.5 - 1.0%

copperSn/4.0Ag/0.5Cu, Sn/3.0Ag/0.5Cu alloy are adopted by AmkorMelting ranges of Sn/Ag/Cu alloys are around 220°C, while

eutectic tin/lead are at 183°C

Lead Finishpure Sn coating - deposition processes are available, cost

efficient, and is compatible with soldering processes butreliability concerns about tin whiskers is a major issue

nickel-palladium pre-plated leadframes - Japanese electronicsindustry has used a higher percentage of these packages

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Solutions for the Elimination of Lead

Flip ChipSn/Ag/Cu or other similar alloy bumpgold stud bumpAnisotropic Conductive Film (ACF)

ReliabilityBoard assembly reflow processes are

required to maintain peak temperatures of240 - 260°C which is as much as 20 - 40°Chigher than current processes

Temperatures of Solders

Solidus Temp: Above the solidus temperature, materialconsists of liquid phase and solid phase

Liquidus Temp: The temperature above which the liquidphase is stable

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Lead-Tin Binary Phase Diagram

Lead Free Critical Issues

Overall costs increaseImpact of PCB finishesImpact of component finishesTin whisker (short) riskComponent reliabilityReworkSolder joint reliabilityReliability testsInfrastructure

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IC packaging Materials

•Ceramic–Good heat conductivity–Hermetic–Expensive ( often more expensive than chip itself !)

•Metal–Good heat conductivity–Hermetic–Electrical conductive

•Plastic–Cheap–Poor heat conductivity

Properties of Materials (Ceramics)

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Properties of Materials (Metal)

Properties of Materials (Polymers)

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Properties of Lead Frame

Properties of Wirebonding Materials

Pure Al, Au, and Cu are too soft mechanicallyto draw and handle

Aluminum (Al + 1% Si, Al+0.5 –1% Mg) wires(diameter > 25 μm)

Gold (Au + ppm Be, Pd, ..) wires (diameter ~25 μm)

Copper (Cu + % Fe, Zn, ..) wires (diameter >25 μm)

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Issues of Wirebonding

Intermetallic compoundPurple plague: AuAl2White plague: Au5Al2

Kirkendahl voids