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Microprocessor control ofelectro-mechanical actuators
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• A Doctoral Thesis. Submitted in partial fulfilment of the requirementsfor the award of Doctor of Philosophy of Loughborough University.
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Publisher: c© Z.M.A. Ismail
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MICROPROCESSOR OF
CONTROL
ELECTRO-MECHANICAL ACTUATORS
BY
ZIAD MUHAMMED AHMED ISMAIL , B.Sc. , M.Sc.
A doctoral thesis submitted in partial
fulfilment of the requirements for the
award of Doctor of Philosophy of
Loughborough University of Tech no I o gy
MAY 1g86
SUPERVISOR
J.E.Cooling B.Sc. , C. En g. , M I E E.
Department of Electronic and Electrical
Engineering
@ Z.M.A.Ismail, 1986.
' I
TO MY WIFE and SONS
ACKNOWLEDGEMENT
I wish to express my deep sense of gratitude to my supervisor
Mr J E Cooling, for his helpfulness, guidance, inspiration and encouragement
during the preparation of this thesis.
I would also like to thank Professor I R Smith, Head of Electrical
and Electronic Engineering Department, for the provision of all facilities.
I am thankful to the staff and student members and technicians for their
assistance.
The author is indebted to his wife for her endurance and support
throughout the project.
Last but not least, thanks are extended to Mrs Pauline Higgs, who
patiently typed this thesis.
SYNOPSIS
This thesis is concerned with the use of all-electric systems for the
closed loop position control of mechanical (valve) actuators.
wide range of topics including
It embraces a
* the use of 3-phase induction motors and their speed/torque control using
Pulse Width Modulation techniques
* implementation of both analogue and digital (PID) controllers
* Using computer simulation methods for the development of digital control
algorithms and tuning techniques
* the use of Computer Assisted Tuning methods for tuning up the position
control loop.
The major hardware activities described here are concerned with the
design, development and construction of a 3-phase 115 volt inverter unit, an
analogue controller, and interfaces to a single board microcomputer (SBC).
The construction and test of the SBC is also described in the text. Details
of the use of an analog controller to study and determine the transfer
function of the inverter/actuator system is presented. Digital
implementation of PID control (for actuator's position) by microcomputer is
also described, togehter with the theoretical development of the control
algorithm.
Software activities consist of two major parts, plant simulation and
software development for the microprocessor (embedded) controller.
The derivation of a plant model from the results of on-line testing
is given; from this a computer simulation is developed to study the effects
of controller tuning parameters on the loop performance.
Software development for the embedded controller covers Man-Machine
Interfacing, tuning, and control functions.
i i
A new approach to the tuning of control systems is developed here,
that of computer assisted tuning. Test results are given showing the
effectiveness of CAT techniques for the tuning of the actuator position
control loop; these tests also demonstrate the performance achieved using a
digital PID controller. It is concluded that, provided plant parameters can
be established, Computer Aided Tuning enables plant tuning to be carried out
to meet specific performance targets (e.g. rise time, overshoot) set by the
plant operator. Furthermore this can be carried out by a relatively
unskilled operator.
i i i
LIST OF PRINCIPAL SYMBOLS
ns
fs
s
p
V
I
Et
E1
R1
x1
R2
x2
Xo
It
Rr
sm
Tq
~
Vs
IZs
Ks
Tc
I m
N
synchronous speed of the induction motor
synchronous frequency of the induction motor
slip
number of poles
voltage
current
rotor speed
terminated voltage
input voltage per phas
resistance of stator/phase
leakage reactance/phase
referred leakage resistance of rotor
referred leakage reactance of rotor
magnetising reactance
stator current per phase
rotor resistance
slip at maximum torque
torque developed by motor
flux
terminal voltage
stator impedance volt drop at current 'I'
constant
repetitive time of carrier frequency
mean current
constant
iv
·.l
K,K1 ,K2 ,K 3 gain
Tm system transmittance sensitivity
Kp proporional gain in PID controller
K; integral gain in PID controller
Kd derivative gain in PID controller
A,B,C constants
Ma slope of the ADC characteristic line
KT response time constant gain
e(t) position error (mm)
U(t) actuating frequency input to the motor
't' time constant
T
M
sampling time
amplitude of sinewave signal
V
.I
1 INTRODUCTION
1.1 Power Actuation In Control Systems
1.2 Actuator Drive Motors And Their Control
1.3 Closed Loop Control Systems
1.4 Thesis Object and Organisation
2 INDUCTION MOTOR DRIVES
2.1 Introduction
2.2 Principle of Cage Induction Motor
2.3 Torque Speed Characteristic of Induction Motor
2.4 Induction Motors For Inverter Drives
2.4.1 Introduction
2.4.2 Cage Motor Speed Control
1
1
3
4
9
9
9
10
13
13
13
2.4.3 Motor Performance on Variable-Frequency supplies 14
2.4.4 Variable-Voltage Supply 14
2.4.5 Constant Torque Control
2.5 Pulse Width Modulation
2.6 P.W.M. Techniques
2.6.1 Introduction
2.6.2 Natural Sampling Techniques
2.6.3 Regular Sampling
2.6.4 Optimal P.W.M. switching strategy
2.7 Power Switching Devices
2.8 Basic PWM Inverter
3 INVERTER.DESIGN
3.1 Overview
3.2 Inverter Types
15
16
16
16
16
17
18
19
19
31
31
31·
4
3.2.1 Quasi Square Wave
3.2.2 Pulse Width Modulated Wave Inverter
3.2.3 Current Source Inverter
3.3 System and Circuit Design
3.3.1 System Structure
3.3.2 Power Stage General Description
3.3.2.1 Introduction
3.3.2.2 Power FET
3.3.2.3 Power Devices Design Criteria
3.3.2.4 Power FET Driving Circuit
3.3.3 Controlling Circuits
3.3.3.1 LSI Chip PWM Controller
3.3.3.2 Overcurrent Protection
3.3.4 Power Supplies
3.3.4.1 Inverter Power Supply
3.3.4.2 Driver Power Supply
3.3.4.3 Control Circuit Power Supply
ELECTRONIC CONTROL SYSTEMS
4. 1 Introduction
4.2 The Analogue Controller
4. 2.1 Functions and Facilities
4.2.2 System Operation
4.2.3 Circuit Operation and Design
4.3 The Digital Controller
4. 3.1 System Description
4. 3.2 Microcomputer Board Design and Operation
4. 3. 3 Interface Board Design and Operation
31
32
33
33
33
34
34
35
36
38
39
39
40
42
42
42
43
63
63
63
63
64
65
66
66
67
72
5 CONTROL SYSTEMS
5.1 Open and Closed Loop Control
5.2 Performance.Criteria
5.2.1 Introduction
5.2.2 Stability
5.2.3 Sensitivity
5.2.4 System Performance
5.2.4.1 Introduction
5.2.4.2 Step Input Function
5.2.4.3 Frequency Response Function
5.3 Digital Control
5.3.1 Why Digital Control
5.3.2 Discretization
5.4 PID Controller
6 EXPERIMENTAL STUDIES
6.1 Introduction
6.2 Analogue Control System Performance
6.2.1 Open Loop Performance
6.2.2 Closed Loop Performance
6.3 Digital Control System Performance
6.3.1 Introduction
6.3.2 The Digital PID Controller
6.3.3 Practical Results
6.4 Computer Aided Tuning
6.5 Plant Simulation
87
87
88
88
88
89
90
90
91
92
93
93
94
95
106
106
106
106
118
110
110
111
112
113
116
7 SOFTWARE DESIGN AND DEVELOPMENT 146
7.1 Introduction 146
1.2 Software Structure And Development 146
7.3 Digital Control Unit 148
7.4 Calibration of Input And Output Sections 148
7.4.1 ADC Calibration 148
7.4.2 DAC Autocalibration-Wrap-Round Test 150
7.5 Software Functioning 151
7.5.1 Manual Tuning of the PID Controller 151
7.5.2 Computer Aided Tuning of the PID Controller 154
8 Conclusion 172
APPENDIX A - Electronic Design-Detailed Design 180
APPENDIX B - Software Documentation '189
APPENDIX C - Computer Simulation 240
CHAPTER 1
1
CHAPTER 1
1 Introduction
1.1 Power Actuation In Control Systems
In many control applications power actuator systems are used as the
final output device of the controller, acting as the plant/controller
1 interface. Typical applications include gas or steam valve control in steam
turbine systems, motorised carburetters for Air/Fuel mixture ratio control,
and aircraft flight surface actuation. Figure 1.1 shows the block diagram
of a generalized position servo system, where the principal components are
the closed loop controller, power amplifier, and actuat~ng device.
Traditionally power amplification and actuation has been carried out
using pneumatic or hydaulic devices, servo systems being almost entirely
based on hydraulics. However recent development in power electronics have
made it possible to design and build electromechanical actuators (EMA) that
can economically replace hydraulic actuators.(HA). Electric actuators are
generally superior to hydraulic ones in terms of size, weight and maintenance
requirements. Above all the EMAs are "power-by-demand" operation versus the
hydraulics "full-time power" operation. Thus EMAs are suitable for use in
both low and high performance closed loop servo systems as power actuation
devices,
1.2 Actuator Drive Motors And Their Control
In the last two decades the great majority of electric actuators for
servo systems have used de motors powered by rotating amplifiers (metadynes
and amplidynes), chopper amplifiers, or phase controlled rectifier systems.
Examples of these include the gun servo stabiliser of the Centurion tank,
rudder steering gear actuation for HMS London, and the "Sea Dart" missile
2
launcher controller.
This was determined mainly by the technical and economic factors
relating to the motor controller. For these very same reasons ac motors
were used only for fixed speed on-off operation, variable speed operation
requiring costly and sophisticated controllers. However, there are a number
of disadvantages associated with the de motor, as follows:
• Brush wear problems (especially at high altitude).
• Significant amounts of routine maintenance required.
• Large size for a given horsepower rating.
• Commutation problems.
It can be seen that these stem almost directly from the use of
brushes within the motor. Hence brushless motors offer a significant
performance improvement over the de type. Two main contenders for use in
serve applications can be identified, the de stepper motor and the ac
induction motor (usually a 3-phase type).
associated with these kinds are as follows:
(a) Advantages of stepper motor.
• Provides very high torque at low speed.
• Accurate position control.
(b) Disadvantages of stepper motor
• High cost system
• Shows unstability at certain torques
• Large in size.
• Totally electronic controlled.
(c) Advantages of induction motor
The advantages and disadvantages
• Low rotor inertia which improves dynamic performance.
• Almost maintenance free.
3
• Long life system.
• Low cost.
• Robust and capable of withstanding harsh environmental condition.
(d) The disadvantages of induction motor.
The induction motor exhibitsa non linear, highly interacting
multivariable control structure, whose essential variables, e.g. rotor
current, cannot be measured. Hence, it gave rise to some difficulties which
limited accurate analysis and applications of such systems. To obtain high
performance variable speed control of induction motors, a complex control
scheme is needed. Only a relatively small number of papers have been
published concerning the use of induction motor control in 2-5
servo systems,
most of them being concerned with the control of elevators employing large
6~ horsepower motors.
In the past implementation of such control schemes using hardwired
logic and discrete components has been complex and expensive. However
recent advances in microprocessor systems and LSI circuits coupled with
developments in power circuitry have made ac motors a practical drive
alternative to the de motor in the low power (Below 10 H.P.) range.
1.3 Closed Loop Control Systems
The great majority of plant control systems are built using standard
off-the-shelf actuators, controllers and sub-systems. This is in distinct
contrast to defence and aerospace applications which are usually special
• purpose designs. In such cases the controller algorithms are equally
individual, the objective being to satisfy highly demanding performance
objectives.
By the very nature of plant control system design such performance
objectives are unlikely to be attained; in fact for many situations they
4
aren't even necessary. Moreover it is a fact that plant operators often
disagree on the 'best' performance criteria and simply retune controllers to
meet their own needs. In the light of this it shouldn't be surprising that
the relatively straightforward 3-term (PID) controller is so widely used in
process control applications.
being
Such controllers are now almost entirely electronic
virtually obsolete and pneumatic ones confined
type, hydraulics
mainly to highly
hazardous applications. Until recently most systems employed analogue
controllers but now digital techniques are commonplace. Digital controllers
are significantly more flexible than analogue ones, can support sophisticated
man-machine interfaces (MMis), and can be integrated within large systems
using local area networking communications methods.
Thus there is a specific requirement for relatively low cost
'intelligent' controllers for use in plant systems, especially with the
perceived importance of local area networks (LANs) in future applications.
Any method which assists the operator in the commissioning and tuning of such
systems is a highly desirable implementation. Further, because of
commercial constraints, these controllers should be based on 8 or 16 bit
processor-s.
1.4 Thesis Object and Or-ganisation
This thesis describes · a microcomputer--based system closed loop for
the control of a mechanical actuator unit. Motive power- for- the actuator- is
provided by a 3-phase induction motor- controlled by a Pulse Width Modulated
(PWM).power amplifier, the complete loop being controlled by an Intel 8085
microprocessor through the use of a PID algorithm implemented in softwar-e.
An analogue controller- circuit is designed and built for- system
5
testing purposes and to enable transfer fUnction analysis to be carried out.
A digital computer simulation for the plant is carried out employing
the model derived from the transfer function analysis (TFA) tests to study
the effects on closed loop performance using various digital control
algorithm. From the digital simulation Computer Aided Tuning rules are
obtained and implemented to enable an operator to tune the actuator's
controller employing Man Machine Interfacing (MMI) methods. With this rule
the required performance for the system can be achieved without the need for
expert control people; no adjusting for the PID gains is needed as it is
carried out totally by the microcomputer. No other published work has been
found relating to the CAT concepts and techniques described here; this would
appear to be the first implementation of such ideas.
The thesis organisation is as follows:
In Chapter 2 the equivalent circuit of the induction motor is
presented together with the mathematical equations of the motor at its steady
state condition and its speed controlling parameters. Power electronics
control of the motor using PWM technique to control the frequency and the
voltage of stator is also presented. This chapter also contains an overview
on the use of power switching devices in controlling induction motor.
Chapter 3 describes the main types of inverters used for the control
of induction motors, concentrating mainly on voltage source inverters. The
design details of the prototype inverter, including drivers, power supplies
and controllers are also given in Chapter 3.
Chapter 4 deals specifically with the electronic control systems used
in· this work. Both analogue and digital controllers functions and
facilities are explained showing the tasks of using each of them in this
work. A detailed description of the electronic hardware designed to meet
6
the control functions is included,
Chapter 5 explains in brief the control systems and the performance
criteria of the controlled system, The traditional methods for testing
systems is also given in Chapter 5. The mathematical equations of the PID
controller and its operation are presented and derived in this chapter,
Chapter 6 investigates the practical approach used to identify the
transfer function of the system both in open and closed loop. A digital PID
controller is implemented, aided with the practical results, The CAT
algorithm is demonstrated and implemented using the microcomputer and the MMI
facility.
Chapter . 7 explains the software organisation implemented by the
microprocessor for position control. The Computer Aided Tuning and its
implementation rules are also explained in details.
The conclusion and comments arrising from this work are explained in
Chapter 8.
The prototype actuator (Figure 1.2) is an EMA with the dimensions of
38 cm, in length, 8.9 cm, in diameter, a shaft of 15 cm. stroke and its
weighing approximately 10 Kiloes,
It is driven by a 1/6 H.P. 3 phase 115 V. 60 Hz induction motor
through a gearbox which has a reduction ratio of 5:1.
The motor speed range is 0 to ± 2000 r,p,m, which gives a maximum
shaft speed of 1.3 cm/sec. Position sensing is accomplished through the use
of a rectilinear continuous track potentiometer mounted on the end of the
shaft.
A photograph for the prototype actuator is shown in Figure 1.3.
7
L-----..JP.A. feedback
response feedback
signal {optional}
Fig.(1.1) Position Servo Block Diagram
-------,38 cm.------+1•1
G. l-15clil....j [)J=· I ICJ \ \
5:1 gear
\ mechanical bearings
Fig.(1.2 I Prototype Actuator
shaft position sensor
1. HLP 190/SA 1 I 150/GK
\ \
\ \ i.
8
. : '-· . \
Fig.(1.3 l Electric Actuator Set-Up.
---------------
CHAPTER 2
I I
• I
' ' '
9
CHAPTER 2
2 Induction Motor Drives
2.1 Introduction
The three-phase induction motor used in the actuator consists of a
wound stator connected to main's a.c. supply and a squirrel-cage rotor having
no external connections. Compared with brush motors the squirrel-cage motor
is more reliable, smaller, lighter, has· lower rotor inertia and is cheaper.
Its major drawback has been the difficulty of controlling its speed or
torque, this traditionally being carried out by electro-mechanical systems.
Recently it has been economical to consider an alternative, that of high
voltage solid state semiconductor switching techniques operating under
digital electronic controller I.C.s.
2.2 Principle of Cage Induction Motor
The principle of operation or the cage induction motor is as follows;
When the stator winding is energised a magnetising current flows and results
in the production of a rotating flux in .the air-gap (Figure 2.1a), lagging
the voltage by 90 degrees. This flux induces a voltage in the short-
circuited closed-cage rotor winding causing rotor current to flow. This
current lags the voltage due to the nature of the inductive winding (Figure
2.1b); it also causes a reflected stator current to flow in order to
counterbalance it. Thus the total stator current (Figure 2.1.c) is the sum
or the magnetising and reflected currents. This figure also shows the
current flow in the stator which must flow by transformer action to balance
the 8
rotor current. The interaction between rotor and stator mmfs is to
produce a torque in the same direction as the rotating field with a speed of
rotation (synchronous speed) ns given by
ns =~ • 60 rev/min p
10
where, ~ is the synchronous frequency and Pis number·of pair of poles.
For power to be.supplied to the rotor, it is necessary for. the rotor
speed ~to be less than the synchronous speed. The difference between the
two speeds is characterised by the dimensionless quantity called slip s.
s = synchronous speed - rotor speed synchronous speed
2.3 Torque Speed Characteristic of Induction Motor
= n -n s r n s
Although the controller described here uses switching. techniques the
' starting point for motor performance analysis is to conside~ its behaviour
when fed with sinusoidal supplies. For this P¥rpose it is helpful to study
the equivalent circuits of the motor shown in Figure 2.2.
9 The basic per-phase equivalent,circuit at a slips is shown in Figure
' 2.2a. Considering the motor reduced to standstill with the mechanical power
1 -s output represented by the power loss in a resistance equal to Rr----leads to s
the equivalent circuit shown in Figure 2.2b. By referring the motor
impedances to the stator, and assuming the transformer to be ideal, the
equivalent circuit shown in Figure 2.2c is obtained. Finally, by applying
Thevenin's theorem, the equivalent circuit shown in Figure 2.2d is obtained,
where
(2.1)
•
in which
jXO(Rl+jXl)
Rl+j (XO+Xl)
11
E1 = input voltage per phase
R1 = resistance of stator per phase
x1 = leakage reactance per phase
Xo = magne~ising reactance
(2.2)
Assuming the power required for the core loss is included in the
mechanical output, the stator current/phase is:
\ = Et
((Rt+R2 )2 +
s
(2.3)
The torque developed by the motor is calculated by equating the
actual mechanical output at a speed Ws to the electrical power dissipated in
the equivalent resistor R2 1 ~s of Figure 2.2C.
i.e. TqWs (1-s) 2
= It ~(1-s) s
substituting for It from equation (2.3)
T q
.. (2.4)
------------ --- --~ ~
12
Figure 2.3 shows the relationship between slip and torque at a fixed
frequency. When driving the induction machine above its synchronous speed
by an external means, the polarity of the induced voltage and current is
reversed, the slip s is negative and the machine generates current back to
the a.c. system. The normal operating region for the motor is between
synchronous speed (s:O) and the pull-out torque at point A. The maximum
pull-out torque is found by differentiating equation (2.4) with respect to s
and equating to zero, giving the slip for maximum torque as
(2.5)
and by substituting this in equation (2.4), the maximum torque as,
(2.6)
Equations (2.5) and (2.6) show that the rotor resistance does not
effect the maximum torque produced by the motor, but only the speed or slip
at which this occurs. If for simplicity the stator parameters are
neglected, the equations for the current and torque reduce to:
I = (2.7)
and
T = q
respectively.
(2 .8)
Equation (2.8) has two asymtotes; for s large To<-1- and for s s
13
small Toes. Referring to figure·2.3, the operating region for motor action
is between zero speed (s~1) and synchronous speed (scO). For a slip greater
than 1, the machine is in a braking mode, a po·ssibility exploited either by
disconnecting the machine from the a.c. supply and injecting d.c. at the
stator terminals (dynamic braking) or by interchanging any two of the three
stator connections (plugging).
2.4 Induction Motors for Inverter Drives
2.4.1 Introduction
Induction motors have hitherto been considered as essentially
constant-speed motors though two major factors are altering this view.
These are:
i) The advent of static frequency inverters using thyristors or
transistors, which are becoming available at high power and reduced
cost.
ii) Greater awareness by industry or the economic benefits to be obtained
by using variable-speed drives for optimizing duty cycles and for
potential savings in energy.
As a result the induction motor is becoming increasingly used as a variable
speed element for many applications.
2.4.2 Cage Motor Speed Control
With the cage motor only stator control techniques can be used to J
achieve·continuously variable torque/speed performance. A simple method is
to use series resistance controllers in the supply line to the motor.
Unfortunately this causes a power loss and is unsuitable for large motors,
since it leads to torque variations at the output shaft. Variable voltage
14
control (say using a variac) is much superior; however it is unsuitable for
use in a full range torque and speed control system. For the reasons given
below it is essential to have full control of both supply voltage and
frequency.
2.4.3 Motor Performance on Variable-Frequency supplies
Figure 2.4 shows the torque/speed characteristics at a reduced
voltage and frequency values with a constant flux rate. These
characteristics show that the maximum torque decreases when working at low
frequencies due to the change in motor reactance and the large percentage
resistive volt-drop. Hence voltage boosting is used around 25 Hz to
maintain the torque-speed characteristic above the full load torque of the
motor. Saturation must not occur in the magnetic circuit when specifying
voltage boosting, which leads to an unacceptable electric noise and losses.
To run the induction motor direct-on-line may demand six times the
full-load current at rated frequency and voltage, hence inverter starting is
normally at reduced voltage and frequency. This increases the torque per
amp at locked rotor conditions; full-load torque can be obtained for
approximately full-load current as shown in Figure 2.5. The voltage and
frequency are then increased together to maintain air-gap flux while the
motor is accelerating to operating frequency. This procedure limits
operation of the motor to the stable part of the speed-torque characteristic
only, i.e. the section between no load (slip:O) and ·maximum pull out torque
as shown in Figure 2.6.
2.4.4 Variable-Voltage Supply
~ The torque-voltage characteristics for an induction motor are
~,Figure 2.7 which shows that it is possible to control the motor
shown in
speed by
15
. varying the supply voltage. Thyristors may be used in the fully-controlled
arrangement shown in Figure 2.8.a, where firing delay of the thyristors
removes sections of the supply voltage, so reducing the r.m.s. value of
voltage to the load. Waveforms associated with such voltage regulation are
shown in Figure .2.8.b. However, referring to Figure 2.7, it is clearly
shown that only a limited amount of speed variation can be obtained.
2.4.5 Constant Torgue Control
This type of speed control keeps the rotor flux constant for a wide
range of speed, which means maintaining the ratio of voltage and frequency
constant. The approximated formula for the magnetic flux produced at the
air-gap of the motor is given by
r/!=
where Vs
IZs
Ks
(Vs - IZs) i<s
f
= terminal voltage
= stator impedance volt drop at current
= constant for a particular machine
(2.9)
= 'I'
" rJ ~-
.. ! '" ill!··· ,.4, .... ~
It is clear that the voltage must vary with the supply frequency to
provide a constant air-gap magnetic flux , since the torque produced in the
motor is a function of~ as shown in Figure 2.9 •.
A boosting voltage should be provided at low motor speeds to overcome
motor losses and torques due to stiction and friction.
10 2.5 Pulse Width Modulation
18
Figure 2.10 shows a basic PWM system where two inputs applied to the
comparator consist of a signal and a carrier. The resulting output of the
modulator is a width-modulated reference frequency pulse-train. Hence, the
basic principle of PWM is the control of the duty-cycle of a switching
waveform by an analog signal such that the average voltage of ·the switching
waveform is proportional to the signal voltage.
The behaviour of the modulator for different input signals is shown
in Figure 2.11. With zero input signal, the output of the modulator is a
square wave having a corresponding zero average value(Figure 2.11.b).
However, if the input is positive the output waveform mark increases whilst
the space decreases; for negative values the converse is true.
11-12 2.6 P.W.M. Techniques
2.6.1 Introduction
There are three distinct approaches to formulate PWM switching
strategies. The first, and the one which has been most widely used because
of its ease of implementation using analogue techniques, is based on natural
sampling techniques. Regular sampling switching strategy, the second
method, is advantageous when implemented using digital or microprocessor
techniques. The third approach is that of optimal PWM switching strategy
based on the minimisation of defined performance criteria (such as
elimination or minimisation of particular harmonics).
2.6.2 Natural Sampling Techniques
Two types of modulation methods are used when employing natural
sampling techniques in analogue implemented PWM inverter. The first one,
illustrated in Figure 2.12, uses a sawtooth reference wave, producing single
17
edge modulation where one of the edges of the pulses occurs at constant
intervals of time. The second type, which uses a triangular wave as a
reference, produces double edge modulation(Figure 2.13).
Natural sampling has two disadvantages; firstly the centre of the
pulses are not equidistant or spaced uniformly and secondly it is not
possible to define the width of the pulses using analytic expressions.
Indeed it is possible to show that the width of the pulses can be
only defined using a transcendental equation of the form
(2.10)
where
tp = the width of the pulse
t1 & tz = switching instants
M.sinwmt is the input signal
Tc = the repetitive time of the carrier ·
13 2.6.3 Regular Sampling
This kind of sampling is now very widely used employing digital
circuits and microprocessor techniques. Two methods are employed, the~r
general features being given in Figure 2.14 (asymmetrical sampling) and
Figure 2.15 (symmetrical sampling). The asymmetric method of sampling for a
two-level pulse width modulator shows that the amplitude of the modulating
signal('a') is first sampled and then stored by the hold circuit. This
maintains each sample at the sampled level until the next sample arrives, and
so on(waveform 'b'). This is compared with the carrier signal ('c'); as a
18
result the points of intersection give the switching edges of the width
modulated pulses ('d'), where the width of pulses are proportional to the
amplitude of the signal frequency ('a'), In this type of modulation the
leading and the trailing edges of each pulse are determined using two samples
of the modulating wave, Therefore each edge is modulated by a different
amount. The width of the asymmetrically modulated pulse may be defined in
terms of these sampling times: thus
(2.11)
In the sYmmetric modulation only one sample is used to determine the
pulse-width, therefore both edges of the pulse are modulated equally. The
width of the pulse may be defined in terms of the sampled value of the
modulating wave at time t1
2.6.4
tp = 'lll2 [1 + M sin(wmtl >]
14-15 Optimal P.W.M. switching strategy
(2.12)
Optimised PWM switching strategies are usually generated by first
defining a general PWM waveform in terms of a set of switching angles and
then determining these angles using numerical analysis methods on a mainframe
computer. The purpose of this approach is to maximise a specified
performance criteria, while at the same time .eliminates a number of harmonics
or torque pulsations etc.
Figure 2.16 illustrates a particular optimised PWM waveform where the
switching angles, based on numerical analysis, produce mirror image quarter
cycle waveforms,
19
2.7 Power Switching Devices
There are two main types of power switching devices used in power
electronics inverters, thyristors and transistors. 18
Traditionaliy thyristors
have been used for these applications mainly due to their high voltage high
current handling capacity. However they need an associated auxiliary circuit
including commutation capacitors and auxiliary thyristors; further their
switching speeds are limited. Recent developments have resulted in a
'1.7-18 . modified thyristor, the Gate-turn off (GTOJ type, now being used extensively
for inverter applications. The significant advantages of the GTO are higher
switching speeds and elimination of the need for commutation capacitors and
auxiliary thyristors.
The other switching device, the power transistor, can be classified
into two main types. The first, the bipolar transistor, is well known and
widely used, having high voltage and reasonably high current ratings.
Unfortunately these are much less robust than thyristors and usually have to
incorporate protection circuits to prevent device failure in high power
applications. 1$-25
The second type is the power Field Effect Transistor (FETJ, which is
now becoming increasingly popular because they are fast, easy to use,
efficient and reliable.
2.8 Basic PWM Inverter
The basic 3-phase PWM inverter using thyristors as switches is shown
in Figure 2.17.a, the switching condition sequence of each thyristor and the'output
Inverter techniques and their
electronic implementation are discussed in detail in chapter 3 of this
thesis.
'"'
Rotor conductors
stator windina
20
(b)
Renected stator current
To1al stator current
(r)
Fig. (2.1) Principle of Operation for the Cage Induction Motor
Rr
( a l
Rr Xr
( b l
x,
( c l
It ( d l
Ficr. (2.~) Incluction Motor Equivalent Circuit
-1 2
Braking
0 1
Motoring
Synchronous Speed
Generating
Fig.(2.3) ilrque/Speed Characteristic at Fixed Freq.~ency
2 Speed -1 Slip
-c ~ a
0
140
120
lOll
•o
zo
0
22
10Hz . 50Hz~
.... , 2S¥. boost ,.,it:"' \
\
Full · ----------load
·JOO 600 900 1200
Speedr/min
Fig.l2.4l Torque/Speed Characterstic At Constant Rux
ISOQ
Per unit 0.5
Frequency 1. 0 apliied freq./ra rod
Fig. ( 2. 5 l Starting Values Related to Frequency For Constant Flux
- ----- ---------:--------------23
Torque
Speed
Stable reg•on of torque curve
Fig. (2.6) Torque-Speed FreqUencies
Characteristic for Diffe~ent Supply
.. ~
f! g
~ ~ ..
11.
7.01------Motor torque •t raaed
SlaiOI voltage Vs
1,5
1,0
0.5
o L:::::~;:::::t:~====~====::==::~~_..Per L unit
slip 1,0 0.8 0.6 0.4 0.2 0
I· ·I Range of speed control
Fig.(2.7) Speed Control by Stator
Fig. (2.8)
3-Phase supply ~·,------4
a) Fully Controlled Load Configuration
' ' ' ' ,,, I a 60"
:t :1 '•zl
a •l "
,,, I 11 I•
" ,,
" " '••I " " ,I '· ,,, I ~ •' I, ,I '•
'•' I ~ ·~ I,
" 11 ,.
' '·
""···
•rt
;. :~ ,. I'
•• lo
11
"
I~ I
:~ " I' 11 ol I' I' I' I 11
I
:. : . '• lo
" ,, " 'I
Supply phase voltaaes
Firilll pulses
r,_r,~ Line 1 1
current I
Load line voltqe
' lo lo
'• :I ,I
: :-;,/ Th)'ristor voltage
b) Associated waveforms
Controlled Voltage Supply
. ::::> a: 1.0
> G.l Cl
~ 0.8 f;
i ~ 0.6
0.4
0.2
------
------------------------
Boosted Volts
/ / Constant :i.
/ /
/-- f
10 20 30
Supply Frequency Hz
40
Fig. (2.9) Voltaqe/Frequency Characteristic (Constant $)
50
N en
26
Comparator
signal ·.'-:\:r
carrier NV\1\ output
Fig.(?,lOJ Basic PWM System
carrier signa I
~ 1\ j A t)l\ 6 rv--v-v-v-v--v--\ m,ark
t space
~ meduim M.!.
A/\!\!\!\!\!\ /V\/VVVV\
!JJ zero Ml.
A-AAAAA-/A V ; V
SJ high M.I.
Input
Output
M.!.: modulation index
Fig.(2.11) Modulation Behaviour
27
;f1 1:;; " :
" ~~ i i ' .. ! ! ;mod~iat ed signal :: .. .. ; .. :; . ..
' ·- ;...._•: ' ; ;,.... .. ;: ·,...
Fig.· {2.12) Jo!atural Sampling - Single Edge Modulation
modulated signal
·- / ....-- r-
. . . . . .
Fig. {2.13) Natural Sampling- Double Edge Modulation
+
Fig. (2.14)
28
. . . . . . . . .
.... ...__
PWM 0/P
2-Level Regular Modulation
Sampling Asymmetric
.
ila b· c
,..-r=~w.l_,a" / \'\
• • • • • • • 0 • •
....._
PWM 0/P
a: Si91al b: Sampling Instants c: Carrier
Fig. (2.15) 2~Level Regular Sampling Symmetric Modulation
..... I ...
I".., -1--11"/2-1
29
I 1f" I
-------21f" ------
Fig. (2.16) Optimal PWM Technique
r, o, T3 03 Ts Ds la
+ I fvab I I ' ib V,~ - ~c - -.,
ic Tr. Dr. T6 D6 D2
a) Circuit Diagram
I Rc:ference sinewave phase A
Reference sinewave phase 8
;: D Reference sinewave phase C
-'"'"'"'""" ~1~1~La.U--U..U-a~wp~~-----·--L•~·L-~·&-~-Ig2!.11 • ..__. • .__. _____ .._. _____ .._._~-----•L...P&...-1P--
i 31 • . - -- -- . . . .. - --- - . . . --i~4L.. i9st. ~6o· .. u.~--~------..... ----..... L.-&--~------.. "'!t"'. - - • • • - - •
•. 'v r-L.. L.. ~ ,.... L
t"- v IL 11. ..JU
(b) Output CUrrents and Voltages Waveform
Fig. (2.17) 3-phase PWM Bridge Inverter
Gate current pulse periods.
Line YOII:tge
CHAPTER 3
31
CHAPTER 3
3 Inverter Design
3.1 Overview
The basic transistorised three phase bridge inverter shown in Figure
3.1 comprises six power transistors T1 TO T6 and six diodes D1 to D6. The
inverter operates such that the direct voltage supply is chopped and applied
sequentially to the stator windings of the induction motor. The motor
behaves like a filter, responding mainly to the fundamental of the voltage
applied to its stator windings. Hence the current flowing in the motor
approximates closely to the sine wave, with the closeness of the
approximation increasing as the switching frequency is raised. For correct
operation, transistors 1, 3 and 5 are driven by a 3-phase signal train while
transistors 2, 4 and 6 are driven by a delayed, inverted version of these
signals (Figure 3.2). Only four transistors are shown here in order to
keep the diagram clear. Diodes D1 to D6 (Figure 3.1) are necessary to allow
electromechanical energy in the stator windings to return to the supply rails
when using dynamic braking methods.
Inverter drives for cage motors can be split into three main
categories
(a) Quasi square wave
(b) Pulse width modulated wave inverters
(c) Current source inverters
3.2 Inverter Types
3.2.1 28
Quasi Sguare Wave
This type of inverter, Figure 3.3, is probably the easiest way of
producing a 3-phase supply from a static source. Three inverter outputs,
32
u.v.w., are switched every half-cycle between the d,c, rail supply source to
give the output voltage waveforms shown in Figure 3.4. Each phase of the 3-
phase bridge switches as a square wave with equal mark-space ratio, switching
displacements being 120 degrees, As a result the voltage waveshape between
any two lines is as shown by VuN• the corresponding current waveforms being
those of Figure 3,5,
In order to produce constant torque in the induction motor when
driven by this type of inverter the de rail voltage must be set in accordance
with the drive frequency, varied so that it is directly
proportional to frequency; this requires the use of an additional circuit
which is typically either a phase-controlled rectifier at the input to the
inverter or a pulsed output arrangement, However, it is not practical to
operate the motor continuously at speeds below that equivalent to 5 Hz due to
27 high torque pulsations,
3.2.2 28
Pulse Width Modulated Wave Inverter
In this type of inverter the output voltage is synthesised by
switching the output devices at higher frequency and at the same time
modulating the on-off time of these switching devices (Figure 3.6), i,e,
controlling the mark-space ratio of the output voltage waveform. Several
variants of this system are in use including controllers that give a variable
carrier-frequency over the inverter operating range for improved performance.
PWM. sine-weighted inverters tend to produce better motor performance
characteristics and higher efficiency, These benefits are particularly
apparent below 5 Hz.
Figure 3,7 shows how the motor drive supply is produced by a pulse
width modulated equipment, these waveforms being typical of phase and line
33
voltage. In this arrangement the output switching devices are used to
control. both the output voltage and output frequency. Hence the d.c. link
voltage can be a fixed value obtained from a diode bridge rectifier as shown
in Figure 3.8. A smoothing circuit is coupled to the diode rectifier to
give a constant d.c. voltage to the inverter bridge and to protect the diode
bridge due to the change rate of current di/dt.
29 Current Source Inverter
This circuit normally uses a controlled input rectifier followed by a
d.c. choke to provide a controlled current source as shown in the block
diagram of Figure 3.9.a. This is fed to an inverting stage which is used to
sequentially switch the controlled current from one phase of the induction
motor to the next. Since the inverter is supplied from a current source it
is protected from transient current surges arising from rapid load
variations.
Commutation of this inverter employing thyristors is achieved by a
charged capacitor network discharging in a resonant mode through the leakage
reactance of the motor. Hence, large voltage spikes can appear at the motor
due to the thyristor commutation as shown in Figure 3.9.b.
The disadvantages of this inverter are that it cannot be used to
control more than two motors in parallel, and motors using this control
method exhibit pulsating torques at low frequencies.
3.3 System and Circuit Design
3.3.1 System Structure
The typical system block diagram is shown in Figure 3.10. The
incoming 3-phase a.c. supply'is stepped down by a 3-phase auto-transformer to
an r.m.s. voltage of 115V. This voltage is rectified and smoothed to
produce about 160V and this is fed to the three-phase inverter via a current-
sensing circuit, The inverter chops the d.c, to give an output of 160V
peak-to-peak pulse width modulated at a maximum frequency 1 kHz. This
output is fed to the a,c, motor which responds mainly to the envelope of the
PWM switching frequency.
The six PFET switches in · the inverter are under the command of a
waveform-generation circuit which determines the conduction time of each
switch, Because the control electrodes of the six switches are not at. the
same potential, the outputs· of the waveform-generation circuit must be
isolated and buffered. A low-voltage power supply feeds the low-power
signal processing circuit, and a further low-voltage power supply drives a
transistorised switch-mode isolating stage to provide floating power supplies
to the gate drive circuits; The complete circuit diagram of the inverter
driver system is shown in Figure 3.11.
3.3.2 Power Stage General Description
3.3.2.1 Introduction
This section is concerned with the design aspects of the switching
30 voltage source inverter to amplify the pulse width modulated signals and feed
them to the motor,
·rn Figure 3.12 the PWM bridge inverter circuit is shown. Each arm of
the inverter consists of a Power FET (PFET), a commutating fast recovery
diode connected in anti-parallel and a series reverse recovery one to prevent
the power FET body-drain diode from conducting(discussed later).
35
3,3.2.2 Power FET
The advantages of PFET are as follows: 31
(a) Simple drive circuit: driving of the Power FET is easy and simple
(b)
(c)
when compared to other switching devices. 32
Fast switching times: the rise and fall times are dependent on the
drive capability of the gate control circuits; nevertheless turn •on'
and 'off' times of 50 nsec are easily achieved.
33 Suitability for parallel operation; parallel operation of FETs can
be implemented because current sharing iS automatically produced by
the positive temperature coefficient of the Drain-Source •on'
resistance.
(d) No second breakdown
The major disadvantage of the Power FET in inverter systems is caused
by its excessive reverse recovery time after carrying reverse current.
Owing to the structure of the Power FET (Figure 3.13) a body forward diode is
created between the source and the drain of the transistor; this exhibits a
low forward voltage drop due to its large area •
. Consider the situation of Figure 3.14. Here a single branch of an
inverter is shown with the load in the centre and the critical moment in the
switching cycle. If the load current flows in the inverse diode of the top
transistor as a freewheeling current and the bottom transistor is again tuned
'on', then the full supply voltage is present at the bottom transistor.
Throughout the reverse recovery time of the inbuilt inverse diode of the top
transistor the bottom transistor conducts not only the load current but also
the reverse-recovery current; this inevitably leads to destruction of the
lower transistor. Added to this, the bottom transistor must also handle the
36
full intermediate-circuit voltage during this time. There are also
secondary effects arising from the parasitic npn structure in the transistor
which, at high currents, can destroy the upper transistor.
As the result of that it is essential to use an external, fast
34 recovery, anti-parallel diode with each transistor. Unfortunately, during
reverse recovery action, the internal (transistor) diode exhibits a lower
voltage drop than the external one and so still carries reverse current. It
then becomes necessary to prevent any reverse· current flow through the
transistor, this being accomplished through the use of a diode connected in
series with the source terminal of each transistor. This is called the
'reverse recovery diode'.
Figure 3.15 shows the behaviour of the upper transistor current and
phase voltage at one of the three branches after using a series diode
blocking the inverse diode of the Power FET. Figure 3.16 shows the free-
wheeling current and the phase voltage of the same transistor. Observing
both figures exhibits that while the transistor is on the freewheel diode is
'off' and vice versa.
35 3.3.2.3 Power Devices Design Criteria
The main power switching transistor and the recovery diode are
selected initially on the basis of current rating IT (av) and IF(av)
respectively, and peak voltage ratings VoRM and VRRM where:
IT(av) = average forward current through transistor
IF(av) = average forward current through diode
= repetitive peak off-state forward voltage across
- 37
transistor
VRRM = repetitive peak reverse voltage across diode
For the voltage ratings, assume a safe design figure is:
main transistor VoRM = main diode VRRM= Vdc (max)+50
For the worst case current ratings, assume that the current is approximated
by a half-wave rectified sinewave giving:
fi = Ir(av) = Im(max). • TI
The peak current of the transistor is the peak load current, and the
corresponding peak current of the diode is the sum of the peak load current
and the peak commutation current. The following approximation can be used
for the selection of the transistor:
ITRM = 5 • Ir (av)
where ITRM is repetitive peak forward current through the transistor, and
for the main diode:
IFRM "'20 • Ir(av),
where IFRM is repetitive peak forward current through the diode. The
antiparallel and series diodes have the same characteristics. The design
parameters for power devices are listed in appendix AJ.
38
3.3.2.4. Power FET Driving Circuit
Driving Power MOS transistors is relatively easy,· The total power
~eeded is very small; all that must be provided is the capability to charge
and discharge the Gate-Source capacitance (typically between 1 and 2 nF) by a
few volts in a short time (typically less than 100 ns), This ensures that
the quality of the waveform is not degraded and that switching losses are
minimised, 36
. The six PWM signals generated by the dedicated LSI chip type HEF4752V
are coupled to the Power FETs gate driver stages via opto-couplers. Figure
3.17 shows a driver circuit coupled to the upper switch at one of the three
inverter branches. Note that the source terminal of the upper Power FETs
are connected to the inverter output and switch up and down at high voltage
rates, while _the PWM controller is referenced to zero volts,
The output side·of each opto-coupler is powered from one of the four
floating power supplies. The lower three stages share a common power
supply, as the source terminals of the three Power FETs are all at about the
same potential; each of the three upper stages has its own floating power
supply.
Referring to Figure 3.17, the isolated signal from the opto-coupler
is coupled to the gate terminal of the Power FET by quad CMOS Schmitt circuit
augmented by output transistors. This gives ·rise to a low impedance gate.
drive signal for the power switch, This feature is not required in the de
condition but is essential if fast switching operations are desired where the
inherent input capacitance of the gate circuit is a problem. This is
_further complicated by the Miller capacitance effect produced during device
switching.
39
Controlling Circuits
3,3.3.1 LSI Chip PWM Controller
The basic function of the PWM IC, (block diagram, Figure 3.18), is to
provide three complementary pairs of output drive waveforms which, when
applied to the six-element inverter, open and close the switching elements in
the.appropriate sequence to produce a symmetical three-phase output. The
output waveforms are thus six sinusoidally modulated trains of carrier
pulses, each pulse having both edges modulated; as a result the average
voltage output between any two output phases varies sinusiodally as shown in
Figure 3. 19.
This PWM controller chip is supplied with an input clock frequency
that is always an exact multiple of the inverter output frequency. At lower
motor speeds the switching frequency is derived from higher multiples of this
in order to improve the pulse distribution; this which results in excellent
phase and voltage balance and consequent low motor losses. A 15-fold
carrier multiple is used only for highest motor speed range while 168-fold
carrier multiple is used at lowest motor speed range, Hysteresis between the
switching points is included to avoid jitter when operating in these regions,
this is clearly shown in Figure 3.20.
The induction motor is governed by the general expression
V = N d~ d't'
so that to maintain constant flux, the voltage-time product Vt must be kept
constant, The IC controller automatically satisfies the requirement by
making the output voltage directly proportional to the output frequency.
Figure 3.21, which is a spectrum analysis of the PWM waveform as a function
40
of the drive signal frequency, shows this effect,
The IC controller sets i~s output in response to three input signals,
clocks FCT and VCT and logic signal CW. Maintaining VCT at its recommended
value and varying FCT controls the speed of the motor at constant flux rate
i,e, V/f constant, Varying VCT increases or decreases the modulation depth
of the fundamental frequency (Figure 3.22) and is used for voltage boosting,
The other control pin CW is used to control the direction of rotation of the
motor by altering the phase sequence RBY to RYB.
Figure 3,23 shows how the chip is coupled to the inverter through a
buffering circuit, Separate control logic provides the controlling signals
for the LSI Controller to set the output frequency and voltage supply to· the
motor. Figure 3.24 and Figure 3.25 are recordings of typical line and phase
voltages applied to the motor at a fundamental frequency of 60 Hz. Figure
3.26 shows the relation between the motor line current and voltage at a
fundamental frequency of 60 Hz.
3.3.3.2 Overcurrent Protection
One of the disadvantages of the voltage source inverter arises from
its low impedance source, which makes difficulty to protect the inverter from
overcurrent in case of shoot-through or short between inverter terminals,
Generally inverters may be provided with an overcurrent protection as
follows:
(a) Turning off all switching devices.
(b) Fusing
(c) Turning on all switching devices,
(d) Turning on or off additional switching devices external to the inverter,
(e) Current limiting reactor.
41
(f) a.c. circuit breaker.
(g) d.c. circuit breaker •.
Combinations of the above items may be used in an inverter to achieve
37-38 the most effective overcurrent protection performance.
The prototype overcurrent protection circuitry provided with the
inverter detects the d.c. line current by means of a low value resistor
connected in series to the -ve d.c. rail as shown in Figure 3.27. In the
event of short circuit or shoot-through the protection circuit signals the
PWM controller chip and switches it 1off 1 • The overcurrent protection
circuit works in the following way: when the power supply is first switched
on the protection circuit provides a logic zero at the output Q, this being
fed to pin L of the controller chip, so turning it 'off'. When switch S1 is
set a logic 1 1 1 is provided at Q switches 1on 1 the PWM controller, and the
inverter is activated.
Current monitoring is carried out by R1, the detected voltage being
amplified by IC1 and applied to IC2. This is a comparator network. which
changes state at· a threshold level set by VR2. Thus when an overcurrent
condition is met the output of IC2 changes state , signalling the logic
circuit via the opto-coupler and resulting in switch-off of the PWM
controller.
Opto-isolation is used because the potential of the current detector
is different from the other controlling circuits. The PWM controller can
also be switched 'off' manually using switch S2.
A demonstration of the protection circuit in action is given in
Figures 3.28 and 3.29; here an inrush of the d.c. rail and motor line
currents caused by a step input command activate the protection circuits.
Figure 3.30 shows the resulting digital signal which is fed to the PWM
42
controller.
3.3.4 Power Supplies
3.3.4.1 Inverter Power Supply
The-rail d.c. voltage supply for the inverter is obtained from the
rectified, smoothed output of a 3-phase auto-transformer as shown in Figure
3.31. The equations for the smoother circuit are included in appendix A,
the design requirements being to supply 4 amps at d.c. with a voltage ripple
of approximately 1~, and meeting the following parameters;
Vdc(nom) = 155V
Vac(max) = 178.8V
Vdc(max) = 258.8V
The rectifier must be capable to withstand more than Vdc(max) for
worst case and a current of 4A. The function of the shunt resistor across
the bridge rectifier is to dissipate the electromagnetic power caused by
dynamic braking since this cannot be returned to the supply due to the
presence of the output rectifier. The other function of the 10 K shunt
resistor is to act as a discharge resistor for the smoothing capacitor.
3.3.4.2 Driver Power Supply
The requirement here is to provide-four isolated power supplies as
shown in the block diagram of Figure 3.32. Each of the three upper power
switches is provided with a floating power supply while the fourth power
supply provides +10V to the overcurrent protection circuit and the other
three power switches.
Figure 3.33 shows the switching mode power supply (SMPS) which
provides the control voltage supplies for the inverter. It operates as
43
follows;
Monostable oscillator IC1 generates a square wave at +5V and a
frequency
through an
of 200 KHz. Two transformers
emitter follower circuit, each
rectified by a single diode and smoothing
are coupled to the oscillator
secondary winding output being
capacitor, These supply a d,c,
voltage of 10 volts for the drivers of each power switch,
3.3.4.3 Control Circuit Power Supply
The control circuit (Figure 3.34) is designed to supply ± 15 volts
for the linear circuits and +5V volts for the microprocessor and the linear
circuits.
A standard power supply transformer, type MT 79FT is used, .having a
primary voltage rating of 240V .and two secondary windings rated 1A rms each.
The 15 volt tappings are used for the split regulated power supply ±15 volts.
Approximate calculations were used to assess the suitability of the
transformer, these being given in appendix A.2.
The 5 volts supply is provided from the rectified +15 volts through a
regulator type LM309K. This is capable of delivering currents in excess of
1A from a rectified input voltage in the range of 7 to 35 volts.
44
V. D. C. os
06
Fig. (3.1) Basic Transistorised Inverter
(a) Bridge Circuit
on off
"-----~"~ /.. J. .I I .... i : ~i otf
- ·---~--------~ -1111-(b) Switching Action waveforms
Fig. (3.2) Transistor Switching Action
V
+ ss
Voc ~u -v
S2 S4
ov--------~---J----~
Fig. ( :i. 3 ) 3-phase Quasi Square Bridge Inverter
1 u_j_ I I Voc ov - - - f - - - - -
V ... I I I ov - - - ------!
U.l/ VDC '------ ,...... L- ----....-t OV
Fig. (3.4 l Quasi Square Switching Waveforms
Voltage
Fig, (3.5 i Line Current and Voltage 0/P Quasi Square Inverter
vu
vv
I
Inverter line /voltage
ov
Fig. (3.6) · Line Current and Voltage waveform of PWM Inverter
....--- ..--- ;- ,... ;--
---- '- ---- -.. -· ·--'---· . . ••• L...-
,... - - ........ ,...
_,~
- ··'-- --- ...._ --- .... -. -- .. - ...... L- ---- L-- -- ··'-
-- L-. _L-- L-.---,. ;--- • . - ,... • r- . . ··..- • .,...__..J '-
.__ .... I- 1- L..
Fig. (3. 7) Voltages Waveform of PWM Inverter
47
Rectifier L P. E ... Inverter TT
* :~~ Output
Fig. (3.8) Block Diagram of Voltage Source PWM Inverter
3tD Input -
(a)
Curr~nt
Voltage
Convetter D.C link Inverter "YTY
.{>!:'
Block diagram
(b) Motor Current ;md Voltage ~laveform
Fig. (3.9) Current Source Inverter
.
Output
240V ""v
~~~ Mains Rectifier -115V & - ~ > f-+-<-~ Smoothing
~ > - ..6 ( * ,- Current De tee tor
Isolated
Power Supply
240V low-Voltage
""v Power Supply
Fig. (3.10) System Block Diagram
3-(/J Inverter
® * ,. Gate-Drive Buffers
R.
Signal Isolation
4
Waveform
Generation
..--I
Cage Motor
-"' -
User
Control
}
,. CD
uc l•b
From P.T. 0r1v"'!lil:, T x1 ~ R11 ccr-,1 p-Z.2p • >- ""'u • Dl
\_ • 'r ·9. lOp
• >- 1 • '-::::02,.. ~~-,.......,
: >- "h . : ~ ,;;~
J!2op . Ju
R12 CIO ::= L..!KI 120p
Rll
C7
r--- -~!o-r- """ lOp
r- ~o~~K 1CI Cl
R19
lKI ~ 06 r-1 R9 I! -i~-r. lr.~. ~-~-~- ~~~y .[, . ! H>~ ~~CJ:ooloKI I I
'--'Won L 1C5 -- f--...l LJ'> r-r--t---1--1-~
..,.- ~ I J~ I ! Rll R20 • 'I I R7 1K2 15K "" OKI
RlllO - .-JUl. I RI 2K2 IC36 •
"' I ~ ;J ,lllL. 2K2
~rs1~~ 1.~ e_HTH-~c:::J2-K2 _ _, 1
1 ••
1'F-.. -,7 t-J__-==-::iiiiiiillifiliiiillBJ[C===== J 7 K t....:= - ..1!.1BllllilliMI!ER CC!.__
• • ~010
R~1) ~l20p
I~ __!!27
R~16
IK~ 120p
~>--- Rll r~:~~J TR14 c~ lKI 10~
lr11 f-1.1,\0l:l f" --1--, H> I:: -Jr. 1, ~ 1Jf I i 11- ? I ,_y !!I I [ ,......._
,,,2 J Lk!_ __ ~J Lf(rv 1C14
~~014 -(-'
Fig.l3.11) P. W.H. MOTOR CONTROL POWER BOARD.
TR1f
Cll :
tO On
TR20 ~
' I
I I
'
50
Bridge s_ill sill sill
11SV "v Rectifier
+ c R y B
s.l!J s.hJ sh.]
-~------~~~------~--~------~--~--~ ....__ __ _,
Fig. (3.12) The Prototype Inverter
Drain
Gate
Source
Fig. (3.13) Power FET Structure
51
+-------r--------------~
lt.
Fig. (3.14)
:W01" . . . . . . :~·: :~~.---•__:_______! . . . • • •
• •• I ' :
-~------\ Turn On Losses in Inverter
t
t
t
Fig. (3.15)
Fig. (3.16)
52
Upper Drive Current and Phase Voltage
Upper Trace-Transistor Current Lower Trace-Phase Voltage
v.
1SOV.
2A.
100V.
Upper Freewheeling Diode Current and Phase Voltage
Upper Trace-Diode Current Lower Trace-Phase Voltage
53
D.C. Rail
·-·-·-·-·-·-·-·-·-·-·----, I . .sv-----,-----,---, j . I
1K1
PWM Signal ----1
ov---1
! ! 3K8 I
I ' ·········-.·· -·-·
Opto-Copper I
·-·- ·---· . ·-·-----·-·-·-·-
+-.._-R to the motor
· to lower P.FET -10V
Fig. (3.17) PFET Driver Circuit Diagram
CW Controlling Signals r·--·-- ·--·-·-- -·~·--·-- ·--·-. I I .
FCT I ~ Counter
!--Decoder
~ ~ I 1 Output
I Stages I !
VC T ___J I Counter .
1 W. I
FCT
VCT
RC T I I Counter r--RCT
-·--·-·--·--·-·-·-·-·-·-·
l _j
Fig. (3.18) LSI Chip PWM Controller Block Diagram
PWM
Clocks
carrier
Vp,_y
Fig. (3.19)
fs inverter switching frequen
!•~~>> t25
1.0
0.75
8 60
54
PWM Controller Chip 0/P Waveforms
0.5 168 pu{ses
0.25
0 10 20 30 40 so 60 70
Output Frequency
fs {m~xi
80
Fig. (3.20) PWM Controller Chip Hysteresis Switching Frequency
55
Fig. (3.21) PWM Controller Frequency 0/P Spectrum
a) Without Boosting
b) With Boosting
Fig. (3.22) PW Modulated TTL Signal 0/P(from the Controller Chip)
2V
40% Boosting
56
·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-· Inverter
13
5 8
6 HEF
22 3 MC 17 lt/52V 9
12 21 140508
4 2 2c
24 Buffer
LSf Chip • PWM Genera tor I
L--·-·-·-·-·-·-·-·-·-·-·-·-·-·-·~
Fig. (3. 23) PWM Controller Interfacing Configuration
Fig. (3.24) Motor Line Voltage Waveform msec.
Fig. (3. 25) Motor Phase Voltage waveform
OCJhol
R1 JA
Fig. (3.26)
·IC1 "•
ov
VR2 WK
ov
lOOK
5-7
Motor Line Current and Voltage Waveform
Upper Trace-Line Current Lower Trace-Line Voltage
.sv
l'IOA
"''
ov
ill dodts typ• OA 91
Fig. (3. 27) OVercurrent Protection Circuit Diagram
1A.
100V.
a n topin.L ot~
PWH ControU•
58
Fig. (3.28) DC Rail CUrrent at a Step I/P
sec.
Fig. (3.29) Motor Line Current at a Step I/P
Fiq. (3. 30) Generated Switch-Off msec.
D.C. Rail current
TTL Signal
Motor- line current
TTL Signal
Motor line current
SA.
2~0V "'-'
3-Phase variable transformer
Fig. (3. 31)
I --- --- --- --- --- --- -, r - -- - 1 I 0 DC 0 •
I _L I _L : : I I ~ 160V tothe
t_ _____________ _ Bridge rectitie r
Voltage Supply and Smoothing Circuit
RI I10K
L-- -- _J
Smoothing circuit
Inverter
350pF
0
en CO
\
Transformer Rectifier Smoother Driver 1
Oscillator Power Stage .. 1
1 Rectifier Smoother Driver 3
Rectifier Transformer
Smoother Driver 5 g
'z'
l Rectifier Smoother Drivers 2,,6 '
Fig. (3. 32) DC-DC Converter Block Diagram
------- -----------------------------------------------------------------
+1 5 V.
1K2
...... Tx.1 ,I • .22K
1~1
F +: =l=10j!F
Driver To '<1- •ni. > 1--:....~ ~ Ul
~ 1
r( > :'1 " > .....
2K2 L( -< ....
...... • 1- -< I;" VI
=?_ +10pF 3 : : 2.2nF -< > 10Jl F : -
..... r >-
-==->-
switches
1
3
·1SV. ...,
...... • Tx.2 VI J; ~
1opF T- T10vF 5 1-SV.
5
>-1!1!lPF < < ....,
f I I + I .... I (040478
11 I < • ~ ,J -
VI
10~F+ , . , 11 1- < ~ 30pF I: ; 2 :-to r > ~ 4K7 3K3 10K >-
1- >
2
~ ~ 1-
I+ .,:. 10~F
4 t--
All diods type OA 91 ·10V 0 +'0 V • transistors type ZX 451 ~ 551 To current detector
I+ circuit 1~F 6 - 6
Fig. (3.33} Drivers Power Supply Circuit Diagram
.6 R •15 V
R3 3K9
Rv 2K2
LH .sv 309K
+ 47001JF Vs 01 240V
1\) N
0 ~
10K
.6 R
Fig. (3.34) Control Circuit Power Supply
CHAPTER 4
63
CHAPTER 4
4 Electronic Control Systems
4.1 Introduction
Two distinct types of electronic control systems have been developed
as part of this research project, an analogue controller and a
microprocessor-based digital unit. Each one of these has been employed with
specific research objectives in mind as follows:
(a) The analogue controller is required for:
•Testing the inverter-motor behaviour for variable input signals.
•Evaluation of the open-loop and closed-loop performance of the actuator
system,
•system identification (transfer\functon analysis) in the continuous time
domain.
•studying the effect of the overcurrent protection on acceleration/
deceleration performance of the actuator unit,
(b)'The digital controller is used primarily as the closed loop position
controller, However it also supports Man Machine Interfacing (HMI) with
the control system via a keyboard/display console and is essential in the
implementation and evaluation of the digital control algorithms and self
tuning features.
4.2 The Analogue Controller
4.2.1 Functions and Facilities
(a) Functions:
•Provides protection features for the inverter under all operational
conditions
•provides constant-flux operation within the motor
64
*provides all signals required by the inverter LS1 PWM controller chip.
*Interfaces between the operator and the inverter-actuator unit.
(b) Facilities
*Adjustment of motor speed in both directions from zero to 1.5 times its
nominal speed
*Adjustment of motor (inverter) acceleration and deceleration rates.
*Limitation of regenerated power during speed deceleration to protect the
inverter against overvoltage.
*Adjustment of starting torque values via 'IR' compensation.
4.2.2 System Operation
The block diagram for the open loop system is shown in Figure 4.1,
and consists of the following sub-sections:
(a) ON-OFF circuit: This controls the inverter on/off function in response
to external push
conditions.
button controls or inverter overcurrent fault
(b) Potentiometer: This controls the motor speed in both directions.
(c) Soft start/stop circuit: Ramps the voltage output from the potentio
meter.
(d) Acceleration deceleration circuit: Adjusts the time constant of the
ramped voltage •
. (e) Direction Detector circuit:
motor.
Alters the direction of rotation of the
(f) Absolute value unit: Provides positive voltage for both positive and
negative input ramped voltages.
(g) Voltage-controlled-oscillator (VCO) and Control Logic Unit:
clocks needed by the PWM controller chip.
provides
38-40 Circuit Operation and Design
(a) Speed Control Unit
65
The inverter is controlled using a soft start mode, this action being
carried out by the circuit of Figure 4.2. Demanded speed is set by
the potentiometer, VR1, its wiper voltage being applied to the comparator
IC1. IC1 output forms the input voltage VN to the integrator IC4,
giving a ramp voltage output (VI); this is also the feedback to the
noninverting input of IC•. Thus VI is ramped at a time constant
proportional to the resistor Rx, the feedback capacitor ex and the
acceleration/deceleration circuit reference voltages VR2 and VR3. The
output voltage VI is fed to the absolute value unit and also to the
direction detector circuit. The direction detector circuit output,
which is TTL compatible, is either a logic '1' or 'O' depending on the
polarity of VI; it is connected to the direction control pin of the PWM
control and so determines the direction of rotation of the motor.
(b) Absolute Value Unit.
The absolute value unit is employed to provide positive output voltages
to the voltage controlled oscillator for both +Ve and -ve~input voltages.
Its circuit is shown in Figure 4.3, where IC6 and its external components
act as a precision rectifier providing +Ve voltage only to IC7 amplifier.
Also fed to IC7 is the offset adjust voltage from VR2. This is used to
set the minimum required output voltage (VO) from IC7, its maximum output
being limited by VZ3. \The circuit characteristic is shown in Figure
4.4, with its behaviour under- transient conditions shown in Figure 4.5
(bottom trace). Here the speed selection has been changed from forward
to reverse direction. Also shown here is the behaviour of the motor
line current (top trace).
66
(c) VCO and Control Logic Unit \ Figure 4.6 is circuit diagram of the VCO and control logic unit, There
are two distinct parts to this subsystem, the clock generator and the
voltage to frequency (V/F) converter,
All clock signals
multi vibrator.
are generated by the MC14047 astable
The functions of the controlling clocks, veT, RCT and OCT are discussed in
Section 3.2.3.1. veT is kept constant at 300 KHz. RCT is fixed also
at 300 KHz, while OCT operates at a frequency of 600 KHz. These clocks
are generated by a monostable multivibrator circuitry employing the I.e.
chip type MC14047. V/F conversion is performed by the Me14046 phase
locked loop I.e., its transfer characteristic being that of Fig 4.7.
4.3 The Digital Controller
The digital controller can perform all the functions required by the
analogue one. However due to the programable nature of the unit it can be
made more flexible in operation, allowing the following functions and
facilities to be incorporated;
*Evaluation of various digital control algorithms
*Programmable Microcomputer-based control of the electric actuator
*Interactive man-machine interfacing, providing facilities for using the
VDU as a development system, and simplifying software debugging,
*Evaluation of parameters and data structures of the control algorithms,
*Development of Computer Aided Tuning (CAT) control strategies,
4.3.1 System Description
The closed-loop position control of the system is carried out
67
digitally using a microprocessor-based system. The system control algorithm
(Chapter 6) is implemented in software, while specialised hardware circuits
are used for plant and terminal interfacing.
Figure 4.8 gives block diagram or the system. Here the general purpose
microcomputer board is interfaced to a VDU for HMI operation to the inverter
via an interface board; actuator position sensor interfacing is made via an
analogue input section. The interface board provides all the necessary
signals required by the PWM controller chip, whilst the analogue input
section performs filtering and digitisation or the position feedback signal.
This signal is transferred to the microcomputer board where it is compared
with the required (demanded) position; any error is processed in accordance
with the preset digital control algorithm; finally the processor outputs
command signals to drive the actuator via the interface board until actual
and demanded positions are equal. The analogue commands, when used, are
generated by the microcomputer board via the analogue output section. HMI
interfacing to the microcomputer board is performed via the communication
section which transmits and receives data from both the VDU and the
microcomputer board.
4.3.2 Microcomputer Board Design and Operation
(a) The Microcomputer Section
The general purpose microcomputer section .hardware circuit diagram is
shown in Figure 4.9, based on a 3MHz 8085 41
microprocessor. The program
instructions are held in .a 16K byte Eraseable-Programable-Read-Only-42
Memory (EPROM) type 27128, which also stores preset data such as look-up
tables • Since the EPROM requires separate address and data buses, an 8-
. bit register 74LS373 is employed to demultiplex ADO-AD7 lines into
68
separate address and data, AO-A7 and DO-D7 respectively, The Address-
Latch-Enable (ALE) signal of the 8085 selects the 74LS373'a output port
and remains there through the whole Central-Processing-Unit (CPU) machine
cycle, ~
An Intel 8155 Programable-Counter and Interface PCI chip provides
256-byte of Random-Access-Memory (RAM), three programmable Input/Output
(I/0) porta and a single programmable timer, This timer generates a 44
square wave signal needed by the 8251 Universal-Synchronous/Asynchronous-
Receiver-Transmitter (USART) and single pulses, which serves to interrupt
the microprocessor on RST 7,5 pin. The I/0 ports A,B and C provides
twenty two I/0 linea grouped into two separate 8-bit ports (Port A and
Port B) programmed either as input or output ports, whilst the third port
(Port C), which is 6-bit, programmed as an output port,
Additional RAM is fitted to the processor by using 8K-byte static 45
RAM (TC5565); this is employed for stack operations as well as data
extension and look-up tables.
All devices are memory mapped, address decoding being performed
in hardware.
Figure 4.9 shows the five most significant address lines (A11-
A15) of the 8085 which are employed to address other peripherals via 3~
to-8 decoder chip (74LS138) and 2-to-4 decoder chip (74LS155).
The microcomputer section is interfaced with the four other
sections via data bus, address bus, and ports A, B and C of the PCI.
When digitised data is to be· read from the analogue input section, the
PCI is selected, ports A and B are programmed as inputs, whilst port C is
programmed as an output port. When data is sent to the interface board
(command signals to control the inverter), the PCI is once more selected,
69
ports A and C being programmed as outputs.
Pull-up resistors of 4.7K each.are connected to the microprocessor's
address, data, and RD and WR lines.
(b) Analogue Input Section
The function of this section is to provide signal processing,
analogue to digital conversion of input analogue signals, supply of
reference voltages required by the microcomputer board, and loop-round
coupling of analogue output section back to the microcomputer section.
It consists of (Figure 4.10); 48
(1) Analogue-to-Digital-Converter (ADC) type 4145 Teledyne-Philbrick to
convert analogue signal to 12-Bit binary applied to the microcomputer
section. 47
(2) 8-channel multiplexer type H1-508A to allow multiple analogue signals to
be coupled to the ADC (selected sequentially).
(3) Appropriate reference voltages, which supplies d.c. reference voltages
required by some peripherals.
(4) Two analogue circuits, each consisting of two differential amplifiers and
a Low-Pass-Filter.
The analogue circuits are connected to channels one and two of
the multiplexer, channel one being the feedback signal from the
actuators's position sensor. Channel selection is made by the
microprocessor via port C of the PCI; 'this routes the appropriate
analogue signal· to the output of the multiplexer. Channel three is
connected to a 10V reference voltage supply, channel four being
connected to ground. Both channels are employed for calibration of the
ADC. Channels five and six are connected to the outputs of the Digital-
to-Analogue-Converter (DAC) of the analogue output section, being used
I . I
70
when DAC auto-calibration is invoked using a wrap-round test. A
detailed explanation can be found in Section 7.4. To convert the
analogue signal the appropriate signal is first selected by the
multiplexer and the ADC is given a command signal to start conversion.
This procedure is accomplished by the microprocessor via Port C of the
PCI. At the end of conversion two signals are generated, one coupled to
interrupt RST 6.5 of the 8085, the other being connected to the MSB of
port C(8155). In this design interrupt action is not used; instead the
status bit (MSB) is checked (polled) for an indication of the end of
conversion state. Once a valid conversion is seen the processor reads
in the digital value from the ADC via ports A and B of the 8155.
A variety of reference voltages are needed in the analogue
circuits, as follows:
(a) +10V. - Reference for autocalibration features.
(b) +5V. - Reference for the ADC.
(d) -5v. - Supply for the ADC.
(c) 0.7V. - Offset for the DACs.
The primary reference voltage is generated from a precision
regulator chip which provides a stable 10 volt signal; this is divided to
produce the 5 volts supply, the actual signal to the system being
obtained from a voltage follower through an inverting amplifier. By
feeding the +5V reference through a unity gain inverting amplifier the
-5V signal is produced. The offset reference voltages are acquired from
these +5 volts references via a resistor network as shown in Figure 4.10.
(c) The Analogue Output Section
This section is employed for monitoring of the internal software and
for recording purposes.
71
Figure 4.11 shows the circuit diagram of this section which comprises
of two DACs and analogue circuitry to buffer the output of the DACs 48
(AD7542). The buffered outputs are connected to the external connector
of the microcomputer board and also to channels five and six of the
multiplexer of the ·analogue input section. Offsets are deliberately
introduced into the buffer circuits so that software correction/
calibration techniques can be .implemented. Using this technique a
precise analogue output signal is generated, where the automatic
calibration compensates for drift in the analogue circuits with time and
temperature.
The 7542 precision 12-Bit multiplying DAC, has a simple, direct
interface to 8-Bit microprocessors. A clear input is connected to RESET
out of the 8085, which resets the DAC output to all zeros when powering
up the device. Loading the DAC is performed a nibble at a time into
input registers called low, mid and high. Each nibble is loaded into
the DAC as a normal write operation; when all three have been loaded the
DAC output is updated by writing a command to a fourth register.
(d) The Communication Section
Communications between the VDU and the microcomputer board is
achieved through the use of an asynchronous serial digital data-link.
This link partially conforms to Electronic 'Industries Association
(EIA)RS-232C standard.
Figure 4.12 shows the circuit diagram of the serial communication
subsystem which consists of an Intel 8251 USART and line
driving/receiving components. The 8251 converts parallel system data
from the microprocessor data-bus into serial format for transmission in
an asynchronous mode, and converts incoming serial data from a VDU
72
terminal into parallel system data for collection by the processor. On
transmission· it adds start and stop bits and, if requird, a parity bit,
to the data byte. On reception it checks for message errors and removes
the appended bits. Transmitted data is converted from TTL level into
line levels by the line circuit, whilst the received data from the VDU is
converted to TTL levels.
Programming the 8251 is accomplished throughout a set of control
words which must be sent by the microprocessor to initialize the 8251 to
support the desired communication format. Selecting the 8251 followed
by a command word to reset the chip and then a control word which
programs the: BAUD . RATE, CHARACTER LENGTH, NUMBER OF STOP BITS,
SYNCHRONOUS AND ASYNCHRONOUS OPERATON, EVEN/ODD/OFF PARITY, etc. In
this design transfer of data to and from the USART is carried out in a
controlled fashion using polling of its status register. Information
concerning the state of the receiver and transmitter registers is held in
the status register; this enables the microprocessor to monitor serial
line signals.
Interface Board Design and Operation
It has been explained earlier in this chapter that the function of
this board is to provide all necessary inverter control signals under
microprocessor control. Figure 4.13 shows the block diagram of this board,
where data and address signals are input to the board from ports A and C
(respectively) of the 8155 as well as signal from the ON/OFF circuit. A 10 49
MHz local oscillator feeds the Intel 8254A Programmable-Interval-Timer (PIT~
which incorporates three independent 16-Bit Programmable counters (Figure
4.14). Two are employed to generate clock frequencies FCT and VCT and the
73
remaining one used as the primary signal Cor OCT and RCT clocks. These
clocks are generated by down counters, stepping down the main local rrequency
using two 4-Bit binary counter chips.
The clock timers are initialised by selecting the PIT and programming
it into the desired working mode, then loading the data to generate the
required frequency. Any changes in clock frequencies can be implemented by
sending the appropriate data words to the PIT.
A latch circuit consisting or two D-type Flip-Flop chips (74LS74)
hold signals feeding the current limiter and the inverter circuits. The
peripheral and the latch circuits are mapped into the sortware bus address
structure using local decoders.
The latch circuit input, connected to the data-bus (DO-D3), controls
the inverter 'on' and 1ofC 1 switching action and also selects the direction
of the motor.
Note that a hardware power-on reset is incorporated in this circuit.
When power is switched on to the board, this circuit resets the PWM
controller, 'tripping' the latch circuit, thus clearing its outputs. As a
further precaution data is written to switch 'off' the inverter via the
ON/OFF circuit under software control as shown in the timing diagram (Figure
4.15). In normal circumstances the inverter is switched • • on and • off under
processor control. However iC an inverter overcurrent condition is signalled , ,
the latch changes state, switches ofr the inverter, and locks itself into
this state. It can be reset either by giving a software generated command
from the processor or manually using the analogue controller ON/OFF circuit.
The input and output lines of the interface board are bufCered using
octal-bus transceiver (74LS245), and octal 3-state driver (74LS244)
respectively; all lines are pulled up to 5V. using 4.7 K resistors.
·-·-·- ·-·-·-·-·-·-·-·-·-, Start ...r. !
·- ON/OFF I i CuiTent
Stop ....n.. Circuit I Detector i ! I L-.-·-·-·-·-· -·-·-·-·-·-·-· -·--·-·~ l I ri' +
------------'I l1
i :a ' I I I-I
Set spee
* control
Speed Controller
Unit Acc/Oec Circuit
------, I
softstart 1 I FCT stop circuit; =±= LL.. I RCT
! OCT I Jl I ; VCT I I I
direction t, Absolute Value VCO 2- Control i i d!!t~~or I Unit logic Unit j(/(\o/ CtrC I
-f I I I . ' ! I I I An 0 e c o \er i -- - - ---- .. -- --- -- - -- - -.I
I
1 L a l gu ontr I . i...-·-·-·-·-·-·-·-·-·-·-·-·-·-. -·-·- ·- ·-·-·-. -·-·-. -·-·-·__J
Fig. (4,1) Open Loop System (Analogue Controller)
240V "V
I I I ......
t I
Inverter I Actuator Set
--------------------------------------;- -- - - ---- - ----- - --- --- -,------------ ..,
r------------, • • : I Decel.
1 I sett in I I VR2
1K I I
+15V
1 +15V I I 470R~
I I 1-~-1 I I
Acceleration I Deceleration Circuit
: 1 - t.7nF t.'/nF
-15V
(at( 470R Acce I. setting VR3
VZ1 L ~ .,_._.,_ ""';_:::--":: : : '= ·------ .:: :.--- ""-:.-:.-:..,._-___ _,_ _______ _,.. ~tF----:1
<7 'I C"' \'--- ~1-....!'r--=-----------· 22 K i CJ- ! Cx : VI 1 To Absolute Value Unit
i rr""- -- --- - - - - - - - - - - -·-, V22
L VN
Speed setting
>---1=]-...,.C~o:- To pin C/CW of PWM
I
I
I
'---' point
1K
Soft Start/Stop
Circuit 100K Direction Detector
Circuit
Q/1
.~.... --- ----- -- - - -15V I L-------------------------------------~' L-- ----------- -- - - -- - --- -- ---- --- - -- -- - - - --- - .- - - -- - J
. .
All diodes type OA91 AU op -amps type 741
Fig, (4.2) Speed Control Unit and Direction Detector Circuit
I
I VB1
I
I I
- I - _J
controller
-- --------------------10K
RI Vz3 Vz4
10K 3V6
01 R4 R'2 K 2K2
RS R3
Vo
IC 6 !( 7
From Soft Start/Stop ~:r,.
circuit
------------------------
Fig. { 4. 3 ) Absolute Value Unit
vco 4f----MC14046
680pf
To FCT of
PWM controller
77
VZ3
1
Fig. (4.4) Performance of The Absolute Value Unit
ov.
Fig. (4.5) VCO and Control Logic Unit
Motor fine current
Absolute Vai.Je Unit 0/P
78
I ------- -- "I Clock Generator
I • 5
I MC 14047 B .. OCT
I ' 600KHz 3K3 +SV ~
I 11
I From vco ·Absolute Value ' .. FCT
MC 1401.6 B Unit • I 7
680pF .. -------- -- --
Fig. (4.6) vco and-Control Logic unit
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•
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80
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86
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Fig. (4.15) ON/OFF Circuit Signals Operation
CHAPTER 5
87
CHAPTER 5
5 CONTROL SYSTEMS
5.1 Open and Closed Loop Control
The type of plant considered here operates in a continuous
mode,having inputs, outputs and disturbances which are continuous in real
time. Therefore systems which exhibit discrete states, such as conveyer
belt transportation. methods, are excluded from evaluation and analysis in
this work.
Continuous systems are dynamic ones and may be modelled in open-loop
form as shown in Figure 5.1a. Provided all plant states can be determined
and that disturbances are also deterministic then it may be possible to
manipulate the input states in order to attain desired output conditions.
As such no attention is paid to the current output of the plant.
open
fails
Wherever possible it is preferrable to operate control systems in
loop mode, Unfortunately the output performance so attained often
to meet system requirements, especially where the criteria are
demanding, In such situations closed-loop control must be
illustrated in Figure 5.1b,
used, as
This type detects the current state of the output, and generates an
error proportional to the difference between the input and output. Ideally
closed-loop control system drives the output until it equals the input,
reducing the error to zero, Any differences between the actual and desired
output will be automatically corrected, thus compensating for the effect of
disturbances on the system,
5.2 Performance Criteria
5.2.1 Introduction
88
The purpose of a closed-loop control system is to minimise the error
between the system output c(t) and the input signal in the presence of
disturbanoes(Figure 5.2). In fact the most desirable response is. one in
which the outp~t is identical to the input at all times; unfortunately
because of the nature of dynamic systems, it is not possible to achieve this
in practice, The actual performance of closed-loop control systems is
generally a function of stability, sensitivity, measurement accuracy, system
dynamics and disturbances, Performance criteria are generally defined in
the time domain, relating to steady state and transient conditions, these
points being discussed further in section 5.2.4. such criteria are usually
specific to application, certain characteristics being more important in some
systems than in others.
5.2.2 Stability
A closed-loop control system must be stable under all operational
conditions; these include varying command signals, disturbance anywhere
within the loop, power supply variations,
parameters.
and changes of the ~oop
In general the control engineer needs not only to stablise the system
but must also establish the .degree ·of stability of the closed-loop.
Referring to Figure 5.1b, the transfer function of the closed-loop system
is:
G(s) C(s) = __ _:___ ( 5.1 )
89
If G(S) H(S) assumes a value or -1 at any frequency (i.e. unity gain
at a phase lag or 180 degrees), then the denominator equals zero and the
feedback system oscillates. The margin by which G(s) H(s) is short or unity
magnitude at -180 degrees or phase, is defined as the "gain margin". In a
stable system, -two conditions may occur:
(a) Gain greater than unity,· phase never achieves -180 degrees.
(b) Gain falls below unity before the phase has attained a lag or 180
degrees.
Condition (b) is illustrated in Figure 5.3. The-margin by which it
is short or -180 degrees at unity gain is the "phase margin" (Figure 5.3).
From these values the closed loop dynamic performance can be deduced.
5.2.3 Sensitivity
The closed-loop system should be insensitive to changes in system
parameters: as plants age, their dynamic behaviour changes, that is, G(s) or
H(s) change. Thus a certain degree of insensitivity to these changes is
essential to the control system.
The sensitivity or a system's transmittance Trn with respect to the
characteristics or a given element K1 is defined as
= (5. 2)
To illustrate the concept or sensitivity, consider the typical
control system shown in Figure 5.4 in which K1 represents the input
scaling/shaping circuits, etc., K2 represents the transfer function or the
feedback transducer, and G represents the transfer function or the open-loop
system.
90
From the equations derived in Appendix A.4, it illustrate that K1 and
K2 are highly critical and therefore they must possess precise and stable
characteristic with time and temperature.
5.2.4 51 System Performance
5.2.4.1 Introduction
Dynamic system testing is normally carried out by subjecting the
system to a variety input of test signals and noting the corresponding output
response. As a result, an assessment can be made whether or not the system
behaviour is satisfactory; if not the controller parameters are modified to
improve the response.
In general the basic input test functions used are those which can be
easily interpreted and analysed mathematically. These input functions may
represent a severe form of disturbance; for instance the most common signal
used for transient response studies is the step function. · This·function
(Figure 5.5a) is very widely used in practice and is simple to handle
mathematically. Another function which is more relevant for some practical
physical systems, such as those possessing high inertia input
characteristics, is the ramp function (Figure 5.5.b). This would be
applicable when step function testing leads to non-linear behaviour or where
the normal input function to the system is velocity rather than a position
demand. A parabolic input function i.e. an acceleration · signal (Figure
5.5.c), is typically used in weapon servo tracker systems.
One other type of input function, the unit impulse function, is of
considerable analytical importance. This is defined to be a function whose
area is unity and pulse duration tends to zero (Figure 5.5.d). However,
impulse response can be obtained indirectly using random input and
91
correlation techniques. Other forms of input function are sinusoidal
52 signals, and statistical signals such as white noise.
The first three input functions mentioned above oan be implemented in
practice to check how the system actually responds to the input signal, while
the fourth function (unit impulse) is unlikely to be used as it generally
takes practical real systems into nonlinear modes of operation.
The signal considered in this section are the step input and the
sinuso~dal (f~equenoy response) function.
5.2.4.2. Step Input Function
A typical set of the responses are shown in Figure 5.6, this being a
form of behaviour widely met in servo systems when subjected to a step
input. . Restricting ourselves to a predominant second-order system the
response shown in Figure 5.7 oan be considered is two parts:
(a) . Dynamic Performance
(b) Statio Performance
(a) Dynamic Performance: The major factors evaluated in dynamic testing are:
•overshoot: This is the maximum difference between the transient and
steady-state solution for a step function, and it is usually expressed a
a percentage of the step size.
*Delay Time Td: It is defined as the time required for the response to
reach 50% of its final value.
*Rise Time Tr: This is usualy defined as the time taken to rise from
10~ to 90% of its final value.
•settling Time Ts: This is the time required for the response to· reach
and remain within a certain percentage limit of its final value.
92
b) Static Performance: When the system response to a step input reaches the
steady state, i,e. after all transients have died out, the static
performance is defined in terms of the steady-state error.
5.2.4.3 Freguency Response Function
This f~nction, which represents the response of the system in the
frequency domain, is of major importance as it is easy to apply, where
graphical methods can be used to determine stability, and it offers a good
basis for synthesizing systems. Furthermore it indicates clearly the type
of change required to modify the dynamic behaviour of 53
the system. The
response of a linear system to an input sine wave is sinusoidal the same
frequency but generally with a shift of time and change in amplitude, The
ratio of the output to input is defined as the transfer function, its
variation with frequency being defined as the system frequency response. In
practice the frequency domain response (gain and phase), is evaluated by
applying a sine wave· test signal to the input and measuring the output steady
state response (i,e, after all transients have died out).
Ari ideal system has constant gain and no phase shift over the
complete operating frequency range. Such an ideal characteristic cannot be
achieved practically. Figure 5.8 shows a normalized transfer function of a
predominant second-order system. It shows gain variation in-band with only
a gradual fall off at higher frequencies with no sharp ______ ,
.~frequency response performance criteria of a system
following parameters:
cut-off. Hence J_cc:..C-.l\?.ect
is decribed by --the
the
(a) Bandwidth BW: This is defined as the frequency between D,C, and the
point at which the gain has fallen by 3dB, i,e, below 0.707 of unity
gain; all frequency components of interest normally lie within the
bandwidth.
(b) Peak Magnification Mp: This defines the height of the response peak,
93
which should be in the range 1.1 to 1.5 of the D.C. level for good
54 transient behaviour.
(c) Wp: The frequency at which the peak magnification occurs.
(d) Cut-off Rate: The rate at which the·magnification curve falls beyond the
peak, normally specified as dB/Decade,
Digital Control
Why Digital Control
Virtually all servo control functions can be implemented using
analogue (continuous) methods. Such techniques are straightforward where
the plant to be controlled is. relatively simple: however where non-
linearities are inherent in the response, where mathematical calculations
have to be performed, or where distinctly different operating modes have to
be catered for the analogue system becomes quite complex. Not only may the
cost become prohibitive but in some instances it may be impossible to achieve
the desired control performance, In these circumstances digital methods are
an attractive alternative but, until the last decade, digital controllers
have been much too costly, large or unreliable,
This has all changed with the advent of the microprocessor. Digital
control in continuous systems can be implemented using relatively low cost
single-board computers, this being on a par with their analogue counterparts.
Software costs have to be considered but these, in standard units, are a
relatively small portion of the total expense, Hence, for even the simplest
loop control applications digital control hardware is competitive with
analogue unit, Figure 5.9.a,b show an example of continuous and digitally
controlled system respectively.
94
5.3.2 Discretization
There are many methods of discretization of analog transfer functions.
The most used methods are the following:
~
a) Impulse invariant transformation (z-transform).
b) Impulse invariant transformation and artifical hold.
c) Mapping of differentials.
d) Bilinear transformation.
e) Bilinear transformation and frequency prewarping.
f) Matched z-transform.
55 An assesment of the above methods has been done, comparing the performance
of a discretized controller with that of analog design; this showed that for
general use the best discretization method is the bilinear transformation. In
particular, this method performed well even 1for slow sampling rates.
A major decision in using a digital controller is to choose the sampling
rate. Ultra fast sampling does not produce good closed loop performance as
increasing the sampling rate (T ~ 0), the discrete processing will not
asymptotically converge to an analog output, because this requires an infinitely
long word length. This puts a definite· upper bound on sample rates. On the
other hand the sampling theorem as developed states that a sampled continuous
signal may be reconstructed from its samples if, and only if, the frequency
contents of the signal is lower than ws/2. However digital control system with
56 such slow sampling rates give totally unacceptable responses.
Although some work has been done on the selection of sampling rates ·in
control 57
systems, generally it is still a matter of engineering judgement, a
typical figure being that of ten times the closed loop bandwidth.
95
5.4 PID Controller
The most widely used control algorithm in industrial process and
servo control is' the proportional plus integral plus derivative (PID)
controller. Although the PID control algorithm is easily implemented using
microcomputers, the control coefficients must be carefully selected to ensure
that the operating system is stable.
Figure 5.10 shows the block diagram of an analog PID controller
acting on an error signal e(t) to give an output u(t). The transfer fUnction
of this controller can be written as
G(s) - IJ:sJ- K Ki + sKd - E(s)- P + s (5.3)
and the corresponding time-domain relation is given in the form,
I
u(t) = Kp e(t) + Kd :~!tl + K;f(t)dt (5.4) 0
where u(t) is the actuating control signal at the PID controller output and,
e(t) is the error signal. The proportional control simply multiplies the
. error signal by a constant Kp, the integral control multiplies the integral
of e(t) by K; , and the derivative control generates a signal which is
proportional to the time defivative of the error signal. The main task in
the design of the controller is to select the value of Kp, K; and Kd to meet
the required performance criteria.
The simplest form of control, a signf~ term controller, is one in which
96
the error signal e(t) is multiplied by a constant K1 to produce the input
control signal to the process as shown in Figure 5.11. This arrangement is
called a proportional controller. Figure 5.12 shows responses of a
predominantly second order system, where for a low value of K1 the response
is over-damped. By increasing K1, the response of the system becomes very
rapid and underdamped; ultimately if K1 is large enough instability is
likely to result (Figure 5.12). However, low gain systems exhibit sizeable
steady-state errors as shown in response 1 in Figure 5.13. Thee fore
integral control is introduced to minimise this steady-state error while
still using a low value of Kp. Varying the gains of Kp and G varies the
degrees of overshoot and rise time response of the system as illustrated by
responses 2, 3 and 4 in Figure 5.13. To reduce the overshoot anticipatory
action can be used, i.e., a derivative control which provides a correcting
effort proportional to the slope of the time variation of the error e(t)
(response 5 of Figure 5.1~
The integral term in equation 5.4 can be calculated by using the
' trapozoidal rule approximation giving
k:n
= ! ~ek-1 + ek l • I 5. 51 k:t
and approximate the derivative with the following difference equation:
~~ dt t:nT
1 --T (5.6)
substituting equations 5.5 and 5.6 into equation 5.4 gives the form of the
digital PID control as
u n
97
(e ··n -e ll n- (5. 7)
and the algorithm for previous step in time is written with the approximate
shift as
u n-1 = Kp e +KiT
n-1 --2
K=n-1
l: K=l
_ subtracting.equation 5.8 from equation 5.7 yield
U =U 1+e (Kp+KiT Kd) n n- n -- +-
K.T +e 1( l. -n- --
Kd Kp -2Kd)+en_2 T
T 2 T . 2
which is the direct digital control algorithm.
Equation 5.9 may be written in. the form
U = Un-l + A en + B e 1 + c e n n- · n-2
where
KiT 2Kd B=---Kp
2 T
Kd c =-T
. (5.8)
(5. 9)
(5.10)
(5.11)
Using microcomputer techniques the digital PID controller given by equation
5.10 can be easily implemented in software.
R(s)
98
G(sl= C(sJ R(s)
(a) Open loop System
E(s) G(s)= ((s) E(sJ
H
(h) Closed loop System
C(sJ
C(s)
Fig. (5.1) Continuous System Block Diagram
Set point
measured value
'
-·-·-·---·-·-i g,_(f..;_J -.-,
:e(tJ K K e(tl 0 (t):;atl 1 Ke(tl
--------- ·- --Het
H
y(t)
Fig. (5.2) Continuous Closed Loop Controlled System
Gain dB
99
0 dB 1--------------~:----....-- W lradlsec.) ! Gain Margin
I
I I
I I I I
0 I . Phase angle - 90
I
-180
-270
Fig •. (5. 3) Phase and Gain Margin Relationship
Rlsl E!sl G(sl C(s)
. ~C!sl
Fig. (5.4) Sensitivity Gains of Closed Loop System
100
Ampl. Ampl.
Amp!.
Input Input r-------~----~
~----------------t t (a) (b)
(cl
Ampl Impulse
Input f--'
P_!llse 1-t--"1
~--~-----------t (d)
F. (5 5) Typical Test Signals l.g. •
Fig. (5.6) Typical System Response-Step Input
----------------------------------------------------------------------------------------
t37
Ql Ill c 0 a. Ill Ql
a:: .9 .._ :J a. .._ :J
0 .63
.5
.1
------
Overshoot
----------
I I
------ _j ___ / I
•/ I
l
/
/_ ' ExpQ'lential Envelope
Dynamic Response
Static .Response !---1
~~*-~_. _______________________ ~--~-------t 1-r;d-1 T Ts
Fig.(5.7) Step REsponse- Second Order System
... 0 ...
102
Gain
Mp I
M - -•----M I 13d B 72------------------~-----:-·
I
I
0
Phase increasing
I
I
I I
BW w
Fig. (5.8) System Transfer Function - Second Order
103
Diff. amplifier Power illlplifier
(a) Analogue Control
Power ~plifier
D/A
; Clock ·----------• • ; . ,..._ _ _._, Digital A/ D
controlter or
computer
VDU or Tape
(b) Digital Control
Motor
Selected position
Fig. (5.9) Closed Loop Controlled System
Position 0/P
104
I
Kp
e( t J • u( tl -• lL [ E(sJ s. • UCsl •
sKd
Fig. (5.10) Analog PID .controller Block Diagram
r(t) 10\ e(t) K1
K1eCtJ Process Sensor c(tJ
~
Fig. (5.11) Proportional Controller in Closed Loop System
~-------------------------t Fig. (5.12) System Performance at variable Controller Gains
Fig. (5.13)
105
Big Kp,Ki 3
..__-;-----1 Uncompensa. ted
system .
L-----------------------t
System Performance to PID Technique
CHAPTER 6
106
CHAPTER 6
6 EXPERIMENTAL STUDIES
6.1 Introduction
Control systems may be classified in general as linear or non-linear
(Bang-Bang), Normally the loop controller (Figure 6,1) is connected in
cascade with the forward portion of th·e loop and is used to compensate the
system performance in terms of stability, steady state holding, and transient
(dynamic) performance. Typically phase-lag, phase-lead, lag-lead and PID
techniques are used as compensation method.
This chapter describes the practical method for obtaining the
transfer function of the plant (Inverter-Motor/Actuator) and shows how this
information is used to deduce the compensation (control) techniques needed
for satisfactory closed loop performance. These are implemented ·digital
PID controller, the control algorithm being executed by software employing
the digital procedure described in section 4.3. The final operational
control algorithm is installed using computer aided tuning techniques which
enable the operator to meet the required static and dynamic performance
criteria of the electric actuator system, In order to generate the set of
tuning rules for the controller a digital simulation for the system was
carried out; this is described in Appendix (C).
6.2 Analogue Control System Performance
6.2. l Open Loop Performance
The analogue controller, described in section 4,2 was used to drive
the plant in order to derive its open loop transfer function (Figure 6.2).
Here a sinewave signal is applied to the analogue controller while the plant
output response is taken from the position sensor ( potentiometer) coupled to
107
the actuator's shaft. For these tests, restrictions were imposed on both
test signal amplitude and frequency in order to ensure linearity of
operation. The minimum frequency was restricted to 0.04 Hz, set by the
stroking length of the actuator, whilst the maximum value was limited by the
current detector circuit (approximately 1.3 Hz). · The signal amplitude was
restricted to t2.5 volts to avoid velocity saturation of the motor.
Figure 6.2 shows the system configuration for the open loop transfer
function test of the system. Here a transfer function analyser (TFA) is
used to produce the frequency response plots (gain and phase) of the plant;
the effect of the analogue controller is negligible. It is fed by two
signals, one, from the signal generator, is the input to the system whilst
the other is obtained from the feedback sensor. Correlation calculations of
these two signals give the gain and phase responses of the plant. Figures
6.3, 6.4 and 6.5 are t~pical of the time response measurements of input
signal, motor speed and shaft position. It can be seen that as .the input
frequency is increased the stroke of the shaft reduces, but its phase
relationship (relative to the input signal) remains constant at -90 degrees.
These tests show that the system behaves essentially as an integrator with a
gain characteristic of -20 dB/decade and a constant phase lag of 90 degrees
(Figure 6.6) although an extra lag component is beginning to show at the
higher frequency levels. From this test it is still ,not clear how the
system behaves at lower frequencies although this can be deduced from the
information available concerning the system. The input signal must be
reduced to a low value to test the system at low frequencies in order to
limit the actual stroking length of the actuator during the test. However it
is not recommended to do this because the signal to noise ratio will be low.
Hence a closed loop test is carried out to obtain full frequency response
108
data.
A series of transient response tests were carried out to complement
the frequency response analysis. The results obtained, Figure 6.7, show
that while the motor runs at constant speed, the shaft position change has a
ramp characteristic, i.e. the actuator behaves as an integrator.
6.2.2 60
Closed Loop Performance
The closed loop test for the system was carried out by inserting a
unity gain error amplifier (Figure 6.8) circuit between the feedback sensor
and the analogue controller as shown in Figure 6.9 and injecting a fixed
amplitude variable frequency sine wave test signal. With the TFA connected
as shown, the input and output signals of the system are correlated to give
the closed loop gain and phase response (Figure 6.10). The input signal was
restricted to t5 volts to ensure linearity of operation. Testing was
carried out in two stages; the first test covers the upper band of
frequencies (0.05- 1.8 Hz, Figure 6.10) arid the second starts at 0.02 Hz and
finishes at 0.1 Hz (Figure 6.11). In practice it was difficult to perform
frequency response testing below 0.0~ Hz; however de testing established that
the system had a closed loop gain of one (i.e. zero dB) at low frequencies.
Hence it is clear that the closed loop bandwidth of the system (-3. dB gain)
is 0.0355 Hz. According to the results obtained, the mathematical model for
the open loop transfer function is
G(s) = 1 sT
where ~ is the time constant of the system.
(6.1)
109
The closed loop transfer function for a unity feedback gain is
G(s) = 1 (6.2) 1 •ST
This is first order lag system having unity gain at de and a characteristic
of -20dB/decade at frequencies higher than the -3dB cut-off frequency. The
phase lag of the system increases with the increase of the test signal. Note
the actual values of the phase shown in Figures 6.10, 6.11 must be modified;
180 degrees must be subtracted from the recordings to obtain the true phase
lag.
Typical results obtained during closed loop frequency response
testing are shown in Figure 6.12, 6.13 and 6.14 comprising input signal
(upper trace), motor speed (medium trace) and shaft position (lower trace)
for different test frequencies.
Preliminary studies of the dynamic behaviour of the system were
carried out using step and ramp inputs. Typical results obtained are shown
in Figures 6.15 to 6.18. Figure 6.15 shows the behaviour of the system for
step input command with the system controller set for unity gain. This
response shows that the system time constant is approximately 5 sec., whilst
that calculated from the frequency response tests is 4.48 sec.
Theoretically in a closed loop linear system there should be no
steady state error if an integrator is present in the loop. In practice
non-linear effects must be considered, in this case the main problem being
that of stiction in the mechanical coupling. Figure 6.15 shows the system
response having about 5% steady state error, reduced to 2% when the
controller gain is doubled (Figure 6.16). Techniques for eliminating this
using a digital control algorithm are described in section 6.3.
110
The second input function employed for testing the system is the
ramp input. Figure 6.17 shows the system behaviour to a ramp input, where
the output of the system (position) follows the input ramp with a constant
steady state error. This error is inversely proportional to the gain of the
system (Figure 6.18).
A photograph of the experimental set-up of the analogue controller
and the inverter is shown in Figure.6.19.
6.3 Digital Control System Performance
6.3.1 Introduction
The digital control system test arrangement consists of (Figure
6.20)
* Digital controller Unit (See Section 4.3)
* Inverter controller (Section 3.3.3).
* Actuator and position sensor (Section 1.4).
* Visual Display Unit (VDU).
A photograph of the digital controller is shown in Figure 6.21.
This differs from the analogue controller in two major ways; firstly
the use of digital software techniques for control, secondly the inclusion of
a VDU to facilitat.e man-machine interfacing.
In this design a discrete 3-term (PID) control algorithm is
implemented in software on an 8 bit microprocessor. The software is written
mainly in CORAL66 but assembly language is used for certain processor
specific functions, including interrupts.
The VDU provides a powerful method of interfacing with the system,
enabling the operator to
* Input the system setpoint.
111
I Input the sampling frequency.
I Debug the software program.
I Generally supervise system operation.
I Mo~ify parameters and data structures of the control algorithms.
6.3.2 The Digital PID Controller
The general form of a 3-term PID controller used in continuous data
controlled systems is described in Section 5.4. Noteng that however, by
setting various coefficients to zero a one or two term, or a 'floating'
controller may be implemented. Figure 6.22 shows the block.diagram of the
digital PID controller used here, where the control formula of the
controller is: (see equation 5.,0) '
(6.4)
This can be written in the form:
u(nT)=U((n-1lT)+A e(nT) +8 e((n-1)T)+(e((n-2)T) (6.5)
The control variable U(nT) in equation 6.5 depends upon the present value of
the error signal e(nT), the previous values of the control variable at time
(n-l)T and previous error values at times (n-l)T and.(n-2)T.
The digital controller,of Figure 6.23, acts in the following way:
When a set point is introduced through the VDU, the controller reads the
actual position of the actuator, compares them, and calculates the resulting
error. The software control algorithm calculates the appropriate control
output which sets the speed of the motor via the interface board and the
112
inverter. This drives the shaft in a direction to reduce the error, and at
a speed which is proportional to this error. A sampling rate of 20mSec is
used to accomodate high gain (and thus wide bandwidth) operation. This time
of 20mSec is just in excess of that required for the software calculations
(using floating point operation) and the ADC conversion time.
Practical Results
The complete closed loop system was subjected to a series of time
response tests using a step and ramp input.
Figures 6.24 and 6.25.
Typical results are shown in
Only a two-term (PID) controller was employed in the test as
simulation results, later confirmed by preliminary practical tests, showed
that the derivative action could be omitted from the control algorithm.
Figure 6.26 shows the step response of the system using only a unity gain
proportional controller, the integral term being set to zero. The response
shows a very small steady state error; this can be reduced by increasing the
gain. The stiction effect, which causes this kind of error, can be
minimised ·by boosting the voltage applied to the motor. Boosting, which is
implemented by software only at low error conditions, has the effect of
raising the motor torque and thus compensating for the stiction load. The
effect of boosting is exhibited in the step response of Figure 6.27. The
motor speed response for a step input is shown in Figure 6.28; note that the
speed rises very rapidly to its maximum value at the instant following the
step input in a ·very short time, then decreases exponentially with the
correction of the error value. When the actuator reaches its demanded
position, the drive supply is reduced to zero and the motor is effectively
switched off. However, if external positional disturbance occur,correction
occurs instantly (Figure 6.29).
•
113
It has been mentioned earlier the digital controller contains
proportional + integral terms. Figure 6.30 shows the step response of
the system using different integral gains. Note that by increasing K1,
the overshoot increases, the number of oscillations also increase, but
the rise time decreases. When the proportional gain Kp is increased,
the rise time reduces as does the overshoot (Figure 6.31). In Figure
6.32, the step response or the system is shown when using a PI
controller; the upper trace is position, while the lower one being motor
speed. The effect of external disturbances on the system (speed and
position) is shown in Figure 6.33.
* The use or three-term controller PID (by adding derivative action to the
PI setting) produced only alittle change in the system performance.
Figure 6.34 shows three responses; one is for the PI controller, the
other being those for the PID unit. It is clearly seen that varying Kd
(0.01-0.3) has only relatively small effect on the response.
result derivative action was not used in the control loop.
6.4 Computer Aided Tuning
As a
When tuning up a plant using conventional methods the operator
initially sets the P,I,D terms to 'guessed' safe values which are usually
based on open-loop testing, mathematical analysis, or experience with similar
systems. The system is then activated in closed loop and subjected to
(usually) time domain testing. Its responses to these tests are observed
and if they fail to meet the desired system criteria, the tuning terms are
re-adjusted (Figure 6.35). This process continues in an interactive fashion
until the 'best' possible performance is achieved.
Such techniques are time consuming, its success depending to a great
114
extent upon the skill, experience and knowledge of the operator. The object
of the Computer Aided Tuning methods developed here is to minimise the skill
element and speed up the tuning process.
The basic concept behind this technique is described in section 6.3,
but the tuning technique is outline'd here for completeness.
Initially the system sets the control algorithm coefficients to
predetermined, safe, values which will also ensure system stability. The
operator then subjects the closed loop to a set of test signals, adjusting
the tuning until a satisfactory response is obtained. He is guided through
this phase by the "supervisor" within the controller, interacting with the
system via the VDU (Figure 6.36 ). Operator's tuning commands are expressed
in terms of system responses (e.g. overshoot, rise time). There is no need
to adjust the actual algorithm coefficients; these are handled by the
computer Aided Tuning (CAT) algorithm.
The turning system has to have an inbuilt set of rules so that it can
adjust the PID coefficients in the correct manner. These rules were
developed using the plant simulation described in Appendix c.
Using the transfer function test results obtained by the analogue
controller (Sections 6.2.1, 6.2.2) a mathematical model of the actuator was
developed.
A digital simulation of this model was developed and modified until
its performance was identical to that of the real actuator. Once this had
been achieved the simulation was used to establish the tuning rules for the
CAT system.
Typical results are given in Figs 6.37 to 6.39
(a) Figure 6.37 1, Initial responses (preset tuning)
2. Operator demands faster rise time with same amount
(b) Figure 6. 38
(c) Figure 6.39
115
of overshoot.
3. Operator demands same rise time but allows a small
increase in overshoot.
1. Response obtained using initial (preset) tuning.
2. Operator demands faster rise time, no constraint
on overshoot.
3. Operator relaxes overshoot restriction to that of
(1) but demands a rise time of (2).
1 •
2.
Response obtained using initial (preset) tuning.
Operator demands a much faster rise time with a
large reduction (decrease) in overshoot.
3. Operator demands much faster rise time but relaxes
overshoot requirement.
A third important factor is that of settling time, especially in
enables this to be taken into fast systems. The CAT algorithm used here
consideration in addition to the overshoot and rise time criteria.
Typical results for settling time tuning are given in Figures 6.40
and 6.41.
(a) Figure 6.41 1. Operator includes a settling time requirement into
Figure 6.42
the preset tuning (compare with response of Figure
6.39.
2 & 3. Operator demands progressively faster settling
times than ( 1 ) •
The long settling time shown in response (2) of
Figure 6.39, is reduced to that shown in Figure
6.41.
116
6.5 Plant Simulation
As described previously, a model of the actuator system (the 'plant')
was implemented on a Multics mainframe computer in order to derive the CAT
rules. This is described in detail+ in appendix c. A series of model and
plant response were carried out to validate the simulation goodness, typical
results being given in Figures 6.42 and 6.43.
Figure 6.42 shows step response test results for both the plant and
the model with unity gain settlings. It is clear from the figure that they
are in a good agreement, where the very small steady state error is due to
mechanical stiction. Figure 6.43 -shows a PI controller where the
proportional setting is unity gain and the integral gain value is 0.3. Once
more agreement between the plant and model is very good, the main difference
being in the overshoot amplitude.
117
R(s} E(s} U(s} Y!sl · + Controller System -
F(s)
~H(s}J
Fig. (6.1) Block Diagram of Closed Loop Controlled System
Signal eltl Analogue u!t} System y(t) Generator Controller
T.F.A. -
Fig. (6.2) Open Loop Test Configuration
118
Fig. (6.3) Open Loop Time Response Test (0.06 Hz)
•.• [\; hco: 'nl ·:A H :: {j ; : ' :f :oj.l~ i; [:/) ;j
I I ' . ·.·. - I .. ' . . . . . .,. .· . . . • .... I ' ., . I ~ ! '" : .,~; . "- I " ! V \) V . . • ·~· ~+~ L\l· \ • I
er-,- -·,·-,0~0-~~~·' \aL~T/r ,., ·,-·A ·'7:1~+~1 !}'!-~~0" ; I I r • .aq; 'I 1 'I 1 • 1 Velocity
1 V V v . H~. _._ vl1
/ v ' 0 ~ \J 1
. ,_ Ar, .3 ! j · ~ · . / ! Position
-ol.16 ,_ sec.
------------~__.,
·Fig. (6.4) Open Loop Time Response Test (0.1 Hz)
·--r • . - • 1
I
Fig. (6.5) Open Loop Time Response Test (0.4 Hz)
zsv
Signal
... ... CQ
. ---------- --·~------------------------------------,r-------
128.81118
lB. 8088 181.888 PHASE
8.08008 8111.881118 m "lJ
-lB. 8088 ------- 88.881118 w z GAIN (f) 1-1 <( <( -2111.0080 48.881118 I C) 0...
-30.0080 -------- -------~-- ---- 28.1!1888 I ... ..,
0
-48.0808 B.f1111188111
-28.-
-48.881118
-7111. 0080 -6111.1!1888
Ill ; Ill I I i Ill
I I Ill Ill !!! I I lil ...
Ill .. • Ill ul GS • • • • • .. ... Fig. (6.6) Open Loop Frequency Response Test - FREQ
Bode Dtagram
·1SV
1 21
Fig. (6. 7) Open Loop-Step Response Test
27K 10K
10K ((1
10K
10K
OFFSET CIRCUIT C OM PAR A TOR
Fig.(6.8) Error Amplifier for Closed Loop Test Circuit Diagram
Position
To Soft Start/Stop Cfrcui t I (1
Analo~ue En-or Amp ifier
r(t) , -· e(t) Signal '· ), Analogue , .. . + • ... I
Generator '"" ' ,1' •• I Controller ',- ., --. f (t)
" T.F.A.
Fig. (6.9) Cloosed Loop Test Confiqutation
u(t) System
h(t)
..... -
y(t)
r-'-
'-r
Senso r ... N N
------- ----------------------------------------------~-----------------
20.0000
10.0000 161!1. 1i'lS0
0.. 00000 128.1i'JS0 m PHASE lJ
-10.0000 90. B08I'J w -----------z (f) H <( <( -20.0000 40. B08I'J I C) 0...
I -30.0000 ---- -------- - +-- 0.1l0008
I ... !\)
-40.0000 -40..1!1088 w
-50.0000 -90. B08I'J
-61!1. 0000 -128. 1i'lS0
-70.0000 -180.000 C5l C5l C5l Ill I
C5l m
I I Ill C5l C5l C5l
I C5l C5l C5l C5l C5l C5l Ill C5l C5l
m C5l m .... !:! 151 m m "Ill C5l ... •
"' Id • • ... ... Fig. ( 6 .10) Closed Loop Frequency Response Test- FREQ Bode Diagram (Upper Band)
---~------------------------------------.-------
-1.001!188 1SILII88'
-2. """"" 14:5.1188
-3. """"" - - -- ---- - - 148.1188
m "lJ
-··""""" 1S5.1188 w z (f) 1--1 < < -5. """"" 188.1188 I C) 0..
-a. """"" 125.1188 ... 11)
"" -7.BI!I88B 128.1188
-B. BBBBB 115.1188
118.1188
-1 e. """" 0.0355 105.1188
t5l
i i I I i I t5l
I I t5l
I t5l t5l .. ; fii t5l .. • • • • •
Fig. (6.10) Closed Loop Frequency Response Test - FREQ Bode Diagram (Lower Band)
12 5
Fig. (6.12) Closed Loop Time Response Test (0.06 Hz)
Fig. (6.13) Closed Loop Time Response Test ( 0.1 Hz)
- ------------------------------
l·~: -:;;:1: .·:·r:~~-···:·· -~- 1
1
1• ····t.' -. -:; ;-~-- .T: --~-- j.: .. : ;:I ...
' ~-:_ :_:_~.l~--- L_-~---- ---· -- ·- ·- . I __ . - ·----· ~-. :-~'?_::. -;--c;:~"'~·.., ·+--'-:..;.._1----:-c-:+'--- --- ---:----, . ·. r:_-7, -~-:_: ---. f-:_ .. · ._·-• . I ; : · ,~ · ; r : : : . . · : ' : • · • : · . : : : i , ; • ·. : : ' · : · I P Signal
I l : - ~ - ; : :· ~· I : : ..
i: . I . !
. I.
."_ 1"-·. ~.; . .:-:..f. -'r 'f~~ .~ ""· yv .-v ··"'r-t ·r .. I' I . i ! I . . . .. .. I. ! -- :
. . I ! . L_...L__.._. -""';~-~,.._ ~-1" ~~'= en I .• • ! I , .. L. .. _._. __ - "' -~
sec. ______ .,.f
Fig. (6.14} Closed Loop Time Response Test (0.4 Hz}
...
STEP
K-r
Fig. (6.15)
STEP
Fig. (6.15)
127
Closed Loop Step Response Test (K=l)
Upper Trace - Shaft Position
Lower Trace - Motor Speed
Cloosed LOO!? Step Response Test (K=2)
Upper Trace.- Shaft Position
Lower Trace - Motor Speed
Position
860 rpm
Speed
Position
1785 rpm
Speed
128 •
Fig. (6.17) Analogue Ramp Input Test (K=l)
Upper Trace - Ramp Input
Lower Trace - Position Response
Fig. (6.18) Analogue Ramp Input Test (K=2)
Upper Trace - Ramp Input
Lower Trace - Position Response .
129
Fig. (6.19) Inverter & And Analogue Controller Set-Up.
---------------Microcomputer Board
Microcomputer Section
- r D.o-ll-7 .. J,o
Serial Communication
Section
--~.-Tx Rx
.. ,.
Analogue Output Section
.L.L D.AC1 D.ACz
I Ao 1-----'\ ll
A 5 1--...--,tl • r
Analogue Input Section
-- .. --
I •
•
1
• r
l
Interface
Board
Fig, (6.20) Digital Controller Block Diagram
240 ,...., I I I ...
Current D.etector
Inverter\ Inverter/ Actuator Input
Signals .,; Set
Position Signal
Position Sensor
.. "' 0
131
Fg.(6.21) The Digital Controller Set-Up.
------------------------------------------------------132
Digital Error · Amptifier
Set Point ~ l!r,(t) Digital PlO
Linear ControQer
To The PWM u" ( t) Inverter
@ I ·-··--··:} ·- ... -· ... . ----- ...... .
ADC I From Position Sensor
Fig. (6.22) Digital PID Controller Functional Block Diagram
- - -- -~ ---I I
Microcomputer Board I
I
I ,..----,
10 ( tl I l;(t)-1 ~(t) I L-....-..J I
I I I
I
I Un=Uo-1+~en(tl+Kzen...,(t) Un 1
+~en-~tl I I I
I
- - --- -- - - - - - --- - -- _J
From Position · Sensor
Fig. (6.23) Implemented PID Controller
iiThe PWM Inverter
Interface~ Board ~
.
133
STEP
a) K=1
STEP
bl K::2 Fig. (6.24) Digital Step Response Test
Fig, (6.25) Digital Ramp Input Test
Fig. (6.26) Actuator Reaponae.to Step Test- Position
Fig. (6.27) Actuator Response Step Test (boosting injection) - Position
... w ...
Fig. (6.28) Actuator Response to Step Test - Velocity
13 6
Fig. (6.29) Effect of External Disturbance
Fig. (6.30) Actuator Position Response to Step Input - P+I Control
Fig. (6.31) Actuator Position Response to Step Input - P+I Control (with increased gain
.. w ....
138
Fig. (6.32) Position Speed Relationship
s
Upper trace - Actuator Position Lower Trace - Motor Speed
1<=0.3 I
Fig. (6.33)Effect of External Disturbance on the Actuator Upper Trace - Actuator Position Lower Trace - Motor Speed
Fig. (6.34) Actuator Position Response to Step Input - P+l+D & P+I
140
PID
0 0 0
Fig. (6.35) Traditional Tuning
t Supervisor
/ '
To
Rule PID Plant
Justifier Controller
.~ / Tuning
.
look-up Tables
Fig. (6.36) Anatomy of the Computer Aided Tuning Algorithm
Fig. (6.37) Actuator Position Response to Step Input - CAT
Fig. (6.38) Actuator Position Response. to Step Input- CAT.
w I. ' '
... ... ...
'
-~--------------------------------------------------------------
'I' j 'I 1:.' ., ;t :t I'
,, 1:
Fig. (6.39) Actuator Position Response to Step Input -CAT
I! ! ! : 'i tt:l I 11 :l::t!ltl
... ... 1\)
'!! J!
. I
I' . . I I ' ..
Fig. (6.40) Effect. of Introducing the Setting Time .Factor on the Actuator Response
. li: I!
!Id I !J'' il' iil!l i!TiiH "qlinJfi;!!i ; ' i, ii I 'I : il;: 1
.11ti".i!lliiil "':l!i::l::; •r: 1!11 T
i I
Fig. (6.41)
..
Effect of Settling Time Factor on the R~sponse
'• I
' : ll' i ~ lt '
' : : i.
" iii .I
I I
' i!. 1 i! I
'I !J 'I' 'I ' I I
: .. , ' ,., .1 I I if
I ! it I I ,I
" ,! I ''
.Fig. (6.42) Response Comparison of the Plant and the Model - Proportional Controller
Fig. (6.43) Response Comparison of the Plant and the Model - P+I controller
CHAPTER·. 7
146
CHAPTER 7
7 Software Design and Development
7.1 Introduction
The function of the software described here is to implement digital
control algorithms for. the closed loop control and tuning of the electric
actuator using the methods shown in section 6.3.2 and 6.4. The source code
is mainly written in CORAL 66, a high level language, with assembler being
used for specialised applications. There are three advantages in using a
high level language; speed of development, problem orientation of the source
language, and inherent structure. Although assembly code executes faster on
the process, actual software development is significantly faster when using a
high level language since it is oriented towards the problem to be solved. 63
CORAL 66 was designed in 1966 by the Royal Radar Establishment
primarily for use in embedded processor systems. The details of the
language are covered in references (64,65 1 66). As such it incorporates some
useful facilities not found elsewhere such as good bit level manipulation and
the in-line insertion of 'CODE' (i.e. assembler) statement. This makes for
easier machine dependent coding in areas such as interrupt handling, time
critical functions, etc.
1.2 Software Structure And Development
The software is organised as a sequence of blocks. Any section of
code which is compiled separately is known as a segment, where each segment
may consist of one or more blocks. The software structure of the digital
controller comprises of a main program segment, sub-main program segment and
five functional segments. The sub-main program contains modifications
implemented during development work and is separated from the main program to
147
decrease working time, whilst each functional segment consist of many
specialised individual procedures which are available for execution by the
main program, sub-main program or by procedures within the same or other
segments (Figure 7.1).
Any embeded program must contain absolute addressing information; in
CORAL this is declared in the Absolute communicators section of the program.
Multisegment programs which share common information must contain a common
·communicators section for declaration of procedures and global variables.
The communicators here in the software structuring are called into use via a
CORAL command called "Library". Using this feature of declaration minimises
the likelihood of producing errors when modifying the communicators sections.
Three library files are used; one contains the absolute communicators for
the digital controller unit, the second one contains the Common communicators
for procedures and the third one holds the global variables used and their
type, i.e. Byte, Integer and Floating.
In this method of structuring each segment can be developed, modified
and compiled individually without touching the others. Each functional
segment holds a set of logically related procedures which, once they are
proven to work correctly on the .hardware, are fixed, i.e. software
modifications are not allowed.
After compiling and assembling each segment separately, their object
files are linked together with the maths Library (Figure 7.2) forming one ~
object file, the main program being the first one linked in. The following
stage is to locate the final object file, that is the CODE, DATA and STACK
areas of memory are defined and all absolute addresses are generated.
Eventually the object file is sent to the EPROM programmer for PROM blowing.
148
7.3 Digital Control Unit
(a) Microcomputer Board memory Map.
Figure 7.3 shows the memory map of the microcomputer board, where the
addresses of the peripherals are nested to avoid overlapping. Addresses
OOOOH up to 0047H are reserved for the interrupt vectors of the 8085
processor.
(b) Analogue Input Section And. Interface Board Memory Map.
It has previously been explained in Section 4.3.4, that addressing
the ADC and peripherals in the interface board is performed through an 8155
Programmable Peripheral Interface (PPI) (Figure 7.4a). Addressing these
peripherals is performed via port C (4 Bit address,RD and WR) and transfering
of data is performed via port A, where RD and WR signals are generated by
software. Figures 7.4b and c show examples of data transfer on the
peripheral bus. The memory map of the Analogue Input Section and the
interface board is shown in Figure 7.5.
7.4 Calibration of Input And Output Sections
7.4.1 ADC Calibration
.Initial calibration of the ADC for both offset and gain settings, is
carried out manually using trimming resistors connected to the converter chip
(Figure 7.6). This is done to ensure that the ADC doesn't exhibit overflow
or underflow, i.e. more than FFFH or below OOOH. Thus once the zero offset
and gain are adjusted the ADC output will attain its
To simplify setting up operations, the operator
"ideal" characteristic.
is assisted by the
microcomputer itself. When calibration is initiated channel 3 of the
multiplexer (the zero signal) is selected first and a start conversion
command is applied to the ADC. At the end of conversion the data output from
149
the ADC is displayed on the VDU and the sequence is then repeated. The
operator trims the zero offset control until the displayed digits flicker
between OOOH and 001H. Then a carriage return key is hit to make the
program transfer to the next stage where the same procedure is carried out
but using channel 4, the 10V reference signal, of the.multiplexer. Once the
gain is adjusted the carriage return key is again operated, so transferring
the program into the DAC adjustment phase (see later).
Unfortunately due to changes in ambient temperature and time the ADC
transfer characteristics change; hence periodic re-adjustment 1s needed in
practical industrial systems. To eliminate any fUrther manual.intervention
an automatic self-calibration technique is implemented.
The characteristic of the ADC is shown in Figure 7.7, where response
(1) represents the ideal one and response (2) represents the characteristic
of the ADC after manual trimming. These offset and gain settings are
deliberately introduced to enable the implementation of the automatic
calibration techniques mentioned above.
By using software correction methods, the characteristic response (1)
can be obtained. It operates as follows:
For the trimmed characteristic (2), the slope is,
Ma= 10 (7.1) ADCFR- ADCZE
Now correction to any digitised analog signal is applied using the
relationship;
Corrected Value = (Input Value - DACZE) • Ma (7.2)
Note that by using of the zero and the 10 volts referance signals, the
processor periodically checks the current values of ADC offset and gain.
150
Hence changes in these parameters can be accounted for in the digitisation
process.
7.4.2 DAC Autocalibration-Wrap-Round Test
Due to the analogue components connected to the DAC output for
buffering purposes, the analogue signal coming out from the analogue output
section of the microcomputer board may not be correct. In particular the
circuit may·produce a negative voltage (instead of zero volts) when the DAC
input is OOOH and an overflow voltage (more than 10 volts) for an input of
FFFH. In this design errors are eliminated by the use of a wrap-round
autocalibration test carried out in software using the analogue input section
(Figure 7.8). The actual characteristic of the DAC, which is a hardware
design feature, is shown in Figure 7.9 (response 2), where its lower value is
a small negative voltage and its maximum value is more than 10 volts. The
autocalibration test changes the reset characteristic to the calibrated one
(Figure 7.9 response 1). Then the minimum value is equivalent to OOOH and
the maximum value to FFFH (4095 decimal).
The procedure for the wrap-round autocalibration is developed as
shown in the flowchart of Figure 7.10; it works in the following way:
The output of each DAC to be calibrated is selected via the multiplexer
and the ADC of the analogue input section. To calculate the negative offset
output voltage of the DAC, an input of OOOH is applied to it and its output
is read back again via the ADC. An adding of one bit at a time to the DAC,
read by the ADC and displayed to the VDU is carried out recuresively until
001 is read by the ADC. This offset value is stored in a memory address
called DACZE. Then the same procedure is carried out for maximum data
calibration, where FFFH is ·applied to the DAC, decremented by 001H at a time
151
until FFEH is read by the ADC. The last value outputed via the DAC is
stored in a memory address called DACFR.
These two values are used as offset and gain correction terms for DAC
output signals, where
Offset = DACZE
Gain(G) = 1 0 (7.3)
DACFR- DACZE
Then, Corrected Output = (Intial Output • G) + Offset.
7.5 Software Functioning
7.5.1 Manual Tuning of the PID Controller
The digital control algorithm sequence is shown in the flow chart of
Figure 7.11, its operation being as follows:
• Block 11.1
The program sequence starts with the main program initialising the
system. This block consists of writing zero data in memory addresses
that are reserved for storing data, calibrates factors and programs the
timers used in the controller. Then the serial communication section is
programmed to write and read text to and from the VDU.
• Block 11.2
The operator enters the gains for the three term controller (Kp, Ki and
Kd) and the sampling time (ST) of the control loop.
• Block 11.3
Calculation of the factors K1, K2 and K3 (the control algorithim
coeffecients) is carried out here using equation 5.11.
152
• Block 11.4
The operator is required to enter the type or signal, step or ramp, which
is to be used in testing the system,
by the software,
• Block 11.5
The actual test input is generated
Calibration for ADC and DAC is carried out and its action is displayed on
the VDU.
• Block 11.6
The actuator is moved under processor control to a position where its
shaft settles at the middle or the stroke. ·
• Block 11.7
The test ror the. actuator starts by reading the demanded kind or input to
be applied to the actuator.
• Block 11.8
For a step function input, its quantity is introduced by
then a comparison between the actual and the demanded
the operator,
(set point)·
position gives the error that should be corrected, moving the actuator,
• Block 11.9
The output from the controller is calculated (U0 ) and applied to the
plant, whilst Un becomes an old command (written as Un-1 ) prepared for
the following calculations.
• Block 11.10
Here the timing for the interrupt RST 7,5 is set and enabled, which when
it is active, calls for the interrupt service routine,
• Block 11.11
A command to the plant is generated here.
• Block 11.12
153
The processor waits until interrupt RST 7,5 is activated,
• Block 11 , 13
This performs the RST 7.5 interrupt service routine which starts the
conversion .of the ADC, for a new feedback' sample from the actuator's
sensor. During conversion time of the ADC which takes around 12 msec.,
the calculations and preparation for a new command takes place,
• Block 11.14
This consists of writing errors en_1 in en-2 and en in en-1 for the next
sample preparations.
• Block 11, 15
The program here either performs for ramp or step test with a limiting
output analogue value of 5 volts,
* Block 11.16
The error of sample n-1 (en_1 ) is multiplied by K2, added to error n-2
factor (K3 e,..2 ) , added to the previous command applied to the motor (Un-1l
and the result of this process is stored in memory,
• Block 11 • 17
The program waits here for the ADC to finish conversion.
• Block 11.18
The output data from the ADC {i,e, the actual shaft position) is
subtracted from the demanded position, multiplied by K1, and its result
is added to the process result of Block 10.16.
• Block 11.19
Here Un is checked, Its absolute value sets the motor speed command
while its sign determines motor direction,
• Block 11. 20
Un command is sent to the motor and the program loops back to the
154
procedure starting from Block 11.12.
7.5.2 Computer Aided Tuning of the PID Controller
The flow chart for this controller is shown in Figure 7.12, the
program functioning as follows;
• Block 12.1
The program sequence starts here and comprises of writing zero data in
memory addresses reserved
programs the timers used
for
in
storing
the
data, calibrates
controller. Then
factors and
the serial
communication section is programmed to write and read text· to and from
the VDU.
• Block 12.2
The sampling time is entered here by the operator.
• Block 12.3
The primary tuning for PI controller is selected here by getting Kp and
Ki from the memory.
• Block 12.4
Calculation of the factors K1 and K2 is carried out here using equation
s .. a.
• Block 12.5
The calibration for ADC and DAC is carried out and its action is
displayed on the VDU.
• Block 12.6
The actuator is moved under program control to a position where'its shaft
settles at the middle or the stroke.
The same procedure is carried out here from Block 12.7 up to Block 12.16
as in Section 7.5.1 from Block 11.9 up to Block 11.18 excluding Block
155
11.5 and the factor (K3 Un-2l they are not used.
• Block 12.17
Here Un is checked, if it is less than zero, then its absolute value is
taken and motor direction is reversed. Also here a rule is implemented
when there is a demand by the operator to change the settling time (this
is explained later in this section).
• Block 12.18
Un command is produced and applied to the motor.
• Block 12.19
Here the number of loops (samples) is compared to 1500; if it is not
equal then the. program sequence returns before Block 12.6, and otherwise
it transfers to implement the CAT algorithm.
When the actuator reaches its demanded position the software program
transfers to the MMI-CAT implementation. The main program logic of this
application is shown in Figure 7.12, where, on entry to the program, the
actuator response is modified or left unchanged. If it is to be changed
three parameters may be adjusted; rise time, overshoot and settling time.
Each one of the chosen parameters is classified within four zones of change,
as follows:
Decisions concerning these changes are made by the operator but
algorithm tuning is carried out automatically by the software. The blocks
X, Y and Z of Figure 7.12 are expanded to give the flow chart shown in Figure
7.13. The decision rule for tuning Kp and Ki that is taken from Blocks X, Y
and Z are shown in Figures 7.14, 7.15 and 7.16 respectively.
A photograph for the complete controller Set-Up is shown in figure
7. 17
MATHS UBRARY
156
call procer:U·--m-a-=in---. --•program
- ..... segment 1 /:-----.., ~-- -- --\: .... - - -··-· I I
r!..----- 1 ---------, I 1 I
segment
N
1 I
Fig. (7.1) Subroutine Excursions
•
LIBRARY FILES
I I 1· ' ' I \ \
I I I I \ 1 I I \ '
I I I I \ ..-----AL-_, - - - - - - - - - r---"'---,
HAIN PROGRAM
-,-,r-r/' I I I I
SEGMENT N
I I I
LINK } OBJECT FILES loCATE
EPROH
Fig. (7.2) Software Processint
DAC2{
USART{
PP!
l/0
D400H
RA/1
157
EB03H E802H EB01H EBOOH
E003H. E002H E001H EOOOH
DB03H DB02H DB01H DBOOH
D405H D404H D403H D402H D401H
DOFFH
DOOOH
3FFFH
EPR0/1
-------------- 0047H L.__I_NT_B_"R_Rlli_'P_T_Vl_'EC_TI_VR._s __ ___, OOOOH
Fig. (7.3} Memory Map. of Microcomputer Board
158
Port A
8155 PPI Port
B 1\,.;~~=
a PPI Interfacing
To- Analogue liP Section & Interface
Board
~~:ss _______ '"I ___ ...... [~~JL. ___ __.I ____ t
[lb.TA ---~ Byte 1 ~~-< Byt-e 2 >---t
WR -----------' I_ ___________ I l_ _____ t b CS Followed by t'IR
WR ________ L-.,.1 _ ____.!_ ____________ t
DATA ---<\... _______ .....~t-----,--t
RD --'------- --- _U_ -------------t C WR Followed by RD
Fig. (7.4) I/O Port Signals Generation
ADC &
M-LXR
ADC &
M-LXR
159
~----~~~--------~2DH r-~----~~--------~2CH r-------~~--------~28H 1------~'!fr--'~--------~ 2A H r-------~~--------~29H
._hr-r-r-,.-T--'t----lf--7--r-"7""""']..-..r-r-.,..--,1 2 8 H
1DH 1C H
~----~~~--------~ WH 1-------*~r---------; MH ~----~~~--------~19H ~~,..-~~~r.~~~~~~~WH
Fig. (7.5) Analogue I/P Section and Interface Board Memory Map
10 VOLTS REF.
0 VOLT REF.
160
Multiplexe.
D
GAIN OFFSET
TRII11ER
...
~
ADC 12-Bit Oat~} --,
. r ZERO O~ET
TRIMMER
Fig. (7.6) ADC Calibration Block Diagram Configuration
Voltage
10V -------------
ADCZE
Fig. (7.7) ADC Characteristic
161
~· ~
12-Bit ' ADC 12-Bit )
DAC M.Jltiplex~::~ Data l Data
r ,
Fig. (7.8) DAC Calibration Block Diagram Configuration
-----------
Fig. (7.9) DAC Characteristic
ADD 001H TO DAC !lP
SUBTRACT 001 H FROM DAC Ill'
F
162
CONVERT TO ANALOG
CONVERT ANALOG
SIGNAL TO Oli!TAL
READ ADC 0/P
CONVERT ANALOG SIGNAL T 0 DIGITAL
DACFR-DAC !JP
DACFR =DACFR
Fig. (7.10) Automatic Calibration Flow Chart (ADC & DAC)
........... ----------------------~--------------------------~---------------------163
INTIALISE 11.1 PROGRAM
11.2
CALCULATE 11.3 Kt, K2, K3
n.4
11.20 to motor
comma
wat or INr zs
11.n
11.12
------ ---· • START ADC
11_13
CONVERSIQ
11; 14
calculate Un Un-1-Un.
SET .INT. 7.5
12.7
12.8
12.13
12.14
12.15
12.16
12.17
164
F RET. TO A
T
~----- ---------------
@ TUNE
X F
D
TUNE DECISION V
y .: ---- --- - - --- - ---- • .J F T
r-----·-·-· I r-·-··--· : z DECISION
L--------------------.---------~----~~TUNE ~----..J
Fig.!7.12l CAT Control Algorithrn-Fiow Chart
I
• I I I ·- -------- ... ------ --·
--·-----------------------------------------------=--------------------------------------------
" / ' .
/ /
'
;'
/f ;'
/ ;'
./
/F /
RET TO A
/
T
F
F
;' ;'
/
T
F
'·
/ /
/ / / ;'
/ ;'
' ....... ' '
H :INCREASE RT: RISE TIME L: DECREASE OS:!NERSHOOT
......
RET TOA / ~F
;'
/
;'
/f /
/ / ......... X /
....... //
' " .............
......................... z /// TS:SETIUN!i TIME
.... / ....,
Fig. (7.13) CAT.Main Logic Flow Chart
;' ;'
/
"''
" / /
/ /
' ' '
;' ;'
;'
...... ......
...... '
'
... 01 -.j
- - - - - - - - - - - - - - - - - - - - - - - - - -I
d ( c. ( b I
+ t • I
Decrease Decrease Increase I
Kp Kp Kp I • t t
GTO MAIN - 1: - - - - - ":" - - - - - - - - - - .. -- - - - - -PROGRAM8J
- - - - - - - - - - - - - - - - - - - - - -
Decrease Decrease Increase K; a Kp K; CJ..Kp K;CiKp
.
- - - - - - - - - - - - - - :... -t- - - - - - - -( TO MAIN
PROGRAM.£
Fig, (7,14} Rise Time Tuning Rules
- - - -TUNE X
- - - -
- - -DECISION
'
- - -
-
- - - - - - ,
-
w
a
__!
Increase Kp
- - - -
)
I I
- .J
- - - /FRCl-1 MAlt) ~OGRAM[
I
Increase I
K;CJ.Kp I ...
01 01
I
I
.I - - - - -
L--------------------------------------------------------------------------~---------------------------
I
I
I
Decrease K;
-----
T I I I I
I L
-
-
~ - - -
I Increase KpaK;
I - - -
Fig. ( 7 .15)
Decrease K· I
------
Increase Kj
-------
Increase K,· a Kp
Increase K;
TUNE Y
Increase K; a Kp
- - - - - - - - -· - - -
c FROM MAIN ) PROGRAM y
-- - - -- - - - - - - - - - - - --- - - -DECISION V -
I
I . I I -Increase IncreaseK; IncreaseK;
Kp a K; Decrease Decrease Ko a Ki Ko a Ki
I I I - - - --- - - - - - - - - -- - - --- -.
TO MAIN PROGRAM E
Overshoot Tuning Rules
h
Decrease Ki
RET. TO A
9
Decrease Ki
RET. TO A
f
Increase. Ki
RET. TO A
Fig, (7.16) Settling Time Tuning Rules
e
Increase Ki
RET. TO A
...
..... 0
...
Fig (7 .17) Experimental Set-Up
CHAPTER 8
172
CHAPTER 8
8 Conclusion
The conclusion arising from the project described in this thesis,
together with suggestion for future extension of the work, may be summarised
as:
(a) Conclusion And Comments
The experimental investigation and the results presented in Chapter
3, 4 and 6 show clearly that the pulse width modulated position
control system developed in the research work offers an attractive
possibility for use with fractional horsepower induction motors.
2 The use for Power FETs in the inverter eliminates the need for forced
commutation, and solves the problem of trapped energy inherent in
other switching based systems. The drives of the power switches are
simple, low cost, and small in size.
3 Since both the voltage and frequency of the power circuit can be
controlled, it offers a significant advantage for zero speed torque
boosting to accommodate high stiction problems and for high inertial
loadings.
4 PWM inverter techniques enable either continuous or digital closed
loop control methods to be used in the actuator system.
5 Accurate closed-loop control of the actuator can be achieved by the
use of a PI algorithm implemented ·on a microprocessor based
controller, the steady state error being less than 39 micrometers for
a well tuned system (i.e. equal to 0.036% of full stroke range).
The microcomputer, based on an 8 Bit microprocessor, is a simple
controller, which doesn't require the use of special maths eo
processors or similar devices to attain this performance.
173
6 Transfer function analysis testing methods proved to be easy and
simple to use, the results so obtained leading to the development of
an accurate mathematical model of the plant, Using this model for a
computer simulation of the plant facilitated-the evaluation and
development of control tuning strategies,
7 Computer aided tuning has been shown to be a technique having
significant practical potential, When implemented correctly it
enables an inexperienced operator to tune the plant for the best
attainable closed loop purpose; moreover it eliminates the need for
the operator to have an understanding of control theory. It can be
used for actuators ___ other than the· experimentral one without the need
to change the in-built software parameters.
8 On-line MMI proved to be a very powerful tool for the development and
debugging of the software functions, setting up the system, and fault
investigation and diagnosis. It is essential to incorporate MMI
facilities for the use of CAT methods_for system set-up.
{b) Suggestion For Further Work
1 Develop software to allow frequency response testing to be carried
out by employing the digital controller, eliminating the ,need for
external measuring equipment {TFA).
2 Implement an on-line identification scheme for the plant to be
carried out using time domain methods in both open and closed loop
operation.
3 Develop tuning methods for the actuator which minimise operator
involvement.
4 Extend the work to cover non-linear modes of operation.
5 Develop general purpose ex p-art system tuning 67
methods for
174
actuator/servo control systems,
(c) Comments on Problems
Problems were associated with the work, the major one being that of
electrical noise and interference affecting the microprocessor
hardware; this· caused malfunctioning to microcomputer board. Noise
was picked up from the keyboard, the power system and the inverter.
The other main problem was backlash in the mechanical shaft which
produced a non-linear effect in the control system, As a result the
system exhibited a small steady-state error unless very fine tuning
was adopted,
175
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lASTED Conference on Computer-Aided Design and Applications, Paris, 1985.
- APPENDIX A -
Electronic Design~Detailed Design
180
Appendix A
A.l Semiconductors Selection parameters
Induction Motor Characteristics
3~ 115 V .1/6 HP
tfuen rectifying 3~ 115 V the average d.c. rail voltage is
V = V X ,12 X 3/Tr d.c.(nom) a.c.
V (rms) < 1.1 *V //2 = LOS Va.c. o ... d .. c. (non) .
assuming 3~ main supply 115 V r.m.s. with ± . .10% when rectified
giving
V = 115 * /'i * 3/Tr d. c. (min)
= 140 V
V = 115 * /i * 3/11 d.c.(nom)
= 115 V
Peak d.c. supply voltage at maximum a.c. supply is obtained
from the peak a.c. supply voltage given by:
V = 115*1.1*/2 a.c.(pk)
= 178.8 V
Under regenerative braking conditions, the d.c. supply voltage
rises above V ( k). Assuming a permitted rise of 80 v, · a.c. p
V = 178.8 + 80 = 258.8 V d. c. (max)
For 1/6 HP
Power= f3·IL·VL•COS~·effic.
18.1
~ * 746 = /3 *llS*IL*0.8*0.8 6
IL = 1 amp
Assuming SO% transient overload
I ( ) = l*l.S = l.S A r.m.s. m max
When using the motor at maximum switching frequency k kHz
VDRM = VRAM = 2S8.8 + SO = 308.8 V
In worst case
= l.S * 12 1T
= .676 A
~ S*0.676
= 3. 38 A
IFRM = 20*0.676
= 13 A
PMOSFET
DIODES
182
A.2 Main Power Supply and Smoothing Circuit Capacitor Filter
8 IN is the capacitor input waveform duty cycle
·~IN 8 IN: 0 where ~IN diode conduction period
D is maximum diode conduction period
For lp bridge rectifier D = 3.3 msec
1 6 IN=3.3 =· 3
a IN= 1 msec
The rectified 3-phase supply with uniform input current pulses to
the capacitor
!12 2 (--- 1) I de 8 8rN
where: Id.c. is the average d.c. current= 1.5
iin = 2.64 A
i2 = out .25 X I2
de = .563 A2 i t=.75 A ou
i2 = 7 + .563 = 7. 56 A2 i = 2.75 cap cap
• 563 ) =
1.1252 2.44 A
IR = 2.44 X .8 = 1.99 A
From table c = 330 ~f corresponds to IR = 2.2 (P..187l
183
A.3 Circuit Power Supply
Assuming RL (worst case)
Rs
= 15 V
= 15g 1 A
% ~ = 6.6%
From rectification characteristic
V c
V m
where
and
. .
= 80%
V = Average d.c. output voltage c
V = peak input voltage m
.VC = 15 xl2 X 0.8 = 17 V
Allowing a voltage drop across the diodes of the bridge of 1.2 V, the
input voltage to the series regulator at a full load is 1 A is 15.8 v.
The voltage reference Zener diode was rated at 10 V 400 mW referring
to fig (3.34).
Assuming the voltage rises·up to 18 V and a required Zener current of
10 mA:
Rl = (18 - 10.4) V = 5600 10 mA
V = ( 18.15 - 2 VEB) = 1. 8 V drop across the series limi ter
allowing say 3 mA for IR2 gives:
1.8 .6 kfl R = = 3
VB = 10.4 = Vo R4
R3+R4 let R4 = 10 giving R3 = 4.4 Kn.
let R3 = =.9 kQ and Ry = 2.2 kQ
. I
184
The full load regulation of the d.c. supply is about 3% whith a full
load ripple voltage of 0.6%.
185
A~ The overall system transmittance T can be shown to be given by the m
following equation:
T m
Sensitivity to overall system transmittance with respect to change
in each parameter is. as follows:
a. with respect to K1
parameter
=
where
dT m
= dKl
s TM
Kl
dT /T m m d~11!a
=
(1 + K2) G-0
(1 + K G) 2 2
Kl Tm = x-
T Kl
b • with respect to K2
T d T /T 5
K2 m m m
= dK2/K2
where
dT 0 - K G2 m 1 --=
dK2
(l+K2
G)2
=
=
=
=
dT m
dKl
G
1 + K2
G
1
K2 dT m
T dK2
K 2G2 1
=
K1 (l+K2
G)2
=
T 2 m
X--= Kl
For cases K2 >> 1, this reduces to
T s m,_l
K2
186
c. With respect to G
where
T S m =
G
dT m --=
dG
T SG m
(1
d T /T m m dG/G
+ K2G)
=
K -1
(1 + K G) 2 2
G K1 =- =
G dTm
T dG
K1
GK2
= T (1+K2G) 2 1
K1 = (l+K
2G)2
1
+ K2
G
187
Design N~tes __ Cln Select1!lf! __ Tl1~ __ D_c__E_moothing Cap':citor,
again using a constant forming voltage. TI1is ensures that any spots where tile dielectric layer is missing, such as the edge or the cut roil, are anodically oxidised. The
"'reforming process results in a capacitor with an extremely low leakage current. .
The capacitor is then insulated in a plastic· sleeve berore being finally inspected and tested.
CAPACITOR DESIGN AND RIPPLE CURRENT RATING
A ripple current 1, will result in a rate or heat generation substantiaUy equal to J1,R, where R is the errective series resistance. To produce a capacitor with a high ripple current rating thererore requires a low errective series resistance and efficient heat dissipation. From the above description, the rea tu res or the 114/115 series capacitors which contribute to their high ripple current rating can be summarised as rollows. • Multi-tab construction • l.Dw-resistance electrolyte • Good thermal contact between winding and can
(rilled can construction) Details or the rated ripple currents ror the 385 V 115
series electrolytic capacitors are given in Table 2. (For run details or the complete 114/11 5 series, see published data). The maximum ripple current is dependent on ambient temperature and frequency, and the influence of these two faciors is now considered.
Ambient temperature
Tite lire expectancy or an electrolytic capacitor is deter· mined principally by its core temperature, and the 114/ liS series capacitors are designed to operate at a maxi· mum core temperature of 95°C. The core temperature will be determined by the ambient temperature and the heating errcct or the ripple current. Tite 114/115 series capacitors are rated at an ambient temperature of 85°C. and at this temperature the rated ripple current therefore COIHrihutes a temperature rise at the capacitor core of
0
I 0 C. At lower amh_ient temperatures, the maximum allowable ripple current (giving a core temperature of 95°C) will contribute a greater temperature rise at the core, and will therefore be greater than the rated ripple current. The 1:naximum ripple at an ambient temperature T is related to the rated ripple current {at 85°C) by:
IR J( 951-0T) lr(T,95) = (2)
where lr!T ,9!' 1 is the maximum ripple current at an ambient temperature T and a core temperature 95°C. IR
TABLE 2
Rated ripple currents ror 385 V 115 series electrolytic capacitors
Capacitance Rated ripple current (IR) "F 85"C, 100Hz
ISO t.2 220 t.6 330 2.2 470 2.7 680 4.8
1000 7 1500 7 2200 9
TABLE3
Multiplier for rated ripple current as a function of ambient temperature
Ambient temperature Multiplier (MT) ·c
85 t.O 80 t.22 75 t .41 70 1.58 65 1.73 60 1.87 55 2.00 50 2.t 2 45 2.24
<:40 2.35
is the rated ripple current at 85°C ambient, and MT is the temperature multiplying factor ror ripple current (see Table 3). It should be noted that both ripple currents in Eq.2, 1r(T ,95) and IR, are specified at I 00 Hz.
Frequency
Tite power dissipated by the dielectric and cathode oxide layers rails with rrcquency. so that the maximum ripple current can be increased as the frequency is increased. Ripple current ratings arc usually standardised at I 00 lfz: ftH non·sinusoidal ripple currents (and hence for multi· rrcquency ripple currents) the equivalent ripple current at lOO llz_is given by:
(3)
where .In is the ripple current at a given frequency. and .Jr n is the multiplying ractor at the same rrcqucncy (sec Table 4).
TABLE4
Multiplier for rated ripple current as a function of frequency
Frequency Multiplier (../r 0 )
llz
50 0.83 100 1.00 200 1.10 300 1.125 400 1.15
1000 1.19 >2000 1.20
RELIABILITY
188
The 114/115 series capacitors are the result of an extensive programme of development and testing. As such, they are highly reliable and if properly selected will give long and predictable service.· As with aU components, however, some failures will occur during the designed service life. For 114/115 series capacitors, this rate of failure is extremely low and relatively constant, and is an indication of reliability.
After a certain time, gradual changes in the properties of the capacitors reach a point signified by a sudden and marked increase in the failure rate. The time taken for this to occur is a measure of the life expectancy of the capacitors.
Fig.7 shows a curve of failure rate as a function of time. The curve can be divided into three distinct zones:
A) failures during manufacture and bum-in procedure (infant mortality);
B) failures during service life; C) failures at the end of useful life (wear-out period).
For 114/115 series electrolytic capacitors, the failure
failUre rate.
. \A B c
V t•me
MI0-0099/1
Fig.7 Failure rate as a function of time
rate during service life (60% confidence level) at 40°C and rated voltage is I X 10"7 /b (catastrophic failures). Temperature and voltage derating have a relatively small influence on this figure. A voltage derating of 50% reduces the failure rate by a factor of approximately 4.5, while a reduction in ambient temperature of approxi· mately 15° c reduces it by a factor of 2.
SERVICE LIFE
As indicated above,the life expectancy/service life (region B of Fig.?) is largely determined by the core temperature, and for capacitors operated at the maximum core temperature of 95°C, the life expectancy is typically 10 000 h. By lowering the core Jemperature the life expectancy can be extended, each ro•c reduction in the core temperature resulting in a doubling of the life expectancy. Thus a core temperature of85°C gives a life expectancy of about 20 000 h, while a core temperature of 5o•c gives a life expectancy of Some 200 000 h, equivalent to approximately 25 years of continuous operation. The guaranteed lifetime (standard endurance test) is 5000 hat an ambient temperature of 85°C.
A specified extended life expectancy can be obtained by selecting a capacitor to operate at the appropriate core temperature. The method of capacitor selection is best illustrated by an example.
Example -Selection of capacitor for extended life expectancy
Required voltage rating
Operating frequency
Ambient temperature
Required ripple current
Required extended life expectancy
385V
300Hz
6o·c
3A
40000h
The first step Is to determine the ripple current at 100Hz equivalent to the required ripple current at the operating frequency of 300 Hz. From Eq.3 and Table 4:
3 .,, = T.T2S •
I, = 2.7 A.
To obtain an extended life expectancy of 40 000 h, a capacitor must be selected that will have a maximum core temperature of 75°C, when operated with a ripple current of 2.7 A (referred lo 100Hz), at an ambient temperature of 6o•c. The maximum allowable ripple current for an ambient temperatUre T and a core temper· ature 0. l,cT.O)• can be obtained by generalising Eq.2 to
189
- APPENDIX B -
Software Documentation
190
APPENDIX B
Digital Controller for Electric Actuator Models
B.1 LIST OF MODULES
(a) SECTION 1 - MODULE NAME
(b) SECTION 2 - MODULE NAME
(c) SECTION 3 - MODULE NAME
(d) SECTION 4 - MODULE NAME
(e) SECTION 5 - MODULE NAME
(a) SECTION 1 - MODULE NAME
MODCOM
MO DIN
MODIO
MODMR
MODIB
MODCOM
This section contains the set of communication I/0 procedures used in the
development of digital control algorithm.
1.1 TEXT WRITE
1. 2 PRINT CHAR
1.3 READ CHAR
1.4 CRLF
1.5 CONSOLE CHAR
1.6 READ ECHO
1.7 CHECUP
1.8 LIMIT
1.9 RFLOAT
191
(b) SECTION 2 - ~ODULE NAME MO DINT
This section contains the set of procedures used in the development
preparation of the control algorithm,
2.1 COMSET
2.2 RDATA
2. 3 SAMPR
2.4 STCONV
2.5 PWM OF
(c) SECTION 3 - MODULE NAME MODIO
This section comprises the set of procedures used for analog signal
handling,
3.1 SETING
3.2 CONVERT
3.3 WRITEOUT
3.4 WRITEOUT2
3.5 SPEDR
3.6 DISPLAY
(d) SECTION 4 - MODULE NAME : MODMR
This section contains procedures used to control the speed of the motor
and incorporate current limit control features.
4.1 DELAYI
4.2 ACCELRT
4.3 DECELRT
4.4 BRAKE
192
(e) SECTION 5 - MODULE NAME ; MODlB
This segment sets up communication with the interfacing board for control
of the motor inverter.
5.1 PWMON
5.2 INTITMI
5.3 TIMER1
5.4 INTITMO
5. 6 TIMERO
5. 7 INTITM2
5.8 TIMER2
5.9 TIMSET
B.2 DETAILS OF SOFTWARE MODELS
SECTION 1 - MODULE NAME MODCOM
This section contains the set of communication I/0 procedures used in the
development of digital control algorithm.
1.1 TEXT WRITE
This is used to write out text to the serial line.
1.2 PRINT CHAR
This is used to print out characters to the serial line via the UART;
it also checks that the UART is ready to accept a new character.
1.3 READ CHAR
This reads a character from the serial line under program control
(not interrupt). It first checks to see if there is a character
ready for reading, if·so it places it in a program defined location
"charin".
1.4 This performs a carriage return/line feed for the VDU.
193
1.5 CONSOLE CHAR
This reads character from the console and writes it in the UART data
address "UARTD".
1.6 READ ECHO
This reads a character from the UART and writes it back so that the
character appears on the VDU screen.
1.7 CHECUP
This procedure reads two characters from the console followed by a
carriage return.
1.8 LIMIT
This check up two digits used to control the frequency of the motor
which should not exceed to70Kz.
1.9 RFLOAT
This writes floating point values to the VDU.
SECTION 2 - MODULE NAME : MODINT
This section contains procedures used in the development preparation of
the control algorithm.
2.1 COMSET
This resets the UART and initialises it for operation.
2.2 RDATA
This reads data from the ADC once conversion is finished.
2.3 SAMPR
This programs the timer of the I/0 ports (PPI) to set the interrupt
service routine timing.
2.4 STCONV
This starts ADC conversion.
194
2.5 PWM OF
This switches 'off' the PWM controller chip when initialising the
digital ·controller software.
SECTION 3 - MODULE NAME MODIO
This section comprises of set of procedures used to deal with the
analogue I/P and 0/P sections.
3.1 SETING
This converts 12 bit binary value to Hexadecimal value and sends it
to the VDU.
3.2 CONVERT
This procedure selects the required analogue channel for conversion
and issues the start conversion command. It waits for the ADC to
end its conversion then reads the digital data available at rrs 0/P.
3.3 WRITEOUT
This procedure outputs a 12 Bit value to AD 7542 Nibble mod DAC.
Each is loaded sequentially followed by a write command to output the
data.
3.4 WRITEOUT2
This is the same procedure as 3.3 but this loads the second DAC.
3.5 SPEDR
This procedure converts 12 Bit value from Binary to BCD to write it
on the VDU.
3.6 DISPLAY
This converts Binary integer into BCD to display it in the VDU.
SECTION 4 - MODULE NAME : MODMR
This section contains procedures used to control the motor ·speed under
restricted value preventing overshooting of current to occur.
195
4.1 DELAY1
This procedure produces a software delay of approximately 20 msec.
4.2 ACCELRT
This procedure speeds up the motor to its demanded step input at a
restricted acceleration.
4.3 DECELRT
This reduces the motor speed to its lower demanded step at a
restricted deceleration.
4.4 MOVE
This comprises of a Look-up table that makes the motor accelerate to
its demanded speed at an incremental frequency step of 3Hz.
4.5 BRAKE
This decelerates the motor to its lower speed demand by decrementing
the frequency input to the motor at a rate of 3 Hz.
4.6 POSITION
This procedure is used to change the direction of rotation of the
motor.
SECTION 5 - MODULE NAME : MODlB
This segment sets communication with the interfacing board for
controlling signals provided to the inverter.
5.1 PWMON
This sets the PWM controller chip 'on•.
5.2 INTITMI
This programs timer1 of the interfacing board.
for initialisation and controller mode change.
5.3 TIMER1
It is called both
This writes data to timer1 of the interfacing board to change its
196
output clock rate (which is used to control the speed of the motor).
5.4 INTIMO
This programs .the working mode of timerO of the interfacing board.
5.5 TIMERO
This writes data to timerO of the interfacing board to change its
output clock rate (which is used to control the torque of the motor).
5.6 INTIM2
This programs the working mode of timer2 of the interfacing board and
has to be called once unless its mode needs to be.changed.
5.7 TIMER2
This writes data to timer2 of the interfacing board to change its
output clock rate.
5.8 TIMSET
This procedure feeds data to timer1; low and high byte.
' 197
'COMMENT' LIBRARY FILE "TTCABS"
VERSION: V1.1 DATE:4/10/84 AUTH:ZHI
ALL ABSOLUTE COMMUNICATORS ARE DEFINED HERE;
'ABSOLUTE'('BYTE' DAC1LO/'HEX'(EOOO), DAC1HI/'HEX'(E001), DAC1HI/ 1HEX'(E002), DAC1LD/ 1HEX'(E003), DAC2LO/ 'HEX I (E800)' DAC2HI/ 1HEX 1 (E801), DAC2HI/'HEX 1 (E802), DAC2LD/'HEX'(E803), COHREG/'HEX'(D400) 1
DATAL/ 1 HEX 1 (D401) 1
DATAH/ 'HEX' (D402), CONTRL/'HEX 1 (D403) 1
TIH1L/'HEX' (D404), TIH1H/'HEX'(D405), UARTC/ 1 HEX'(D801), UARTD/ 1HEX 1 (D800));
'COHHENT'THE MEANING OF THE ABSOLUTE LABELS ARE DEFINED HERE.
DAC1LO :FIRST 4 BITS LOADING OF DAC No.1. DAC1HI :SECND = ---- ------- = ==== === -------DAC1HI :THIRD = ==== ======= = ---- === DAC1LD :LOADING THE 12 BITS OF ==== ---DAC2LO :FIRST 4 BITS LOADING OF DAC No.2. DAC2HI :SECND = ---- ------- = ---- === -------DAC2HI :THIRD = ---- ------- = ---- === -------,. DAC2LD :LOADING THE 12 BITS OF ---- === DATAL :SELECTING OF PORT A DATAH :========= = ---- B CONTRL ========== = ==== c
. TIH1L :PPI TIMER - LOW BYTE TIH1H :=== ===== - HIGH BYTE UARTC :SERIAL COH. COMMAND PORT UARTD ======= --- DATA PORT;
1COHHENT'THIS IS EXTRA INFORMATION ON I/0 ADDRESS SPACE • ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
DESTINATION/SOURCE ADC CH.1
2 3 4 5 6 7 8
PORTC WRITE 'HEX 128
29 2A 2B 2C 2D. 2E 2F
PORTC READ 'HEX' 18
19 1A 1B 1C 1D 1E 1F
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• I
'COMMENT I
ERSION: V1.3 ............ LIBRARY FILE "COMLIB"
DATE: 12/04/84
198
AUTHOR: ZMI
ALL COMMON COMMUNICATORS ARE SPECIFIED HERE;
1COMMON 1 ( 1BYTE 11 PROCEDURE'CONSOLE CHAR); 1COMMON 1 ( 1PROCEDURE'COMSET,
,.
TEXT WRITE('VALUE''INTEGER 1 ) 1
READ CHAR( 1LOCATION''BYTE'), PRINT CHAR('VALUE 11BYTE 1 ) 1
READ ECHO('LOCATION''BYTE 1 ) 1
TIMERO('VALUE''BYTE'), PWMOF('VALUE''BYTE'), DELAY1, INTITM1, PWMON( 'VALUE I 'BYTE I)'. ACCEL('LOCATION''INTEGER 1
11VALUE 11 INTEGER'),
DECCEL('LOCATION 11 INTEGER 11
1VALUE 11 INTEGER', 'VALUE "BYTE I) ' TIMER1 ('VALUE I 'BYTE •• 'VALUE. 'BYTE') I
POSITION('VALUE 11 BYTE'), LIMIT( 'LOCATION I 'BYTE I I 'LOCATION I 'BYTE I' 'LOCATION I 'BYTE I' 'LOCATION I 'BYTE I)·, CHEKUP( 1LOCATION 11 BYTE 1
11LOCATION 11 BYTE 1 ,
'VALUE I 'BYTE I) I CONVERT( 1LOCATION 11 INTEGER','VALUE''BYTE 1 ),
WRTOUT( 1LOCATION 11 INTEGER 1 ),
WRTOUT2('LOCATION 11INTEGER'), SETING( 1LOCATION 11 INTEGER 1 , 1LOCATION 11 BYTE 1 ,
1LOCATION 11 BYTE','LOCATION''BYTE', 'LOCATION 11 BYTE 1 ),
TIMSET('LOCATION 11 INTEGER 1 ),
SPEDR( 1VALUE''INTEGER 1 , 1LOCATION 11 BYTE 11
'LOCATION I 'BYTE I I 'LOCATION I 'BYTE I I
'LOCATION''BYTE'), DISPLAY( 'VALUE I 'INTEGER I. 'LOCATION I 'BYTE I. 'LOCATION I 'BYTE I I 'LOCATION I 'BYTE I' 1LOCATION''BYTE 1
11LOCATION 11BYTE 1 ),
MOVE('LOCATION''INTEGER 11
1VALUE''INTEGER'), BRAKE( 'LOCATION I 'INTEGER I. 'VALUE I 'INTEGER I)' SAMPR ( 'VALUE I I INTEGER I) • RDATDC('LOCATION 11 INTEGER 1 ),
STCONV('VALUE''BYTE'), CRLF, RFLOAT('VALUE'rFLOATING'), INTITM2,TIMER2('VALUE 1 'INTEGER'));
200
'COMMENT' LIBRARY FILE "ZLIB";
VERSION: V1.1 DATE: 30/08/85 AUTHOR: ZMI
••••••••••••• ALL GLOBAL VARIABLES FOR THE MAIN AND SUBMAIN PROGRAM ARE DECLARE HERE;
'COMMON'('BYTE'BELL,LINEF,DIGITH,DIGITL,OFF,FALSE,TEST,DIRECTION,
CRTRN,CH3,UNIT,HUNDR,INPUT,FL,FL1,FRD,VD,I,PT,
RESPONSE,CR,Il,I2,I3,D1,D2,D3,PITCT,PITCTL,TFREQ,
RETURN,SET,CH4,CH1,CHAN,TENS,THOUS,STH,STL,STLL,
CH5,0VERSHOOT,RISETM,ADCZE,ADCFR;
'INTEGER'SAMPD,PITCNT,IDATA,FDATA,K,J,COW,Q,DATA,RSL,
RVM,RPM,ISTEP,DPOS,APOS,Kp,ST,OUT,EIN,UIN,UOUT,
ENEW, NEW,K1,Kd,K1,K2,K3,DATA1,DACZE,DRAT,DACFR,.
Ma;
'FLOATING'FK1,FK2,FK3,FKp,FKd,FK1,FEOLD,EOLD,EOLD2,FEOLD2,
FUOLD,UOLD,FDAC,KN,ENEW,FD1,FD2,FD3,FI1,FI2,FI3,FST,
FUNEW,CFOUT,FOUT,FSAMPD,FDPOS;
'INTEGER'~ARRAY'SDD[1:2000];'LABEL 1NXTP,VECT75;);
201
'CORAL I B1;
'COMMENT' THIS SECTION CONTAINS THE SETTING OF THE SYSTEM TO COMMUNICATE WITH THE OPERATOR BY ENTERING ALL THE VARIABLES NEEDED FOR THE MANUAL TUNING OF THE PID CONTROL ALGORITHM IN POSITION COMNTROL OF THE MOTOR
VERSION: V2.7 DATE: 30/08/85 AUTHOR: ZMI .............. I
'COMMENT'ALL ABSOLUTE VALUES ARE DECLARED HERE; 'LIBRARY'":F1:TTCABS"; 1COMMENT'THE COMMON COMMUNICATORS ARE CALLED UP HERE; 1LIBRARY'":F1:COMLIB"; 'COMMENT 1DECLARE ALL VARIABLES HERE; 1LIBRARY'-":F1 :ZLIB";
'BEGIN I
1COMMENT'THE MACROS ARE CALLED UP HERE; 'LIBRARY'":F1:VECLIB";
'COMMENT' ************************
'GOTO I START; BLOCK; INT75 ( VECT75); 'BEGIN I
START: BELL:=£H07; LINEF:=£HOA; DIGITL::£HOO; DIGITH::£HOO; KN:=2975.2;
IDATA::3500; TFREQ:=£H21; FDATA:=£H0820; CH1:=£H38; CH3:=£H3A; CH4:=£H3B; CH5:=£H3C; RSL:=1000/955; CRTRN::£HOD; EOLD:=O.O; EOLD2:=0.0; UOLD:=O.O; DATA::O; CFOUT:=70.0/2047.0; DPOS:=O; OFF: :0; FRD:=£H02; RVD: :£H03; PT::£H2E; PWMOF(OFF);
* INTIALIZE THE SYSTEM * ••••••••••••••••••••••••• •
(CALIBRATED FREQUENCY I/P TO THE MOTOR)
COMREG:=£HOF; CONTRL: =£H23; DATAL::£H16; CONTRL:=£H13; CONTRL::£HFF; TIMERO(TFREQ); COMSET; INTITM1; TIMSET(IDATA); 'COMMENT'
2 02
contro-[+1- ] ___ ..:.':, ller
+++++[ __ ] + +
inverter: .: ___ : driver __ :,M/G:
+ +
+++++++++++++++++++++++++++++++++++++++++++++++++;
· TEXT WRITE (" TEXT WRITE ( n
TEXT WRITE(" PRINT CHAR(BELL);
P.I.D POSITION CONTROL OF INDUCTION MOTOR*C*L"); =========================================*C*L*C*L");
DESIGNER: Z.M.ISMAIL 30/8/85*C*L*C*L*C*L");
TEXT WRITE("ENTRE P.I.D GAINS; PROPORTIONAL GAIN Kp:"); READ ECHO(DIGITH); DIGITH:=DIGITH-£H30; READ ECHO(DIGITL); DIGITL:=DIGITL-£H30; Kp::(DIGITH*10)+DIGITL;
CRLF; SPEDR(Kp,THOUS,HUNDR,TENS,UNIT); CRLF; FKp::Kp; R~AD CHAR (CRTRN); 'COMMENT'<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>; TEXT WRITE ( n DERIVATIVE GAIN Kd: n); READ ECHO ( D 1) ; 'IF' D1 = 'LITERAL' (.) 'THEN'
'BEGIN' READ ECHO(D2); D2:=D2-£H30; FD2:=D2/10.0; READ ECHO(D3); D3:=D3-£H30; FD3:=D3/100.0; READ ECHO(I2); I2:=I2-£H30; FI2:=I2/1000.0; READ ECHO(I1 ); I1 ::I1-£H30; FI1:=I1/10000.0; FKd:=FD2+FD3+FI2+FI1;
'END' 'ELSE'
'BEGIN'··
D1::D1-£H30; READ ECHO(D2); READ ECHO(D3); D3: =D3-£H30; FD3:=D3/10,0; FD1:=D1; FKd::FD1+FD3;
'END'; CRLF; RFLOAT ( FKd) ;
203
CRLF; 'COMMENT'<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>; TEXT WRITE(" INTEGRAL GAIN Ki="); READ ECHO(I1);
'IF' I 1 : 'LITERAL' (,) 'THEN' 'BEGIN'
READ ECHO ( I2) ; I2:=I2-£H30; FI2:=I2/10.0; READ ECHO(I3); I3:=I3-£H30; FI3:=I3/100.0; FK1:=FI2+FI3;
'END' 'ELSE'
'BEGIN' I1:=I1-£H30; READ ECHO ( I2) ; READ ECHO(I3); I3: =I3-£H30; FI3:=I3/10.0; FI1:=I1; FK1:=FI1+FI3;
,- 'END'; CRLF; RFLOAT(FKi); CRLF; 'COMMENT'<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>; TEXT WRITE("INPUT SAMPLING FREQUENCY SF="); READ ECHO(STH); STH : =STH -£H 30 ; READ ECHO(STL); STL:=STL-£H30; READ ECHO(STLL); 'IF' STLL=CRTRN 'THEN' ST::(STH*10)+STL
'ELSE' 'BEGIN'
STLL:=STLL-£H30; ST::(STH*100)+(STL*10)+STLL; CRLF; SPEDR(ST,THOUS,HUNDR,TENS,UNIT); CRLF; READ CHAR ( CR) ;
'END';
CRLF; FST:=ST; FST: :1,0/FST; RFLOAT(FST); CRLF;
204
FK1:=FKp+(FK1*(FST/2.0))+(FKd/FST)j RFLOAT (FK1); CRLF; FK2::(FK1*(FST/2,0))-FKp-(2.0*(FKd/FST)); RFLOAT(FK2); CRLF; FK3:=FKd/FST; RFLOAT(FK3); CRLF; READ CHAR(CRTRN); s 1: TEXT WRITE("WHAT I/P DO YOU WANT •• ? [1 or 2]"); CRLF; TEXT WRITE(" 1-RAMP I/P,. 2-STEP I/P,,"); CRLF; READ ECHO(INPUT); CRLF; 'IF' INPUT= 'LITERAL' (2)
'THEN' 'GOTO' W3; CRLF; 'COMMENT'::::::::::::::.FIRST CALCULATIONS FOR RAMP I/P,:::::::::::; PRINT CHAR(BELL)j ISTEP:=1; (STEP I/P ONEACH SAMPLE) DPOS: =DPOS+ISTEP; (DPOS: DEMANDED POSTION) SPEDR(DPOS,THOUS,HUNDR,TENS,UNIT); CRLF; 'COMMENT' •••••••••••••••••••
,. W3: CHAN::CH4; W1:
• ADC CALIBRATION • • ••••••••••••••••••• •
CONVERT(DATA,CHAN); SPEDR(DATA,THOUS,HUNDR,TENS,UNIT); 'IF' (UARTC 'MASK' £H02) = 0 'THEN' 'GOTO' W1; READ CHAR(CRTRN); CRLF; 'IF' CHAN <> CH3 'THEN'
'BEGIN' ADCZE:=DATA; CHAN: =CH3; 'GOTO' W1;
'END'; ADCFR:=DATA; TEXT WRITE (" : =ADCZE*C"); SETING(ADCZE,THOUS,HUNDR,TENS,CRTRN); CRLF; TEXT WRITE (" : :ADCFR *C") j SETING(ADCFR,THOUS,HUNDR,TENS,CRTRN)j
205
CRLF; 'COMMENT' ••••••••••••••••••••••••••••••••
* ZERO AUTOCALIBRATION FOR DAC * ••••••••••••••••••••••••••••••••• ,
TFREQ:=£H28; DATA:=O; CHAN::CH5; DATA 1: =DATA j W2: DATA: =DATA+l; WRTOUT(DATA); SETING(DATA1,THOUS,HUNDR,TENS,CRTRN); CONVERT(DATA1,CHAN);
·'IF' DATA1=£HOOOO 'THEN' 'GOTO' W2; CRLF; TEXT WRITE("ZERO OFFSETTING*C*L"); DACZE:=DATA-2; TEXT WRITE(" :=DACZE*C"); SETING(DACZE,THOUS,HUNDR,TENS,CRTRN); CRLF; 'COMMENT' *************************************
DATA:=£HOFFF; DATA1:=DATA; W4: DATA: :DATA-l j
* MAX. AUTOCALIBRATION FOR THE D/Aa * •••••••••••••••••••••••••••••••••••••• ,
WRTOUT(DATA); SETING(DATA1,THOUS,HUNDR,TENS,CRTRN); CONVERT(DATA1,CHAN); 'IF I DATA 1 = £HOFFF 'THEN I 'GOTO I W4;. CRLF; TEXT WRITE("MAXIMUM OFFSETING OF THE DAC*C*L"); DACFR:=DATA+lj TEXT WRITE(" :=DACFR*C"); SETING(DACFR,THOUS,HUNDR,TENS;CRTRN); CRLF; 'GOTO 'NXTP; 'COMMENT' ,,,,,,,,,,,TO THE CONTROL ALGORITHM PROGRAM ••••••••• ;
'END I j
'END I
'FINISH'
VECT75: 'BEGIN I
SAVE; STCONV ( CHAN); FL:=1; WRTOUT(J); RESTORE;
'END I j
206
'CORAL' W;
'COMMENT' THIS SECTION IS THE SUBMAIN PROGRAM FOR THE MANUAL TUNING OF THE PID CONTROLLER • FORMULLAS FOR THE CONTROL ALGORITHM ARE IMPLEMENTED HERE •
VERSION: V1.3 DATE: 20/12/85 AUTHOR: ZMI •••••••••••••• ' 1COMMENT 1ALL ABSOLUTE VALUES ARE DECLARED HERE; 'LIBRARY'":Fl:TTCABS"; 'COMMENT'THE COMMON COMMUNICATORS ARE CALLED UP HERE; 1LIBRARY'":Fl:COMLIB"; 'COMMENT'THE GLOBAL VARIABLES ARE DECLARED HERE; 1LIBRARY'":Fl:ZLIB"; 'BEGIN' 'COMMENT'VECTOR COMMANDS ARE DECLARED HERE; 'LIBRARY'":Fl:VECLIB"; NXTP: FDl::ADCFR-ADCZE; FD2: =FDl/2.0; (MID STROKE) Ma::FD2; FD1::4096.0/FD1; CHAN:=CHl; TEXT WRITE(" THE POSITION OF THE MOTOR SHOULD BE OOOO*C"); S5: CONVERT(DATA,CHAN); DATA:=DATA-ADCZE; (GET RID OF THE OFFSET) APOS:=DATA-Ma; 'IF' APOS < 0 'THEN' PWMON(FRD)
'ELSE' PWMON(RVD); S6:
CONVERT(DATA,CHAN); DATA::DATA-ADCZE; APOS:=DATA-Ma; 'IF' APOS ~ 0 'THEN' APOS:=-APOS; ENEW:=APOS; FOUT::l.l+(CFOUT*ENEW*FDl); PITCNT::KN/FOUT; TIMSET (PITCNT); FI3:=FI2; FI2: =Fil;. Fil :=APOS; . 'IF' APOS = FI3 'THEN' 'GOTO' S7; 'GOTO I S6;
S7: SPEDR(APOS,THOUS,HUNDR,TENS,UNIT); 1IF' (UARTC 'MASK' £H02):0 'THEN' 'GOT0 1 S5; READ CHAR(CRTRN); CRLF; READ CHAR(CRTRN); CRLF; APOS:=O;
207
'IF' INPUT='LITERAL' (2) 'THEN' 'BEGIN I
TEXT WRITE("INPUT DEMANDEDE STEP FROM (0-5) VOLTS.*C*L"); READ ECHO(STH); STH::STH-£H30; READ ECHO (STL); READ ECHO(STLL); STLL::STLL-£H30; Fil:=STH; FI2:=STLL; FI3:=FI1+(FI2/10.0); FI3:=(FI3*2047.0)/5.14;
. DPOS:=FI3; 'END I;
CRLF; TEXT WRITE("INPUT TFREQ*C*L"); READ ECHO(TENS); READ ECHO(UNIT); TFREQ::((TENS-£H30)*10)+(UNIT-£H30); CRLF; FD2:=APOS-ADCZE; (GET RID OF THE OFFSET) FD2: =FD2 *FD 1 ; FDPOS:=DPOS; ENEW:=FDPOS-FD2; RFLOAT(ENEW); CRLF;
'COMMENT':::::::::::·::::.::: .CONTROLLER FORMULAS.:::::::::::::::::::; FEOLD::FK2*EOLD; RFLOAT(FEOLD); CRLF; FEOLD2::FK3*EOLD2; RFLOAT(FEOLD2); CRLF; 1
FUOLD::UOLD+FEOLD+FEOLD2; RFLOAT(FUOLD); CRLF; . FUNEW:=FUOLD+(FKl*ENEW); RFLOAT(FUNE'II); CRLF; FOUT:=(FUNEW*CFOUT)+l.O; RFLOAT(FOUT); CRLF; PITCNT:=KN/FOUT; SPEDR(PITCNT,THOUS,HUNDR,TENS,UNIT); CRLF; FSAMPD:=384000.0*FST; SAMPD:=FSAMPD; RFLOAT(FSAMPD); CRLF; FL: :0; DACFR:=DACFR-DACZE; FI2:=DACFR; FDAC::4096.0/FI2; (GAIN OF THE DAC)
SPEDR(DACFR,THOUS,HUNDR,TENS,UNIT); CRLF; READ CHAR(CRTRN);
208
FD2::2048.0/FDAC; (GENERATE 5V) DRAT:=FD2; SPEDR(DRAT,THOUS,HUNDR,TENS,UNIT); CRLF; DACZE:=DACZE+DRAT; (OFFSETING THE 0/P OF THE DAC) WRTOUT(DACZE); SPEDR(DACZE,THOUS,HUNDR,TENS,UNIT); READ CHAR(CRTRN); CRLF; NEW: :FI3; SPEDR(NEW,THOUS,HUNDR,TENS,UNIT); CRLF; FI3:=FI3/FDAC; (STEP 0/P FROM THE DAC) DRAT:=FI3; SPEDR(DRAT,THOUS,HUNDR,TENS,UNIT); CRLF; DACZE: =DACZE+DRAT; (OFFSETING THE STEP) SPEDR(DACZE,THOUS,HUNDR,TENS,UNIT); PWMON (FRD); UOLD::FUNEW; TIMSET(PITCNT); WRTOUT (DACZE) ; CRLF; J::O; SAMPR ( SAMPD ) ; DEMASK;
'COMMENT'
FLl:=O; S3:
EOLD2::EOLD; EOLD:=ENEW;
•••••••••••••••••••••••••••••••• * NEW SAMPLE INPUT BY INT. 7.5 * ••••••••••••••••••••••••••••••••• '
'IF' INPUT= 'LITERAL'(2) 'THEN' 'GOTO' L2; DACZE:=DACZE+ISTEP; DPOS:=DPOS+ISTEP; WRTOUT(DACZE);
(GENERATES RAMP I/P TO )
'IF' DPOS > 2048 'THEN' DPOS:=2048; (5V MAX. ie. =F.B. V) 'GOTO I L2;
'IF' FL1=1 'THEN' 'BEGIN I
'IF' DPOS<=4 'THEN' DPOS::DPOS-ISTEP;
'END I
'ELSE I
DPOS:=DPOS+ISTEP;
L2:
FL 1: =0; -
FEOLD:=FK2*EOLD; FEOLD2:=FK3*EOLD2; FUOLD:=UOLD+FEOLD+FEOLD2;
(RAMP TYPE BUT WITH A) (DECELERATINGH THING) (AS ACONTINOUS RAMP)
(INPUT TO THE END OF THE ELSE STAT.)
209
WAIT: 'IF' FL=O 'THEN' 'GOTO' WAIT; (CHECKING FOR ACTIVE INT7.5) FL::O; WAIT2: . 'IF I DATAH > £H7F 'THEN I 'GOTO I WAIT2; RDATDC(DATA); (READ THE A/DC 0/P DATA) DATA:=DATA-ADCZE; APOS:=DATA-Ma; 'IF' APOS < 0 'THEN' APOS::-APOS; J:=J+1; 'IF' J > 2000 'THEN' 'GOTO' L3; SDD [J]: =APOS;
L3: FD2:=APOS; ENEW: :FD2*FD1; FUNEW::FUOLD+(FK1*ENEW); UOLD:=FUNEW; 'IF' FUNEW < 0,0 'THEN'
'BEGIN I
FUNEW:=-FUNEW; PWMOF(RVD);
'END I
'ELSE' PWMOF ( FRD) ;
FOUT:=(FUNEW*CFOUT)+1.0; PITCNT::KN/FOUT; 'IF' INPUT : 1LITERAL'(2) 'AND' PITCNT > 2000 'THEN'
TIMERO(TFREQ); TIMSET(PITCNT); 'IF' J > 10000 'THEN'
'BEGIN I
'CODE I 'BEGIN' DI SIZ1
'END I; 'GOTO I L4;
'END I; 'GOTO I 53;
1COMMENT':::::::::::STORED SAMPLES ARE SHOWED HERE:::::::::::::;
L4: COMSET; PRINT CHAR(BELL); CRLF; CRTRN:=32; K1: =0; 'FOR' K:=1 'STEP I 1 'UNTIL' 285 'DO'
'BEGIN I
CRLF; 'FOR' J::1 'STEP' 1 'UNTIL' 7 'DO'
'BEGIN I
K1:=K1+1; FDAC: =SDD [K1 ] ;
RFLOAT(FDAC); PRINT CHAR(CRTRN);
'END' 'END I;
. 'GOTO I S5; 'END I
'FINISH I
,.
210
211
'CORAL' B;
'COMMENT' THIS SECTION CONTAINS THE SETTING OF THE SYSTEM TO COMMUNICATE WITH THE OPERATOR BY ENTERING ALL THE VARIABLES NEEDED BY THE CAT CONTROL ALGORITHM FOR POSITION CONTROL OF THE ACTUATOR
VERSION: V1.1 DATE: 30/08/85 .AUTHOR: ZMI ......... I
1 COMMENT'ALL ABSOLUTE VALUES ARE DECLARED HERE; 'LIBRARY'":Fl:TTCABS"; 'COHHENT'THE COMMON COMMUNICATORS ARE CALLED UP HERE 'LIB.RARY 1 ":Fl: COMLIB"; 1COMMENT'DECLARE ALL COMMON VARIABLES HERE ; 'LIBRARY'":Fl:ZLIB";
'BEGIN I
1COMMENT'THE MACROS ARE CALLED UP HERE ; 'LIBRARY'":Fl:VECLIB";
1COMMENT'***1 ***'**11**'*''***************'*'**********''************** INTIALIZE THE SYSTEM;
'GOTO' START; BLOCK; INT75(VECT75); 'BEGIN' START:
BELL:=£H07; LINEF:=£HOA; DIGITL::£HOO; DIGITH:=£HOO; KN:=2975.2; FK1::0.2; FKp::l.Oj FKd:=O•O; IDATA:=3500; TFREQ: :£H21; FDATA:=£H0820; CH1: =£H38; CH3:=£H3A; CH4: :£H3B; CH5::£H3C; RSL:=l000/955; CRTRN: :£HOD; EOLD: :0,0; EOLD2:=0.0; UOLD::O.O; DATA:=O; CFOUT:=70.0/2047.0; DPOS:=O; OFF:=O; FRD:=£H02; RVD:=£H03; PT: :£H2E; PWMOF(OFF); COMSET; INTITH1; INTITH2;
(CALIBRATED FREQUENCY I/P TO THE.MOTOR)
TIMSET (!DATA); TIMER2(IDATA); 'COMMENT I
centre-[+/- ] ____ : ller
+++++[ __ ] + +
212
inverter: ___ : driver __ :M/G :
+ +
++++++++++++++++++++++++++++++++~+++++++++++++++;
TEXT WRITE(" P.I.D POSITION CONTROL OF INDUCTION MOTOR*C*L"); TEXT WRITE(" =========================================*C*L*C*L"); TEXT WRITE(" DESIGNER: . Z.M.ISMAIL 30/8/85*C*L*C*L*C*L"); PRINT CHAR(BELL); 'COMMENT'<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>;
TEXT WRITE("INPUT SAMPLING FREQUENCY SF="); READ ECHO(STH); STH:=STH-£H30; READ ECHO(STL); STL:=STL-£H30; READ ECHO(STLL);
'IF' STLL=CRTRN
CRLF; FST:=ST; FST: =1.0/FST; RFLOAT(FST); CRLF;
'THEN' ST:=(STH*10)+STL 'ELSE I
'BEGIN' STLL:=STLL-£H30; ST::(STH*100)+(STL*10)+STLL; CRLF; SPEDR(ST,THOUS,HUNDR,TENS,UNIT); CRLF; READ CHAR ( CR ) i
'END I i
'COMMENT'[][][][][][][][][][][][][][][][][][][][][][][][][][][][[][][][][]; FK1:=FKp+(FKi*(FST/2.0))+(FKd/FST); · RFLOAT(FK1); CRLF; FK2::(FKi*(FST/2.0))-FKp-(2.0*(FKd/FST)); RFLOAT(FK2); CRLF; FK3: =FKd/FST; RFLOAT(FK3); CRLF; READ CHAR(CRTRN);
s 1:
'COMMENT I •••••••••••••••••••• * A/Do CALIBRATION * •••••••••••••••••••••
W3: CHAN: =CH4;
W1: CONVERT(DATA,CHAN); SPEDR(DATA,THOUS 1 HUNDR,TENS,UNIT);
I
'IF' (UARTC 'MASK' £H02) = 0 'THEN' 1GOT0 1 W1; READ CHAR(CRTRN); CRLF;
'IF' CHAN <> CH3 'THEN' 'BEGIN I
DACZE:=DATA; CHAN:=CH3; 'GOTO I W1;
'END I; ADCFR::DATA; TEXT WRITE(" :=ADCZE*C"); SETING(ADCZE,THOUS,HUNDR,TENS,CRTRN); CRLF; TEXT WRITE(" :=ADCFR*C"); SETING(DACFR,THOUS,HUNDR,TENS,CRTRN); CRLF;
'COMMENT' *********************************
TFREQ:=£H28; DATA::O; CHAN: =CH5; DATA1:=DATA;
W2: DATA:=DATA+1;
* ZERO AUTOCALIBRATION FOR D/Ao * •••••••••••••••••••••••••••••••••• •
WRTOUT~DATA); SETING(DATA1,THOUS,HUNDR,TENS,CRTRN); CONVERT(DATA1,CHAN);
'IF' DATA1=£HOOOO 'THEN' 1GOTO' W2; CRLF; TEXT WRITE("DAC ZERO OFFSETTING*C*L"); DACZE:=DATA-2; TEXT WRITE(" :=DACZE*C"); SETING(DACZE,THOUS,HUNDR,TENS,CRTRN); CRLF;
'COMMENT' *************************************
DATA:=£HOFFF; DATA 1: =DATA;
W4: DATA: =DATA-1;
* MAX. AUTOCALIBRATION FOR THE D/Ao * •••••••••••••••••••••••••••••••••••••• •
WRTOUT(DATA); SETING(DATA1,THOUS,HUNDR,TENS,CRTRN); CONVERT(DATA1,CHAN);
'IF' DATAl = £HOFFF 'THEN' 'GOTO' W4;
214
CRLF; TEXT WRITE("DAC MAXIMUM OFFSETING *C*L"); DACFR:=DATA+l; TEXT WRITE(" :=DACFR*C"); SETING(DACFR,THOUS,HUNDR,TENS,CRTRN); CRLF; ' 'GOTO'NXTP; 'COMMENT'•••••••••••• TO THE CONTROL ALGORITHM ••••••••••••• ;
'END';
'END' 'FINISH'
VECT75: 'BEGIN'
SAVE; STCONV(CHAN); . FL:=l; WRTOUT(J); RESTORE;
'END'; .
215
'CORAL' UMAR;
'COMMENT' THIS SECTION IS THE SUBMAIN PROGRAM WHICH CONTAINS THE (CAT) ALGORITHM FOR SETTING THE 'RISE TIME', 'OVERSHOOT' AND THE SETTLING TIME'. VERSION: V1. 3 DATE: 20/12/85 AUTHOR: ZMI ............. 1 COMMENT 1ALL ABSOLUTE VALUES ARE DECLARED HERE; 1LIBRARY'":F1:TTCABS"; 'COMMENT'THE COMMON COMMUNICATORS ARE CALLED.UP HERE; 'LIBRARY'":F1:COMLIB"; 'COMMENT'THE GLOBAL VARIABLES ARE DECLARED HERE; 1LIBRARY 111 :F1:ZLIB";
'BEGIN I 'COMMENT'ALL VECTORS ARE DECLARED HERE;
'LIBRARY 1 ": F 1 : ,VECLIB"; NXTP: I1: =0; FI 1: =0. 01; NXTP1: CHAN: =CH1; RFLOAT(FKp); CRLF; RFLOAT(FK1); CRLF; CH4:=£H20; CRLF; CRLF; EOLD:=O.O; UOLD::O.O; EOLD2:=0.0; PWMON(£H03); RFLOAT(FI1); CRLF; FD1:=ADCFR~ADCZE;
FD2:=FD1/2.0; Ma:=FD2; FD1:=4096.0/FD1;
S5: CONVERT(DATA,CHAN); DATA:=DATA-ADCZE APOS:=DATA-Ma; 'IF' APOS < 0 'THEN' PWMON(FRD)
'ELSE' PWMON(RVD); RFLOAT(CFOUT); CRLF; RFLOAT(KN); CRLF;
S6: CONVERT(DATA,CHAN); DATA:=DATA-DACZE; APOS:=DATA-Ma; 'IF' APOS < 0 'THEN' APOS:=-APOS; ENEW: =APOS; FOUT::KN/(1.25+(CFOUT*ENEW*FD1));
PITCNT::FOUT; TIMSET(PITCNT);
216
'IF' PITCNT > 2375 'THEN' 'GOTO' S7; 'IF'(UARTC 'MASK' £H02) > 0 'THEN' 'GOTO' S7; 'GOTO' S6;
S7: SPEDR(APOS,THOUS,HUNDR,TENS,UNIT); CRLF; . . READ CHAR(CRTRN); FDPOS;=796.0*FD1
'COMMENT'•••••••••••• ·coNTROLLER FORMULLAS FKl::FKp+(FKi*(FST/2.0)); FK2:=(FKi*(FST/2.0))-FKp;
................ '
' COt-fi.!ENT ' •••••••••••••••••••••••••••••••••••••••••••••••••• ; TIMER0(32); TEXT WRITE("INPUT TFREQ*C*L"); READ ECHO(TENS); READ ECHO(UNIT); TFREQ::((TENS-£H30)*10)+(UNIT-£H30); CRLF; FD2: :APOS; ENEW::FDPOS-FD2; RFLOAT (ENEW) ; CRLF;
'COMMENT':::::::·::::::::: FEOLD:=FK2*EOLD; RFLOAT(FEOLD); CRLF; FUOLD:=UOLD+FEOLD; RFLOAT(FUOLD); CRLF; FUNEW::FUOLD+(FK1*ENEW); RFLOAT(FUNEW); CRLF; ,. FOUT:=(FUNEW*CFOUT)+l.O; RFLOAT (FOUT); CRLF;
CONTROLLER ACTION
PITCNT::KN/FOUT; SPEDR(PITCNT,THOUS,HUNDR,TENS,UNIT); CRLF; FSAMPD:=384000.0*FST; SAMPD:=FSAMPD; RFLOAT(FSAMPD); CRLF; FL: :0; DACFR:=DACFR-DACZE; FI2: =DACFR;
............... . . . . . . . . . . . . . . ,
FDAC:=4095.0/FI2; (GAIN OF THE DAC) SPEDR(DACFR,THOUS,HUNDR,TENS,UNIT); CRLF; READ CHAR(CRTRN); FD2:=2047.0/FDAC; (GENERATE 5V) DRAT::FD2; SPEDR(DRAT,THOUS,HUNDR,TENS,UNIT);
217
CRLF; DACZE:=DACZE+DRAT; (OFFSETING THE 0/P OF THE DAC) WRTOUT (DACZE); SPEDR(DACZE,THOUS,HUNDR,TENS,UNIT); READ CHAR(CRTRN); CRLF; NEW::FI3; SPEDR(NEW,THOUS,HUNDR,TENS,UNIT); CRLF; FI3:=FI3/FDAC; (STEP 0/P FROM THE DAC) DRAT: :FI3; SPEDR(DRAT,THOUS,HUNDR,TENS,UNIT); CRLF; DACZE:=DACZE+DRAT; (OFFSETING THE STEP) SPEDR(DACZE,THOUS,HUNDR,TENS,UNIT); CRLF; PWMON(FRD); UOLD:=FUNEW; READ CHAR(CRTRN); TIMSET ( P ITCNT) ; WRTOUT(DACZE); J: :0 j SAMPR (SAMPD) ; DEMASK;
'COMMENT' •••••••••••••••••••••••••••••••• * NEW SAMPLE INPUT BY INT. 7.5 * •••••••••••••••••••••••••••••••••
FL1::0; S3:
EOLD2::EOLD; EOLD:=ENEW;
L2: FUOLD:=UOLD+(EOLD*FK2)+(EOLD2*FK3); WAIT: 'IF' FL=O 'THEN' 'GOTO' WAIT; FL::O; WAIT2: 'IF' DATAH > £H7F 'THEN' 'GOTO' WAIT2;
'
RDATDC(DATA); (READ THE A/DC 0/P DATA) APOS::DATA-2047; 'IF' APOS < 0 'THEN' APOS:=-APOS; J::J+1; 'IF' J > 1500 'THEN' 'GOTO' L3; SDD(J]::PITCNT;
L3: ENEW::DPOS-APOS; FUNEW:=FUOLD+(FK1*ENEW); UOLD::FUNEW; 'IF' FUNEW < 0.0 'THEN'
'BEGIN' FUNEW::-FUNEW;
218
PWMOF(RVD); 'IF' I1=1 'THEN'
'BEGIN I
EOLD:=O.O; FK1: =5.0+FI1; FK2:=FI1-5.0; I1:=1;
'END I; 'END I
'ELSE I
PWMOF(FRD); FOUT:=KN/((FUNEW*CFOUT)+1.0); PITCNT:=FOUT; 'IF' INPUT = 1LITERAL 1 (2) 1AND 1 PITCNT > 2000 'THEN'
TIMSET(PITCNT); 'IF' J > 5000 'THEN'
'BEGIN I 'CODE I 'BEGIN I
DI SIZ1
'END I; 'GOTO I EXPR;
'END I; 'GOTO' S3;
EXPR: PWMOF(OFF); COMSET; PRINT CHAR(BELL); ENEW: =APOS; TIMERO(£H21); TEXT WRITE("POSITION= "); RFLOAT (ENEIJ); CRLF; 'GOTO'J1;
J1: READ ECHO (I 1) ; 'FOR' J::300 'STEP' 2 'UNTIL' 2000 'DO'
'BEGIN I
PRINT CHAR(CH4); 'IF 1 (UARTC 'MASK' £H02) > 0 'THEN' 'GOTO' W1; FOUT:=SDD[J]; RFLOAT(FOUT);
'END I;
W1: READ CHAR(CRTRN); CRLF;
TIMER 0 ( TFREQ ) ;
TEXT WRITE("SATISFIED WITH THE RESPONSE ••• ? (Y/N)*C*L"); 'FOR' RESPONSE:=CONSOLE CHAR 'WHILE' RESPONSE <> 'LITERAL'(Y)
'AND' RESPONSE <> 'LITERAL'(N) 1D0 1
'BEGIN I
PRINT CHAR(BELL);
219
CRLF; TEXT WRITE("Y OR N");
'END'; 'IF' RESPONSE = 'LITERAL'(Y) 'THEN' 'GOTO' FIN; TEXT WRITE("DO YOU WANT TO CHANGE THE SPEED ••• ? (Y/N)*C*L"); 'FOR' RISETM::CONSOLE CHAR 'WHILE' RISETM <> 'LITERAL'(Y)
'AND' RISETM <> 'LITERAL'(N) 'DO' 'BEGIN'
PRINT CHAR(BELL); CRLF; TEXT WRITE("Y OR N");
'END'; 'IF' RISETM : 'LITERAL'(N) 'THEN' 'GOTO' OVS;
'COMMENT':::::::::: ADJUSTING RISE TIME ::::::::::::; TEXT WRITE("WHAT SPEED DO YOU WANT.,,?*C*L"); TEXT WRITE("l= MUCH HIGHER*C*L"); TEXT WRITE("2= HIGHER*C*L"); TEXT WRITE("3= LOWER*C*L"); TEXT WRITE("4= MUCH LOWER*C*L"); 'FOR' RISETM::CONSOLE CHAR 'WHILE' RISETM <> 'LITERAL'(l)
'AND' RISETM <> 1LITERAL 1 (2) 'AND' RISETM <> 'LITERAL 1 (3) 'AND' RISETM <> 1LITERAL 1 (4) 'DO'
'BEGIN' PRINT CHAR(BELL); CRLF; TEXT WRITE("1,2,3 OR 4"); CRLF;
'END'; 'IF' RISETM = 'IF 1 RISETM = 'IF 1 RISETM = 'IF' RISETM =
OVS:
1 LITERAL 1 ( 1) 'LITERAL '(2) 'LITERAL' ( 3) 'LITERAL' (4)
'THEN' 'THEN' 'THEN' 'THEN 1
FKp::FKp+(FKp*0.8); FKp:=FKp+(FKp*0,25); FKp:=FKp-(FKp*0,15); FKp::FKp-(FKp*0,8);
TEXT WRITE~"DO YOU WANT TO CHANGE THE OVERSHOOT,,,? (Y/N)*C*L"); 'FOR' OVERSHOOT:=CONSOLE CHAR 'WHILE' OVERSHOOT <> 'LITERAL'(Y)
'AND' OVERSHOOT <> 'LITERAL'(N) 'DO' 'BEGIN'
PRINT CHAR(BELL); CRLF; TEXT WRITE("Y OR N"); CRLF;
'END 1 ;
'IF' OVERSHOOT = 'LITERAL'(N) 'THEN' 'GOTO' RST; 'COMMENT::::::::::::: ADJUSTING OVERSHOOT :::::::::::::; TEXT WRITE("WHAT OVERSHOOT DO YOU WANT ••• ?*C*L"); TEXT WRITE("l= MUCH BIGGER*C*L"); TEXT WRITE("2= BIGGER*C*L"); TEXT WRITE("3= SMALLER*C*L"); TEXT WRITE("4= MUCH SMALLER*C*L"); 'FOR' OVERSHOOT::CONSOLE CHAR 'WHILE' OVERSHOOT <> 1LITERAL 1 (1)
'AND' OVERSHOOT <> 'LITERAL'(2) 'AND' OVERSHOOT <> 'LITERAL'(3) 'AND' OVERSHOOT <> 'LITERAL'(4) 'DO'
'BEGIN' PRINT.CHAR(BELL);
CRLF; TEXT WRITE("1,2,3 OR 4"); CRLF;
'END I;
220
'IF' OVERSHOOT= 'LITERAL 1(1) 'AND' RISETM <> 1LITERAL 1 (N) 'THEN I
'BEGIN' 'IF' RISETM = 'LITERAL 1 (1) 'OR' RISETM = 'LITERAL 1(2)
'THEN' FK1:=FK1+(FK1*0.5)+(FKp*0.2) 'ELSE I FK1: =FK1+ (FK1 *0. 7);
'END I; 'IF' OVERSHOOT = 1LITERAL'(2) 'AND' RISETM <> 'LITERAL'(N)
'BEGIN' 'IF' RISETM = 'LITERAL'(1) 'OR' RISETM = 1LITERAL 1 (2)
'THEN' FK1:=FK1+(FK1*0.15)+(FKp*0.4) 'ELSE 1 .FK1:=FK1+(FK1*0.15);
'END I; 'IF' OVERSHOOT = 'LITERAL 1 (3) 'AND' RISETM <> 1LITERAL 1 (N) 'THEN' FK1:=FK1-(FK1*0.2); 'IF' OVERSHOOT = 'LITERAL'(4) 'AND' RISETM <> 'LITERAL'(N) 'THEN' FK1::FK1-(FK1*0.7);
'COMMENT'::::::::::: ADJUSTING SETTLING TIME:::::::::; RST: 'IF' RISETM = 'LITERAL 1(N) 'AND' OVERSHOOT <> 'LITERAL'(N)
'THEN I
.'BEGIN I 'IF' OVERSHOOT= 1LITERAL 1 (1) 'THEN'
'BEGIN' FK1:=FK1+(FK1*0.6); FKp:=FKp-(0.3*FK1);
'END I; 'IF' 9VERSHOOT = 'LITERAL 1 (2) 'THEN'
'BEGIN I FK1:=FK1+(FK1*0.1); FKp::FKp-(0.15*FK1);
'END I; 'IF' OVERSHOOT= 'LITERAL'(3) 'THEN' FKp:=FKp+(0.1*FK1); 'IF' OVERSHOOT = 1LITERAL'(4) 'THEN' FKp:=FKp+(FK1*0.3);
'END I; 'COMMENT ' ••••••••••• ·• • • • • ADJUSTING Kp- •••••• -: •••••••• ; 'IF' OVERSHOOT = 'LITERAL'(N) 'AND' RISETM <> 'LITERAL'(N)
'THEN' 'BEGIN I
'IF I RISETM = 'LITERAL 1 (1) 'THEN I FKi:=FK1+(0.4*FKp); 'IF' RISETM = 'LITERAL I (2) 'THEN I FK1:=FK1+(0.1*FKP); 'IF I RISETM = I LITERAL I ( 3 ) 'THEN I FKI:=FKI-(FKp*0.1); 'IF' RISETM = 'LITERAL' ( 4) 'THEN' FK1:=FK1-(FKP*0.4);
'END I; FIN: 'COMMENT'••••••••••••• ADJUSTING SETTLING TIME •••••••••• ;
·TEXT WRITE("DO YOU WANT TO SPEED UP THE SETTLING TIME •• ?*C*L"); 'FOR' SETLTM :=CONSOLE CHAR 'WHILE' SETLTM <> 'LITERAL'(N)
'THEN I
2·21
'AND' SETLTM <> 'LITERAL'(Y) 'DO' 'BEGIN'
PRINT CHAR(BELL); TEXT WRITE("Y OR N"); CRLF;
'END'; 'IF' SETLTM = 'LITERAL'(N) 'THEN' 'GOTO' NXTP1; 11:=1;
TEXT WRITE("WHAT SETTLING TIME DO YOU WANT •• ?1 C1 L"); TEXT WRITE("l= FASTER1 C1 L"); TEXT WRITE("2= MUCH FASTER*C*L"); TEXT WRITE("3= SLOWER*C*L"); TEXT WRITE("4= MUCH SLOWER*C*L");
'FOR' SETLTM :=CONSOLE CHAR 'WHILE' SETLTM <> 'LITERAL'(l) 'AND' SETLTM <> 1LITERAL'(2) 'AND' SETLTM <> 'LITERAL 1(3)
'BEGIN' PRINT CHAR(BELL); TEXT WRITE("1,2,3 OR 4"); CRLF;
'END'; FI2: =FI1;
'AND' SETLTM <> 'LITERAL'(4) 'DO'
'IF' SETLTM = 'LITERAL'(l) 'THEN' FI1:=FI1+(FI21 0.2); 'IF' SETLTM : 'LITERAL'(2) 'THEN' FI1::FI1+(FI2*0.4); 'IF' SETLTM = 'LITERAL'(3) 'THEN' FI1:=FI1-(FI21 0.15)
'GOTO' NXTP1; 'END'
'FINISH'
'ELSE' FI1:=FI1-(FI2*0.35);
222
'CORAL'MODCOM;
'COMMENT' THIS SECTION CONTAINS THE SET OF COMMUNICATION I/0 PROCEDURES USED IN THE DEVELOPMENT OF DIGITAL CONTROL ALGORITHMS. VERSION: V4.1 DATE: 12/11/84 AUTHOR: ZMI ••••••••• •
' 'COMMENT'ALL ABSOLUTE VALUES ARE DECLARED HERE; 'LIBRARY'":F1:TTCABS"; 'COMMENT' THE COMMON COMMUNICATORS ARE CALLED UP HERE; 'LIBRARY'":F1:COMLIB"; 'BEGIN' 'COMMENT' DECLARE ALL VARIABLES HERE;
'BYTE'DIGITH,DIGITL,X,Y,FD,LINEF,RETURN,L,CR,LF; 'INTEGER'J,I; 'FLOATING'FDE;
'COMMENT'************************************************************** YHE PROCEDURES STARTS HERE;
'COMMENT'============================================================== *** TEXT WRITE ***;
'COMMENT'THIS PROCEDURE WRITES UP THE MESSAGES TO THE OPERATOR; 'PROCEDURE'TEXT WRITE('VALUE''INTEGER'MESSAGE);
'BEGIN' 'BYTE'!; 'FOR'I:=1'STEP'1'UNTIL'[MESSAGE]'DO'PRINT CHAR([MESSAGE+I]);
'END'; 'COMMENT'==============================================================
*** PRINT CHAR ***; 'COMMENT'THIS PROCEDURE PRINTS OUT ONE CHARACTER ON THE VDU;
'PROCEDURE'PRINT CHAR('VALUE''BYTE'CHARO); 'BEGIN'
WAIT:'IF'UARTC'MASK''HEX'(04)=0'THEN''GOTO'WAIT; UARTD:=CHARO;
'END' ;1·
'COMMENT'============================================================== *** READ CHAR ***;
'COMMENT'THIS PROCEDURE READS ONE CHARECTAR FROM THE VDU OR KEY BOARD; 'PROCEDURE'READ CHAR('LOCATION''BYTE'CHARIN);
'BEGIN' WAIT1: 'IF'(UARTC'MASK''HEX'(02))=0'THEN''GOTO'WAIT1; CHARIN:=UARTD;
'END'; 'COMMENT'==============================================================
*"* CRLF *** 'COMMENT'THIS PROCEDURE RETURNS THE CONSOLE AND FEEDS LINE ;
'PROCEDURE'CRLF; 'BEGIN'
CR:=£HOD; LF:=£HOA; PRINT CHAR(LN); PRINT CHAR(CR);
'END';
223
'COMMENT'============================================================== *** CONSOLE CHAR ***;
'COMMENT'READS CHARACTER FROM THE CONSOLE; .'BYTE 1 'PROCEDURE 'CONSOLE CHAR;
'BEGIN 1
WAIT4: 'IF' (UARTC 1MASK"HEX'(02)):0 'THEN' 'GOTO' WAIT4; 'ANSWER'UARTD;
'END 1 ;
'COMMENT'============================================================== ••• READ ECHO ***;
'COMMENT'THIS PROCEDURE READ IN THE CHARECTAR AND PRINTS IT OUT BACK AGAIN TO THE OPERATOR ;
'PROCEDURE'READ ECHO('LOCATION''BYTE'CHARIN); 'BEGIN 1
WAIT2: 'IF' (UARTC 'MASK' 'HEX' (02) ):0 'THEN' 'GOTO 'WAIT2; CHARIN:=UARTD; WAIT3:'IF'(UARTC'MASK''HEX'(04))=0'THEN''GOTO'WAIT3; UARTD:=CHARIN;
'END'; 'COMMENT'==============================================================
*** CHEKUP ***; 'COMMENT'THIS PROCEDURE CHECKS TWO I/P CHARACTERS WHITH A CARRAGE
RETURN; 'PROCEDURE' CHEKUP('LOCATION''BYTE'HDIGIT,LDIGIT;
'VALUE''BYTE'CRTUR); 'BEGIN I
READ ECHO(HDIGIT); READ ECHO(LDIGIT); START: READ CHAR(CRTUR); 'IF' CRTUR = £HOD
'THEN' 1GOT0 1 OUT 'ELSE' 'GOTO' START;
OUT:. 'END';'
'COMMENT'============================================================== *** LIMIT ***;
'COMMENT'THIS PROCEDURE CHECKS THE RANGE OF TWO I/P CHARACTERS FOR SPEED LIMITATION OF THE MOTOR;
'PROCEDURE'LIMIT('LOCATION''BYTE'HDIGIT,LDIGIT,FD,TRUE); 'BEGIN'
LINEF:=£HOA; X:=LDIGIT-£H30; Y: =HDIGIT-£H30; FD:=Y*10+X; TRUE: :0; I IF ' FD > 70 I OR ' FD < 00
'THEN' 'BEGIN'
TRUE: =1; PRINT CHAR(LINEF);
224
TEXT WRITE("THIS SPEED IS OUT OF RANGE,TRY ANOTHER VALUE*C*L"); PRINT CHAR(LINEF);
'END 1 ;
'END I; 'COMMENT'==============================================================
*** RFLOAT ***; 'COMMENT' THIS PROCEDURE READS AFLOATING VALUE AND SETS IT TO THE VDU;.
1PROCEDURE'RFLOAT('VALUE''FLOATING'FDN); 'BEGIN I
'BYTE'PT,MRK; J: =0; PT: =£H2E; MRK: =£H2D; 'IF' FDN < 0.0
'THEN I
'BEGIN I
FDN:=-FDN; PRINT CHAR(MRK);
'END I; J::FDN; DISPLAY(J,DIGITH,DIGITL,X,Y,FD); FDE:=J; FDN:=FDN-FDE; PRINT CHAR(PT); 'FOR' I:=1 'STEP' 'UNTIL' 4 'DO 1
,.
'BEGIN' FDE:=FDN*10,0; J: =FDE; L:='BITS 1 [4,0]J; L:=L+£H30; PRINT CHAR(L); FDN:=J; FDN::FDE-FDN;
'END 1
'END'; 'COMMENT'***********************************************************;
'END I
'FINISH I
225
'CORAL'MODIB;
'COMMENT'THIS SECTION CONTAINS THE PROCEDURES REQUIRED TO PROGRAM THE INTERFACE BOARD AND SETTING THE COMMANDS FOR CONTROLLING THE MOTOR. VERSION: V2.2 DATE:11/11/84 AUTH: ZMI ••••••••; 'COMMENT'ALL ABSOLUTE VARIABLES ARE DECLARED HERE; 'LIBRARY'":F1:TTCABS"; 'COMMENT'THE COMMON COMMUNICATORS ARE DECLARED HERE; 'LIBRARY'":F1:COMLIB";
'BEGIN' 'BYTE'PICTL,PICTH;
'COMMENT'************************************************************** PROCEDURES START HERE;
'COMMENT'============================================================== *** PWMON. ***;
'COMMENT'THIS PROCEDURE SWITCHES ON THE "PWM" CONTROLLER AND SETS THE DIRECTION WHEN INITIALISING THE CONTROLLER;
'PROCEDURE'PWMON('VALUE''BYTE'DIRC); 'BEGIN'
COMREG:=£HOF; DATAL:=£HF2; CONTRL:=£H24; CONTRL:=£H04; CONTRL:=£H24; DATAL:=£H06; CONTRL::£H04; CONTRL: :£H24; DATAL:=DIRC; CONTRL::£H04; CONTRL:=£HFF;
'END'; ,. 'COMMENT'==============================================================
••• TIMER1 •••; 'COMMENT'THIS PROCEDURE WRITE DATA IN TIMER1 TO SET THE SPEED OF THE
MOTOR ; 'PROCEDURE' TIMER1('VALUE''BYTE'PICNTL,PICNTH);
'BEGIN' COMREG:=£HOF; CONTRL: :£H3D; CONTRL:=£H31; DATAL::PICNTL; CONTRL::£H11; CONTRL:=£H3D; DATAL:=PICNTH; CONTRL::£H31; CONTRL:=£H11; CONTRL:=£HFF;
'END';
226
'COMMENT'============================================================== *** INTITM1 ***;
1COMMENT'THIS PROCEDURE PROGRAMS TIMER1 AND IT HAS TO BE CALLED ONCE WHEN INITIALISING THE CONTROLLER;
1PROCEDURE 1INTITM1; 'BEGIN I
COMREG::£HOF; CONTRL: :£H23; DATAL:=£H76; CONTRL:=£H13; CONTRL:=£H3D; CONTRL:=£HFF;
'END I; 'COMMENT'==============================================================
*** TIMSET ***; 'COMMENT'THIS PROCEDURE FEEDS THE DATA TO TIMER1; LOW & .HIGH
BYTES; 'PROCEDURE'TIMSET('LOCATION''INTEGER'INCNT);
'BEGIN' PICTH:= 'BITS' [8,8] INCNT; PICTL:= 'BITS' [8,0] INCNT; TIMER1(PICTL,PICTH);
'END I; 'COMMENT'==============================================================
*** INTITMO ***; 1COMMENT'THIS PROCEDURE PROGRAMS TIMERO OF I.B. AND HAS TO BE CALLED
ONCE WHEN THE SYSTEM IS INTIALISED; 1PROCEDURE'INTITMO
'BEGIN I
COMREG:=£HOF; CONTRL:=£H23; DATAL::£H16; CONTRL:=£H13; CONTRL:=£HFF;
'END I; 'COMMENT'==============================================================
*** TIMERO ***; 1COMMENT'THIS PROCEDURE SELECTS PORTS A,B&C AS AN OUTPUT BPORTS
AND SETS THE TORQUE OF THE MOTOR; 1PROCEDURE 1TIMERO('VALUE''BYTE'TORQUE);
'BEGIN I
COMREG:=£HOF; DATAL:=TORQUE; (MODE SELECT) CONTRL:=£H30; CONTRL:=£H10; (WRITE) CONTRL::£H30; CONTRL:=£HFF;
'END I; 'COMMENT'==============================================================
*** PWMOF ***; 'COMMENT'THIS PROCEDURE SIWTCHES OFF THE "PWM" CONTROLLER;
1PROCEDURE 1PWMOF('VALUE''BYTE'CONDIT); 'BEGIN I
COMREG:=£HOF;
DATAL:=CONDIT; CONTRL:=£H24; CONTRL: =£H04; CONTRL:=£HFF;
'END';
227
(RESET PWM) (WRITE IN F .F.)
'COMMENT'=============================================================
'COMMENT'THIS PROCEDURE 'PROCEDURE'INTITM2;
'BEGIN 1
COMREG:=£HOF; CONTRL:=£H23; DATAL:=£HA6; CONTRL:=£H13; CONTRL:=£HFF;
'END';
*** INTITM2 n•; INTIALISE TIMER2 OF INTERFACING BOARD;
'COMMENT'============================================================== •n TIMER2 n•;
'COMMENT'THIS PROCEDURE PROGRAMS TIMER2 OF INTERFACING BOARD; . 1PROCEDURE'TIMER2('VALUE''INTEGER'DATAT2);
'BEGIN' COMREG::£HFF; DATAL:= 'BITS' [8,0] DATAT2; CONTRL:=£H32; CONTRL:=£H12; CONTRL:=£H32; DATAL:= 'BITS' [8,8] DATAT2; CONTRL:=£H12; CONTRL:=£HFF;
'END'; 'COMMENT'**•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••; 'END 1
'FINISH'
228
'CORAL'MODMR;
'COMMENT' THIS SEGMENT CONTAINS THE CONTROLLING THE SPEED OF THE MOTOR AT RESTRICTION LIMITS FOR OVER CURRENT PURPOSES;
VERSION: V2.2 DATE:11/11/84 AUTH: ZMI ......... '
'COMMENT'ALL ABSOLUTE VALUES ARE DECLARED HERE; 1LIBRARY 1 n:F1:TTCABSn; 1COMMENT 1ALL COMMON COMMUNICATORS ARE DECLARED HERE; 'LIBRARY'n:F1:COMLIBn; 'BEGIN' 1BYTE 1PICTL,PICTH;
'COMMENT'************************************************************** PROCEDURES START HERE;
'COMMENT'============================================================== •n DELAY1 .. *;
'COMMENT'THIS PROCEDURE IS DEFINED IN MACRO AND EXISTS A DELAY OF 800 mSec. TO THE CPU;
'PROCEDURE'DELAY; 'BEGIN'
n 'CODE 1 'BEGIN' LXI B,9FFFH ?LOOPO: DCX B MOV A,B ORA C JNZ ?LOOPO SIZ 9
'END';"; 'END'; .
'COMMENT'============================================================== . *** ACCELRT ***;
'COMMENT'THIS PROCEDURE SPEEDS UP THE MOTOR TO THE RATED FREQ. AT A RESTRICTED ACCELERATION;
'PROCEDURE'ACCEL('LOCATION''INTEGER'PICNT;'VALUE''INTEGER'MAXSPD); 'BEGIN 1
'INTEGER' I,F; PICNT:=1100; F:=10; LOOP4: 'IF' PICNT > MAXSPD
'THEN' 'BEGIN'
'IF' PICNT > 300 'THEN'
'BEGIN' TIMSET(PICNT); PICNT::PICNT-100; DELAY1; 'GOTO'LOOP4;
'END' 'ELSE'
'IF' PICNT > 200
,.
'THEN' 'BEGIN'
TIMSET(PICNT); PICNT:=PICNT-25; DELAY1; 'GOTO 'LOOP4;
'END' 'ELSE' 'IF' PICNT > 130
'THEN' 'BEGIN'
229
TIMSET ( PICNT); PICNT:=PICNT-12; DELAY1; 'GOTO'LOOP4;
'END' 'ELSE' 'BEGIN' 'IF' PICNT > 100 'THEN'
'BEGIN' F:=F+1; TIMSET(PICNT); PICNT::PICNT-1; 'FOR' I:=1 'STEP' 1 'UNTIL' F 'DO' DELAY1; 'GOTO' LOOP4;
'END' 'ELSE' ' 'BEGIN'
F:=F+1; TIMSET (PI CNT) ; PICNT:=PICNT-1; 'FOR' I::1 'STEP' 1 'UNTIL' F 'DO'
DELAY1; 'GOTO' LOOP4;
'END' 'END'
'END' 'END';
'COMMENT'============================================================== *** DECELRT ***• . ' . 'COMMENT'THIS PROCEDURE DECELARATES THE MOTOR TO THE DEMANDED FREQUENCY
WHITH ARESTRICTED LIMIT; 'PROCEDURE'DECCEL('LOCATION''INTEGER'PICNT;'VALUE''INTEGER'MINSPD;
'VALUE''BYTE'FRAC); 'BEGIN'
'INTEGER'!; 'BYTE 'F; F:=50; LOOP6:
230
'IF'PICNT < MINSPD 'THEN'
'BEGIN' 'IF' PICNT < 50
'THEN' 'BEGIN'
F:=F-t; TIMSET (PICNT); 'FOR' I:=1 'STEP' 1 'UNTIL' 45 'DO' DELAY1; PICNT: =PICNT+ 1 ; 'GOTO' LOOP6;
'END' 'ELSE'
,
'IF' PICNT < 58 'THEN'
'BEGIN' TIMSET (PICNT); 'FOR' I:=1 'STEP' 1 'UNTIL' 20 'DO' DELAY1; PICNT: =PICNT+ 1; 'GOTO'LOOP6;
'END' 'ELSE' 'IF' PICNT < 80
'THEN' 'BEGIN'
TIMSET ( PICNT) ; 'FOR' I:=1 'STEP' 1 'UNTIL' FRAC 'DO' DELAY1 j
PICNT::PICNT+1 j 'GOTO'LOOP6;
'END' 'ELSE' 'IF' PICNT < 100
'THEN' 'BEGIN'
TIMSET(PICNT); DELAY1; PICNT::PICNT+4; 'GOTO'LOOP6;
'END' 'ELSE' 'IF' PICNT < 130
'THEN' 'BEGIN'
TIMSET(PICNT); DELAY1; PICNT:=PICNT+15; 'GOTO' LOOP6;
'END' 'ELSE' 'IF ' PICNT < 200
'THEN' 'BEGIN'
TIMSET(PICNT); PICNT::PICNT+35;
DELAY1; 'GOTO' LOOP6;
'END' 'ELSE'
2 31
'IF' PICNT < 330 'THEN'
'END' 'END';
'BEGIN' TIMSET(PICNT); PICNT:=PICNT+75; 'GOTO' LOOP6;
'END' 'ELSE'
'BEGIN' TIMSET(PICNT); PICNT:=PICNT+200;
'END'
'COMMENT'============================================================== *** MOV •••;
'COMMENT'THIS PROCEDURE COMPRISES OF A LOOK-UP TABLE TO ACCELERATES THE MOTOR AT ARATE OF 3Hz;
'PROCEDURE' MOVE('LOCATION''INTEGER'TIMD;'VALUE''INTEGER'SPDMX); 'BEGIN' 'IF' TIMD > SPDMX
'THEN' 'BEGIN' 'IF' TIMD > 497
'THEN' 'BEGIN'
TIMD: :496; 'GOTO' STAR;
'END' 'ELSE' 'IF' TIMD > 331
'THEN' 'BEGIN'
TIMD:=330; 'GOTO' STAR;
'END' 'ELSE' 'IF' TIMD >249
'THEN' 'BEGIN'
TIMD:=248; 'GOTO' STAR;
'END' 'ELSE' 'IF' TIMD > 199
'THEN' 'BEGIN'
TIMD:=198; 'GOTO' STAR;
'END'
2 32
'ELSE I
STAR: 'END I;
'IF I TIMD > 166 'THEN I
'BEGIN' TIMD: :165; 1GOTO' STAR;
'END I
'ELSE I
'IF' TIMD > 124 'THEN I
'BEGIN' TIMD:=TIMD-24; 'GOTO 1 STAR;
'END I
'ELSE I
'IF I TIMD > 99 'THEN I
'BEGIN I
TIMD: =TIMD-1 2 ; 1GOTO' STAR;
'END I
'ELSE' 'IF I TIMD > 81
'THEN I
'END I;
'BEGIN I
TIMD:=TIMD-9; 'GOTO' STAR;
'END I
'ELSE I
1IF 1 TIMD > 70 'THEN I
'BEGIN I
TIMD:=TIMD-6; 'GOT0 1 STAR;
'END I
'ELSE I
1IF 1 TIMD > 58 'THEN I
'BEGIN I TIMD:=TIMD-4; 'GOTO' STAR;
'END I 'ELSE' 'IF I TIMD > 42
'THEN' 'BEGIN'
TIMD:=TIMD-3; 'GOTO' STAR;
'END I .
'ELSE' TIMD:=42;
2 33
'COMMENT'============================================================== *** BRAKE *11
; 'COMMENT' THIS PROCEDURE ~KES THE MOTOR DECEL. PROPORTIONAL TO THE
ERRORE AT A RATED FREQUENCY OF 3Hz; 'PROCEDURE' BRAKE('LOCATION''INTEGER'TIMD;'VALUE''INTEGER'SPDMN);
'BEGIN' 'IF' TIMD < SPDMN
'THEN' 'BEGIN'
'IF' TIMD < 58 'THEN'
'BEGIN' TIMD:=TIMD+3; 'GOTO' JAN;
'END' 'ELSE' 'IF' TIMD < 70
'THEN' 'BEGIN'
TIMD::TIMD+4; 'GOTO' JAN;
'END' 'ELSE' 'IF' TIMD < 82
'THEN' 'BEGIN'
TIMD: =TIMD+6 ; 'GOTO' JAN;
'END' 'ELSE' 'IF' TIMD < 99
'THEN' 'BEGIN'
TIMD::TIMD+9; 'GOTO' JAN;
'END' 'ELSE' 'IF' TIMD < 124
'THEN' 'BEGIN'
TIMD: =TIMD+ 12; 'GOTO' JAN;
'END' 'ELSE' 'IF' TIMD < 165
'THEN' 'BEGIN'
TIMD::TIMD+24; 'GOTO' JAN;
'END' 'ELSE'
,
JAN: 'END I j
234
'IF' TIMD < 197 'THEN I
'BEGIN I
TIMD:=198; 1GOT0 1 JAN;
'END I
'ELSE I
'IF' TIMD < 247 'THEN I
'BEGIN I
TIMD:=248; 'GOTO' JAN;
'END I
'ELSE I
'END I j
'IF' TIMD < 329 'THEN I
'BEGIN I
TIMD:=330; 1GOT0' JAN;
'END I
'ELSE I
'IF' TIMD < 495 'THEN'
'BEGIN' TIMD:=496; 'GOTO' JAN;
'END I
'ELSE I
'IF' TIMD < 991 'THEN I
'BEGIN I
TIMD: =992; 'GOTO I JAN;
'END I
'ELSE I
TIMD:=2970;
'COMMENT'*************************************************************; 'END I
'FINISH I
2 35
'CORAL'MODIN;
'COMMENT'THIS SECTION INITIALISE THE SYSTEM AFTER SWITCHING ON THE POWER SUPPLY VERSION 2:5 DATE 12/11/84 AUTH: ZMI *******; 'COMMENT'ALL ABSOLUTE VALUES ARE DECLARED HERE; 'LIBRARY'":F1:TTCABS"; 'COMMENT'THE COMMON COMMUNICATOR IS DEFINED HERE; 'LIBRARY'":F1:COMLIB";
'BEGIN' 'BYTE'TIM1,CHAN,CR,LF; 'INTEGER'DATAT2;
'COMMENT'11111111*****111********1111*1 *1111********1 *111****** PROCEDURES STARTS HERE;
'COMMENT'===================================================== tu SETURT ***;
'COMMENT'THIS PROCEDURE SETS THE SERIAL COMMUNICATION "UART" CHIP AND THE BAUD RATE;
'PROCEDURE'COMSET; 'BEGIN'
TIM1L:=£H50; TIM1H::£H40; COMREG::£HCC; UARTC:=£HOO; UARTC::£HOO; UARTC::£HOO; UARTC:=£H40; UARTC::£H7A; UARTC:=£H15;
(LOW DATA TO TIMER1) (HIGH DATA TO TIMER1)
(RESET THE CHIP)
'END'; 'COMMENT'==============================================================
Ill RDATD *11;
'COMMENT' THIS PROCEDURE READS DATA FROM THE AID CONVERTER; 'PROCEDURE'RDATDC('LOCATION''INTEGER'DATA);
'BEGIN' COMREG:=£HOC; 'BITS' [8,0] DATA :=DATAL; 'BITS' [4,8] DATA ::DATAH;
'END'; 'COMMENT'==============================================================
Ill SAMPR "*; 'COMMENT' THIS PROCEDURE PROGRAMS THE I/P __ O/P PORT (IPP) TIMER
'0 FOR INT. SERVICE ROUTEEN; 'PROCEDURE'SAMPR('VALUE''INTEGER'SAMPD);
'BEGIN' TIM1:= 'BITS' [8,8] SAMPD; TIM1H:=TIM1+£HCO; TIM1L:: 'BITS' [8,0] SAMPD; COMREG: :£HCC;
'END';
236
'COMMENT'============================================================== *** STCONV n•;
'COMMENT' THIS PROCEDURE INHIBITS THE A/DC AND STARTS CONVERTION; 'PROCEDURE'STCONV('VALUE''BYTE'CHAN);
'BEGIN' COMREG::£HOC; CONTRL::CHAN; CONTRL:=CHAN-£H20; CONTRL:=CHAN; CONTRL:=CHAN-£H10;
'END'; 'COMMENT'=============================================================
*** PWMOF ***; 'COMMENT'THIS PROCEDURE SWITCHES OFF THE PWM CONTROLLER;
'PROCEDURE'PWMOF('VALUE''BYTE'CONDT); 'BEGIN'
COMREG:=£HOF; DATAL:=CONDIT; CONTRL::£H24; CONTRL:=£H04; CONTRL:=£HFF;
'END'; 'COMMENT'**************************************************************; 'END' 'FINISH'
237
1CORAL 1MODIO;
1 COMMENT'THIS SEGMENT COMPRISES OF PROCEDURES USED TO. DEAL WHITH THE ANALOG I/P & 0/P SECTIONS
VERTION: V 1.2 ATE 19/12/84 AUTH:ZMI ••••••••• I .
'COMMENT'THE ABSOLUTE COMMUNICATORS ARE DEFINED HERE 1LIBRARY'":F1:TTCABS"; 1COMMENT 1THE COMMON COMMUNICATOR IS DEFINED HERE; 1LIBRARY'":F1:COMLIB";
'BEGIN I
'COMMENT'CH1=38,CH2=39,CH3=3A,CH4=3B,CH5=3C,CH6=3D; 'COMMENT'11111111111111111111111111111111111111111111111111111111111111
THE PROCEDURES STARTS HERE; 'COMMENT'==============================================================
nt SETING **1 ;
'COMMENT'THIS PROCEDURE CONVERTS 12 BIT DATA.TO HEXADECIMAL DATA TO PRESENT IT ON THE VDU;
1PROCEDURE'SETING( 1LOCATION''INTEGER 1ADCOUT; 1LOCATION''BYTE 1SET1,SET2, SET3 1 CRTURN) ;
'BEGIN' SET1:= 'BITS' [4,0] ADCOUT; SET2:: 'BITS' [4,4] ADCOUT; SET3:= 'BITS' [4,8] ADCOUT; 'IF' SET1 >= £HOA 'THEN' SET1::SET1+£H37
'ELSE' SET1::SET1+£H30; 'IF' SET2 >= £HOA 'THEN' SET2:=SET2+£H37
'ELSE' SET2::SET2+£H30; 'IF' SET3 >= £HOA 'THEN' SET3::SET3+£H37
'ELSE' SET3:=SET3+£H30; PRINT CHAR(SET3); PRINT CHAR(SET2); PRINT CHAR(SET1); PRINT CHAR(CRTURN);
'END I; ,. 'COMMENT'==============================================================
ttt CONVERT 111 ; 1 COMMENT 1THIS PROCEDURE INHIBITS THE ADC AND WAIT TO READ THE CONVERTED
DATA; 'PROCEDURE'CONVERT('LOCATION''INTEGER'ANALOG;
'VALUE''BYTE'CHANEL);
'BEGIN I
COMREG::£HOC; CONTRL:=£HFF; CONTRL:=CHANEL; CONTRL::CHANEL-£H20; CONTRL:=CHANEL; CONTRL:=CHANEL-£H10; CHECK:'IF' DATAH > £H7F 'THEN' 'GOTO' CHECK; 'BITS' [8,0] ANALOG:=DATAL; 'BITS' [4,8] ANALOG:=DATAH; CONTRL::£HFF; COMREG::£HOF;
23 8
'COMMENT'============================================================== *** WRITEOUT ***;
'COMMENT'THIS PROCEDURE OUTPUTS A 12 BIT VALUE TO AD7542 NIBBLE MOD DAC; 'PROCEDURE'WRTOUT('LOCATION''INTEGER'DAC1IN);
'BEGIN' DAC1LO: = 'BITS' DAC 1MI: = 'BITS' DAC1HI:: 'BITS' DAC1LD:: £HFF;
'END';
[4,0] [4,4] [4,8]
DAC1IN; DAC1IN; DAC1IN;
COMMENT'============================================================== *** WRITEOUT2 ***;
'COMMENT'THIS PROCEDURE OUTPUTS A 12 BIT VALUE.TO AD7542 NIBBLE MOD DAC2; 'PROCEDURE'WRTOUT2('LOCATION''INTEGER'DAC2IN);
'BEGIN' DAC2LO:: 'BITS' DAC2MI:= 'BITS' DAC2HI: = · 'BITS' DAC2LD:= £HFF;
'END';
[4,0] [4,4] [4,8]
DAC2IN; DAC2IN; DAC2IN;
'COMMENT'============================================================== *** SPEDR ***;
1COMMENT'THIS PROCEDURE READS DATA & CONVERTS FROM BINARY TO BCD; 'PROCEDURE'SPEDR( 1VALUE 11 INTEGER'ADCO;
1LOCATION''BYTE'UNIT1,UNIT2,UNIT3,UNIT4); 'BEGIN I
'BYTE'CRTRN; 1INTEGER'Z1,Z3,Z4,Z5,Z6,Z7,Z8; CRTRN:=£HOD; 'BITS' [4,12] ADCO ::0; Z1:=ADC0/1000; Z3:=ADCO-(Z1*1000); Z4:=Z3/100; Z5:=Z3-(Z4*100); Z6:=j!:5/10; Z7:=Z5-(Z6*10); Z8: =Z7/1; UNIT1:= 'BITS' [4,0] Z8; UNIT2:= 'BITS' [4,0] Z6; UNIT3:= 'BITS' [4,0] Z4; UNIT4: = 'BITS I [4,0] Z1; UNIT1:=UNIT1+£H30; UNIT2:=UNIT2+£H30; UNIT3:=UNIT3+£H30; UNIT4::UNIT4+£H30; PRINT CHAR(UNIT4); PRINT CHAR(UNIT3); PRINT CHAR(UNIT2); PRINT CHAR(UNIT1); PRINT CHAR(CRTRN);
'END I ;
239
'COMMENT'============================================================== *** DISPLAY ***;
1COMMENT 1THIS PROCEDURE CONVERTS THE INTEGER BINARY INTO B,C.D.; 'PROCEDURE' DISPLAY('VALUE''INTEGER'INUMB;
'LOCATION''BYTE'PARM1,PARM2,PARM3 1 PARM4,PARM5); 'BEGIN I
1BYTE 1CRTRN; 1INTEGER 1V1,V2,V3,V4,V5,V6,V7,V8; CRTRN:=£HOD; V1:=INUMB/10000; V2:=INUMB-(V1*10000); V3:=(V2/1000); V4:=V2-(V3*1000); V5::V4/100; V6::V4-(V5*100); V7:=V6/10; V8::V6-(V7*10); PARM1:: 'BITS' [4,0] VB; PARM2:= 'BITS' [4,0] V7; PARM3:= 'BITS' [4,0] V5; PARM4:: 'BITS' [4,0] V3; PARM5: = 'BITS' [4,0] V1; PARM1:=PARM1+£H30; PARM2::PARM2+£H30; PARM3:=PARM3+£H30; PARM4::PARM4+£H30; PARM5:=PARM5+£H30; PRINT CHAR(PARM5); PRINT CHAR(PARM4); PRINT CHAR(PARM3); PRINT CHAR(PARM2); PRINT CHAR(PARM1);
'END I; 'COMMENT'*************************************************************; 'END' ,-'FINISH I
•
- APPENDIX C -
Computer Simulation
240
APPENDIX C
Computer Simulation
The digital simulation formulas for the PID controller are derived
from the equations given in section 5.4 equation, where the model as it was
defined as an integrator, gives the transfer function below:
G(s) = Y(s) U(s) =
K s (C. 1)
where K is the plant gain, Y(s) is the output and U(s) is the input signal to
the plant. Figure C.1 shows the transfer function of the controller which
is inserted in series to the plant. The error produced from the set point
and the actual value of the position is multiplied by the controller transfer
function to form the signal applied to the plant. The transfer function·of
the controller is given by:
D(s) =
,. U(s) E (s)
where E(s) is the input error to the controller.
(C.2)
Using the bilinear transformation method, the z-transform of the
model (Figure C.2) is given by:
xi& G(z) = u(z) = .!*K* 2
(l+z-1) -1
(1-z )
where T is the sampling time, and U(z) = D(z) e(z)
!. * ( ) T -1 -1 Y(z) = 2 K * u z + 2 * K * u(z) * z + y(z)*z
(C.3)
(C.4)
241
Equation C.4 can also be written in the sampled time form leads to,
(C.5)
where n represents the present sample at time t.
Un(t) is the output signal applied to the model after being calculated from
equation 5.10 which it is
(C.6)
Figures C.3- C.17 represents the behaviour of the plant at variable
amounts of PID gains, where the K of the model is fixed at 0.2. ·
,.
242
E (s) O(s) U(s) G<s>=K Y<
s s)
Fi g.<C.1) s-0 am a in . T. F.
e (z) O(z) · u(z) TK <1 +t1) y( -
2 <1-z> z)
,
Fig.<C.2) z-Domain T.F.
·.
I PI Controller
I. 10 ~
I .00 l<p =I
0.'30.
n. 0.80' ' 0. 0. 70: "' (j)
0.60
0' 50:
0.40.
0' 30:
0.20.
0.10:
O.QO:,, .. , .... , ... ,, .... , .... , .... , .... ,,,,,,,.., ... ,,,,.,, .... , .... , .... , .... , .... , .... , .... , .... , .... , ... ,, .. ,,,,, .. ,,.,,,·,,., ..... , .... ,,,,,""'"''' 0 2 4 6 8 10 12 14 16 18 20 22 24 '26 28 130
I ime Sec.
Fig(C.3)Slep response lesl for a unily gain (ST=0.02 mSec.).
a.. .....
c.. ., (f)
I. 10
I .00
0.90
0.8
0.70
0.60
0.50
0.40
0.30
0.20
0. !0
0.00 0 2
244
'/-~~:::::~:~;=~__.;;~:::~~~:==~-i=='···~· _.....--=-"":t.Kp = I
.. 4 6 8
(P) Controller
10 12 \'4 16 I ' ' • . • ' • • ' ' • . ' . • ' '
18 20 22 24 26 28
f ime Sec.
v'<o '2 . +t<p:: ~
><t<p=4 Dt<o';=.
30
Fig.( C. 4) S I e p res~ on se I e s I ( s amp t i n g I i me = 20 mS e c . ) .
( Pl Controller I!P
... , 9 12 15 18 21 24 27 30
f ime Sec.
Fig.(C.S).Ramp response test (sampling lime= 20 mSec.).
I .20 (PI) Controller
I. 10
1.00. l<p·l l<i".2
0.90. (l_ ..._
0.80~ a. Q) --lll 0. 70.
0.60.
0.50
0. t!O~
0.30
0. 20~
0.10
• Q .00: 111111111111 , 1 :;; 1 , 1 , 1 • 11111 , 1,,,,,,,,, 1 ,, ··''''1''''''''·1''''·''''1''·'''''·1' ·'''·'·!·•·•·•· ·I
0 6 12 18 2tl 30 36 t12 t!B 5tl 60
I ime Sec.
Fig.f[.6)Siep response lesl IPI conlroller ST"20 mSec.l.
u. '·
1 ··c . ) ]
I 21 I . I .:,J
1 . cc,] (\ . '\ :j
1- :j 0 evj \J. 7d 0. o(.J
1 (\ :>0.,
0. 40.1 0. 30:!
~·-~.
vPID A PI
Ki=0.3 ~=0.3
~=1.0
l'""l' "'l"'"'f'l ffi'JTII"IfiiTrflTIITT1Trf1TrTI"fiTI FI"I"T(riTip1 f1111 nrnrlfiH'f' ~"~'l•·n 1f1"11 'I '"'1''' '1~'~ 1 •1••n-;n• 1 1\ 1111TTI 1 p1 l'fj '' HfiTl t'1
2 4 6 8 IQ 12 14 16 !8 20 ~~ ~4 2o 2b 3C I imc
Fig.(C.7)Siep response tesl (sampling !ime '20 rnSec 1.
0.. ... 0. .. -"'
0.. ... -0.
• "'
" 1.50
1.40
I .30
1.20
I. IQ
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.0 0 2 4 6 8 10 12
Fig.(tB) SI ep response I es I
! . 50
1.4p
1.30
! . 20
! . IQ
1.00
0.90
a 80
0 7Q
0.60
a. so
0.40
0. 30
o.zo
a. 10
0.00
247
{PI) Controller
" Ki=O.S V J<i:1.Q + Ki=1.5 • Ki=2.0
I)J=1.0 c Ki=2.5
14 16 18 20 22 24 26 28 30 I ime Sec.
(sampling I ime • 20 mSec.)
I \ I
\ "
{PI) Controller
"Ki=O.S V Ki=1.0 + Ki=1.5 • Ki=2.0 cKi=2.5
0 2 3 4 5 6 7 8 9 10 11 12 13 14 !5 I ;me
FiglC.9) Sleo •esoonse lest rsompl ing I ime • 20 mSec l
I
ll. ,. -Q.
• <J'
ll.
' -Q.
• -<J'
!
I. j(1
tj 1. !C:l
l I ' .. ooi
' C.1C.:
i 0 se.:
l 0 ?d
' 1
0 603 . . 0 5G~
i 0 ~d
l . c ;o;
. c 20J .
l 0 tQ;
l
c CO 0
' ! I
I I
248
( PII Controller
Kp = 2.0
• Ki:QS V Ki :1.0 + Ki =1.5 X Ki :2.0 cKi=25
i T· 6 e , o 'z '4 ·i o i a ·z.c · zz · 2~ 26 zs 3o
';.,..e Sec.
Fig.((.10) Step resoonse lest (somot ing I ime • 20 mSec. l
I '3C' 1
' I .2C.1
' , I . I ('i I oci /
' l c :;C:.
' l 0 oO.:
0 70 oKi:O.S
l V Ki:I.O +Ki=1.5 0 ov.: X J<i :2,0
c 'OJ cKi=25 --c 40j '
Kp=2.0
' :I r ;o.:
i...~-~-.,---~-~.,__.,.......-:""""'...,....~r·-.'O"T.,....,..,..-~....,.:- ....... -·..-•~ 2 3 4 5 6 7 8 1 I\) JJ 12 13 14 15
t p·ne Sec.
Fig.(C.11) Step re•oonse test (sampling time • 20 mSec l.
Q.
' a. u
"'
,. Q.
' -a. u
"'
249
fl I .30
I .20
I. I
I .00 ~~~~~~~?==*~~~~-~--~~•'Ki•.5 0.90 i
i
t 0.80
0.70
••·.: • • I
+I<< •. I '5
0.60 l 1),=3.0
0.50
0.40
0.30
0.20
0. IQ
0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 130
Hme Sec.
Fig.IC.12l Step response test (sampling time = 20 mSec. ).
I. 30
1.20
I. 10
I .00
0.90
0.80
0. 70
0 60
0.50
0 40
0. 30
0 20
0.10
0.0 0
Ki • .5 vKi =1 + Ki =1.5 ><Ki =2 oKi =25
2 3 4 5 6 1 e 9 10 11 12 13 14 15
I ime Sec.
Fig(C.13l Step response test (sampt ing time • 20 mSec.).
I, 2C_
~ I I .2t
I
I. !C; I
250
(PIJ Control!er
~ !.c • .:
'
0..
' " • ;
0 7('~ .
r :;~("~
\ . :o.:
C 4C;
. G I(~
• Ki=O.S • Ki=1.0 + Ki =1.5 X l(j :2.0 cKi =25
Fig.(C.14) S t eo r e ~ 0 on se t e s t ( s amp I i n g t i me • 20 mS e c . ) .
I
I . ~C'.l
' . ::r.: • ,, I
,,.: ,_
I . eo.: l
r ;
:::11..! ' ' c C(·~ l
c· ,, r ;o:
" :c:
c L • .v_ .
;J 3C: • G zc~
J c 1 .... ,;:
c OG. 0
Kp=4.0
' i rn"!
• Ki=O.S • Ki=1.0 +Ki=1.5 X Ki:2.Q cKi=2.5
Sec.
Fig!C.15) Step r e~ponse test ( samp I i ng time • 20 'l15ec ) .
Q.
' " < -
I 3C_
l 1.~
I 1,,:
. I ( (...:
. r x3
2 51
(PI) Controller
'.!" c r.:c.:
0:..
' -" ! "'
I
.
G 7C,;: • .
( ·De ' !
c 51.5 .
0 .:l(..~ . • c 3C.:
l G 2C'.:
l 0 IQ"
0 oc. 0
Kp=S.O
2 ' ; fr'!
4 Ki=O.S • Ki:1.0 + Ki=1.5 X l(j :2.0 cKi=ZS
Sec.
Fig.(C.16) Step •esoonse lest (sompl ing time • 20 mSec.l.
3C_
' .. ,J.: ~·
' 1(1
' . ("(,,;
0 ~c.:
c 6C;
l r·. 7
c Q(J~
c SC'.: . .
0 40.:! . . c ;c3
: ?:V.:
l c 10·
0 OC 0
(PI) Controller
4 Ki=QS • Ki=1.0 + Ki=1.5 X l(i:2.Q cKi=2.5
--:-> .... _., . .,.._,...-:-~·-~-~---:----r---.---:--.,-..... ~ ...... ~.,.._,..........,.,....,..__,.... I 2 ) 4 5 0 7 8 ~ ;Q 11 1?.. 13 14 1!1
'!me Sec.
Fig.(C.17) Step response lest (sompl ing time • 20 mSec.l.
--------------------------......... 252
pr zt1 .fortran
zt1 .fortran 05/06/86 0956.1 bst Tue
c Kp,Ki,Kd are the PID gains c K1 ,K2,K3 are the parameters of the controller c ST sampling time c U signal 0/P from the controller c Y position 0/P c *********************************** c c
DOUBLE PRECISION X,Y,T,ST,Kp,Kd,Ki,K1,K2,K3,E,U,K,FOUT DIMENSION XI60031,YI60031,TI6003J,EI6003J,UI60031 OPENIUNIT= 6,FILE= '21' ,FORM= 'FORMATTED' I PRINT 1 FORMAT ('ENTER SAMPLING TIME ..• ?' I READ *,ST PRINT 2
2 FORMAT I'ENTER NO OF POINTS ... ?' I READ •,M PRINT 3
3. FORMAT I'ENTER GAIN Kp,Ki,Kd,K= •.. ?'I READ *,Kp,Ki,Kd,K PRINT 4
4 FORMATI'ENTER STEP I/P' I READ * , INPUT
DO 22 J=1,3 XIJl=O.O YIJl=O.O UCJI=O.O EIJJ=O.O TIJJ=O.O
22 CONTINUE INPUT= 1
K1=Kp+IKi*ST/21+Kd/ST K2=1Ki•ST/21-Kp-12•Kd/STJ K3=Kd/ST
EC41=INPUT DO 10 N=4,M XIN>=INPUT UINJ=UIN-1 I+K1•EINJ+K2>EIN-1 J+K3•EIN-21 YINI= IK•ST•CUINJ+UIN-1 J J/2 l+YIN-1 J EIN+1 >=XINI-YINJ TIN><>T+T<N-1 I
10 CONTINUE DO 20 I= 1 , N URITE 16,9991TIII,YII J,XII J,EIIJ
20 CONTINUE 999 FORMAT 12X,IJE14.51
CALL EXIT END
r 09:56 0.117 1 level 71
I
253
grafp.fortran 05/06/86 0956.9 bst Tue
C This program plots up to 10 sets of data on the same axes C or in different pages c
c
DIMENSION X<7000l,Y<7000l,AY<7000l DIMENSION ITITLE(80l, NAME<20l, LABX<20J, LABY<20J CHARACTER•B FINPUT
PRINT 1 FORMAT('1 = S5601 2 = M6250 3 = C1051N'l READ •,KP IF<KP.EQ.1 >CALL S5601 IF<KP.EQ.2lCALL T4010 JF<KP.EQ.3lCALL C1051N CALL ERRMAX<1000l !F<KP.EQ.1 lCALL UNITS<0.7l CALL DEVPAP<210.0,297.0,1 l print 2
2 format<'no of files' l read •,NOS DO 100 JJ=1 ,NOS PRINT 8
8 FORMAT<' name of input file' J READ •,FINPUT OPEN<UNIT = JJ, FILE= FINPUT, FORM= 'FORMATTED' l PRINT 11 1
111 FORMAT<'No. of points to plot:•> READ * ,NBS DO 20 I=1 ,NBS READ<JJ,•JX(Il,AY<I l
20 CONTINUE 25 CONTINUE
PRINT 333 333 FORMAT<'enter 1 to plot the next set, 0 to bypass it' l
READ *, IDRW
10
5
IF<IDRW~EQ.1 J GO TO 30 JJ = JJ + GO TO 25
30 ·CONTINUE PRINT 9
9 FORMAT<'enter 1 for new axis , otherwise 0' l READ *, I SAME
1 1
1 2
1 3
1 I I
15
IF<ISAME.EQ.OJ GO TO 17 PRINT 11 FORMAT<' enter READ *• XORX, PRINT 1 2 FORMAT<'enter READ *• XBEG, PRINT 1 3 FORMAT<' enter READ *• XORY, PRINT 1 4 FORMAT<' enter READ *• YBEG, CONTINUE CONTINUE PRINT 5 FORMAT<' X-axis
X_axis position,XOR,YOR, and length' YORX, XAXL
Xbeg, Xend, NO. of intervals' l XEND, NJNTX
Y_axis position, XOR, YOR, and length' l YORY, YAXL
Ybeg, Yend, NO. of intervals' l YEND, NINTY
label:' J
READ 555, LABX PHINT 6
254
6 FORMATC'Y-axis label:'> READ 555,LABY PRINT 7
7 FORMATC'enter position of title'> READ "• XTL, YTL PRINT 16
16 FORMATC'enter title of plot, not more than 80 character'> READ 555, I TITLE
555 FORMAT ( 1 OOA 1 l c
c
c
c
17 CONTINUE PRINT 4, JJ
4 FORMATC'NAME OF DATA SET NO', I2l READ 555, NAME DO 40 K = 1 , NBS
40 YCKJ = AYCKJ
IFCISAME.EQ.OJ GO TO 55 CALL CHASIZC2.5,2.5J CALL WINDOWC2l CALL AXIPOSC1, XORX, YORX, XAXL, 1 > CALL AXIPOSCO, XORY, YORY, YAXL, 2> CALL AXISCAC3, NINTX, XBEG, XEND,1 l CALL AXISCAC3, NINTY, YBEG, YEND,2l CALL AXIDRAC2, 1,1 l CALL MOVBY2C-50.0, -06.0) CALL CHAA1 CLABX,20l CALL AXIDRAf-2,-1 ,2> CALL MOVBY2C-15.0, -50.0l CALL CHAANGC90.0l CALL CHAA1 CLABY,20l CALL CHAANGCO.Ol
55 CONTINUE CALL PENSELCJJ,O.O,Ol CALL GRAPOLCX,Y,NBSl DMOV=-JJ*5 CALL MOVBY2CO.,DM0Vl CALL CHAA1 CNAME,20l
PRINT 57 57 FORMAT(' enter NSYMBOL: 1 - 3., or 0 for no symbols& NSPACE' l
READ "• NSYM, NSPACE IFCNSYM.EQ.OJ GO TO 58 CALL GRASYMCX, Y, NBS, NSYM, NSPACEJ
58 CONTINUE CALL CHASIZC3.,3.l CALL MOVT02CXTL, YTLJ CALL CHAA1 ( ITITLE,BOJ
60 CONTINUE PRINT 75
75 FORMATC'enter 1 for new page,O for the same page•, " • ,q to quit the pt·ogt·am' J
READCO,•,ERR=1000l KPAG !FCKPAG.EQ.OJ GO TO 100 CALL PICCLE
1 00 CONTINUE 1000 CALL DEVEND
CALL EXIT END
C-----------------------------------------------------------
.... ..
·'
.,.
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