IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-34, NO. 2, JUNE 1985

Microprocessor-Controlled Binary IndictiveVoltage Dividers

GUNTHER RAMM, REINHOLD VOLLMERT, AND HANS BACHMAIR

Abstract-This paper describes microprocessor-controlled binary in-ductive voltage dividers (IVD's) for use in IEC bus systems. Besides a24-bit binary IVD, a combination of a 12-bit binary IVD and a 12-bitDAC is reported upon. With a smaller expense of windings and circuitry,these dividers distinguish themselves to some extent by characteristicsbetter than those obtained with decade IVD's.

I. INTRODUCTIONIN CONNECTION with ac bridges [1], as well as in many

other fields of applications [2], IVD's are often used to gen-erate very accurate voltage ratios irrespective of temperatureand aging effects. While nowadays the overwhelming majorityare dividers with decade adjustable ratios, binary dividers willin future gain in important due to their better aptitude forcomputer control. In this paper such microprocessor-controlledbinary IVD's for use in IEC bus systems are described.

II. COMPARISON BETWEEN BINARY ANDDECADE IVD'S

Compared with a decade divider, a binary IVD has some sub-stantial advantages, especially with respect to operation withmicroprocessor or computer control. The expense of windingsand circuitry is reduced by about 35 percent, as may be seenfrom a comparison between a seven-decade IVD and the cor-responding 23-bit binary IVD. While the former consists of 70separate windings, the latter requires only 46 windings. At thesame time the expense of switches is also reduced, of, a binaryIVD needing only DPDT switches which may easily be replacedby the corresponding relays.At a frequency of 400 Hz, the relative errors in the real com-

ponent of the ratios are nearly the same for a seven-decadedivider and a 24-bit binary IVD. A typical value is 5 X 10-8for arbitrary ratios between zero and unity. On the otherhand, measurements have shown that typical errors of a seven-decade divider are of the order of 1 X 10-6 in the imaginarycomponent of the ratio whereas those of a binary IVD aresmaller by at least a factor of two. A more symmetrical struc-ture and smaller winding capacitances for the smaller numberof turns are reasons for this improvement.A binary IVD used for compensation purposes is adjusted in

a very similar way to a successive approximation ADC func-tion. A simple and fast adjustment is, therefore, possible espe-cially when the divider is operated with microprocessor orcomputer control.

Manuscript received August 20, 1984.The authors are with the Physikalisch-Technische Bundesanstalt,

Bundesallee 100, D-3300-Braunschweig, Federal Republic of Germany.

S1 S2 S7 S8

Uj

S9

Trl Tr2

Fig. 1. Winding diagram of the first core of a 24-bit binary IVD.

III. CIRCUIT DESIGN FOR BINARY INDUCTIVEVOLTAGE DIVIDERS

A. 24-Bit Binary IVDThis section describes the circuit design for a 24-bit binary

IVD with the least significant bit (LSB) corresponding to a re-solution of 6 X 10-8. The whole arrangement consists ofthreecores with separate windings for every 8 bit, the first two coresbeing realized as two-stage transformers, while the third one isa single-stage transformer. As an example, Fig. 1 shows thewinding diagram of the first core. The magnetizing core carriesthe main magnetizing winding with 256 turns and an auxiliarywinding with 1 turn for the magnetization of the second core.For the ratio windings the number of turns decreases in powersof two from two times 128 turns, to two times 1 turn. Thewindings are switched by special relays having extremely smallcontact resistances with small loads. The relays are directlydriven by TTL logic.The divider is designed for an input voltage Ui = 0.15 X f V,

200 V maximum, where f is the frequency in Hz. It may beoperated in a frequency range from 50 Hz to 5 kHz. Its inputimpedence is that of a parallel resonance circuit with L t 10H, C ;1 nF and a Q-factor of about 10, corresponding to avalue of 25 kQ at a frequency of 400 Hz. The maximum out-put impedance is represented by a series connection of a resis-tor of about 1.4 Q2 and an inductor of about 25 pH. At a fre-quency of 400 Hz, typical values for the ratio error of thedivider are 5 X 10-8 for the real component and 5 X 10-7 forthe imaginary component arbitrary ratios included.

B. Combination ofa 12-Bit Binary IVD and a 12-Bit DACThe combination of an IVD and a DAC, as shown in Fig. 2,

represents an even simpler solution for a binary divider. Thewhole arrangement consists of a 12-bit binary IVD with a resolu-tion of Uj/212 and a multiplying 12-bit DAC, the referencevoltage of which is derived from a special winding of the IVD.

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-34, NO. 2, JUNE 1985

S,3 I5,4 I I I I SIS13 S14 S23 S24

Fig. 2. Combination of a 12-bit binary IVD and a 12-bit DAC.

The output voltage of the converter is connected in series withthe output voltage of the divider by means of an additionaltransformer. By choosing appropriate numbers of turns forthe windings, the most significant bit (MSB) of the DAC cor-responds to Ui/213 and 1 LSB to Ui/224 so that the whole ar-rangement represents a 24-bit binary divider with a resolutionof 6 X 10-8.With respect to a 24-bit binary IVD, this circuit arrangement

has a certain number of advantages. The expense of circuitryand, therefore, the costs can be further reduced. The switchesmost frequently operated in the case of bridge balances arereplaced by fast and wear-resistant semiconductor switches.With the chosen distribution of 12 bits each, the output im-pedance is halved and at the same time nearly independent ofthe setting of the last 12 bits.The number of turns on the winding producing the reference

voltage for the DAC was so chosen that the reference input ofthe DAC is almost equal to its rated voltage, when the divideris operated with its maximum input voltage. The dynamicerrors of the DAC can be neglected, because it operates understeady-state conditions. The static errors of the DAC will notinfluence the ratio error of the divider, if its gain is properlyadjusted. This is done by self-calibration with the full outputvoltage of the DAC (Ui/212-Ui/224) connected opposite to thesmallest possible output voltage of the IVD (Ui/2'2) and thereal component of the differential voltage adjusted to Ui/224.With this self-calibration the ratio error of the combination ofa 12-bit binary IVD and a 12-bit DAC does not differ fromthat of the 24-bit binary IVD.

IV. INSTRUMENT DESIGN AND OPERATION

The 24-bit binary divider described above was combinedwith a microprocessor to form a programmable binary divider.As can be seen from Fig. 3, this divider is suitable for operationwith local as well as with remote control. With respect to asimple serviceability, the desired ratio is fed into the divider asan 8-digit number from 0.000 000 00 to 0.999 999 99. Thefunctional diagram in Fig. 4 describes the different modes ofoperation in more detail.In the case of manual control, the desired ratio is set by

means of up-down keys for each digit with a self-instructedcarry, except for a carry from 0.000 0(0 00 to 0.999 999 99,anjd vice versa. In addition, with separate function keys threefilxed ratios can be adjusted: the ratio nought (key "N), themaximum ratio (key "M") and a preset ratio (key 'P") stored

Fig. 3. Block diagram of a microprocessor-controlled 24-bit binarydivider.

Fig. 4. Functional diagram of the binary divider.

before actuating key "S". With a separate switch, the instru-ment can be switched over from remote to local control.With remote control the divider acts as a listener and is oper-

ated via an IEEE-488 interface which is controlled by the micro-processor. Having addressed the device, the controller transmitsa value for the divider ratio in a form of 8 BCD digits. Thisvalue is taken over and displayed.A single-board computer with a Z80A CPU controls the ad-

justment of the desired ratio of the divider with local as well aswith remote control. With the power switched on, the dataregisters are set to zero in order to bring the device to a defined,original state. With remote control, the BCD digits trans-mitted by the controller are taken over and directly trans-formed into a 24-bit binary word by means of the micropro-cessor. With manual control, the divider ratio adjusted by the8 up-down keys will be sensed cyclically and corrected if oneof the keys is acutated as described above. To avoid an un-wanted change-over of the relays, a certain delay is providedbetween the actuation of the keys and the setting of the relays.Actuating one of the function keys overwrites the data registers.The final storage contents is transformed into a 24-bit binaryword and the relays are set.

V. CONCLUSIONBinary IVD's are superior to decade IVD's for different rea-

sons. The expense of windings and circuitry will be reducedand can be further cut down if a binary IVD is combined witha DAC. Binary dividers have smaller errors in the imaginarycomponent of the ratio and allow fast and simple setting whichmeans reduced requirements on the stability of the source andbetter reproducibility for the bridge balance. But their greatest

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-34, NO. 2, JUNE 1985

advantage is that they can be directly controlled by a computeror a microprocessor and are, therefore, well-suited to com-puterized measuring systems. In this case, not only decaderatios but also other ratios calibrated in decibels or nepers andeven values of trigonometric functions (in conjunction withsynchro-resolvers) can easily be realized.

REFERENCES

[11 J. J. Hill, "An a.c. double bridge with inductively coupled ratioarms for precision platinum-resistance thermometry," Proc. Inst.Elect. Eng., vol. 110, pp. 453-458, 1963.

[21 G. Ramm, "Impedance measuring device based on an AC poten-tiometer," pp. 341-344, this issue.

A Low-Frequency Bridge For High-TemperatureResistance Thermometry

LUIGI CROVINI, PIERO MARCARINO, AND GIORGIO FRASSINETI

Abstract-A 28.5-Hz resistance bridge, is described as beingparticularlysuited to high-temperature resistance thennometry. It features a balancesensitivity to within 0.3 nV, a nonlinearity less than ± 10-6 of the mea-sured value and battery operation. The design is such that it requiresonly commercial components for its construction.

I. INTRODUCTION

T ODAY platinum-resistance thermometry requires mea-surement sensitivities at micro-ohm and submicro-ohm

levels, with dissipated power not exceeding 100 1W. Conven-tional standard platinum-resistance thermometers complyingwith the requirements of the International Practical Tempera-ture Scale of 1968 (IPTS-68) cover the range from 13.81 to903.89 K, with resistances varying approximately from 0.035 to85 Q (25.5 Q2 at OOC), and sensitivities from 5 to 100 mQ/K.To match the reproducibilities of most flxed points it is neces-sary to measure resistances with a resolution of 0.5 ,u2, or bet-ter, at very low temperatures and 5 ,u2, or better, above 0°C.To extend the platinum-resistance scale to the freezing point

of silver (961.930C), or to the freezing point of gold, lower re-sistance thermometers are used in order to minimize systematicerrors due to insulation leakage and to obtain better stability,presenting a smaller surface per unit mass to chemical contam-ination. Resistances at 0°C of 0.25 Q2, or of 2.5 2, are com-monly used, with sensitivities proportionally reduced, but withlead resistances proportionally increased. In addition, thermalEMF's generated at high temperature can be so large and vari-able that it would not be possible with a dc bridge to detectchanges below 10 mK.In one practical case, it is necessary to resolve 0.1 p,u in 1 Q2,

with not more than 10 mA in the thermometer, to obtain a

measurement sensitivity slightly better than 0.2 mK at the gold

Manuscript received August 21, 1984.The authors are with the Istituto di Metrologia "G. Colonnetti," 10135

Torino, Italy.

point. Moreover, the result of the measurement must be com-pletely independent of the lead resistances, and the linearity ofmeasured resistance ratios must be better than ±10-6. Theunique solution to this problem is an ac bridge.A few such bridges, of differing design, have been made avail-

able commercially in the last ten years, but most of them donot meet the requirements of high-temperature resistancethermometry, partly because the excitation frequency is toohigh (e.g., above 50 Hz), and partly because they have not beenoptimized for very low resistances.A few other bridges have been described recently, show-

ing adequate performances for this application [I] - [4]. How-ever, they require nonstandard components for their realiza-tion, particularly specially made, multistage, inductive voltagedividers.

II. DESCRIPTION OF THE BRIDGE

The bridge that has been realized at the Istituto di Metrologia"G. Colonnetti" (IMGC) operates at 28.5 Hz. It is manuallybalanced, but its out of balance signal can be fed to a recorderstill maintaining good linearity and sensitivity. The instrumentis completely battery-powered in order to avoid ground-loopswhen measuring a thermometer in a furnace. Perhaps its mostimportant feature is that it can be constructed with commer-cially-available components and is thus easily reproduced in anylaboratory where it is needed.The operating principle is based on the possibility of generat-

ing currents with extremely accurate ratios in two, or more,isolated loops, as first described by Crovini and Kirby [5]. Anautomated bridge, operating on the same principle and intendedfor use with 25-2 thermometers, was developed by Kirby [2].Fig. I shows a loop schematically: there are two differentialoperational amplifiers with very high open-loop gain, equippedwith two fully isolated dual-voltage power supplies. Assumingthe gain is infinite there results a perfect current generator, the

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