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UNIT-I

8085 Microprocessor The salient features of 8085 µp are:

• It is a 8 bit microprocessor. • It is manufactured with N-MOS technology. • It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory

locations through A0-A

15.

• The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD

7.

• Data bus is a group of 8 lines D0 – D

7.

• It supports external interrupt request. • A 16 bit program counter (PC) • A 16 bit stack pointer (SP) • Six 8-bit general purpose register arranged in pairs: BC, DE, HL. • It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock. • It is enclosed with 40 pins DIP (Dual in line package).

Overview of 8085 microprocessor 8085 Architecture

• Pin Diagram • Functional Block Diagram

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8086 Microprocessor •It is a 16-bit µp. •8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). •It can support up to 64K I/O ports. •It provides 14, 16 -bit registers. •It has multiplexed address and data bus AD0- AD15 and A16 – A19. •It requires single phase clock with 33% duty cycle to provide internal timing. •8086 is designed to operate in two modes, Minimum and Maximum. •It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. •It requires +5V power supply. •A 40 pin dual in line package Minimum and Maximum Modes: •The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single microprocessor configuration. •The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a multi micro processors configuration.

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Architecture of 8086

The 8086/8088 architecture can be broadly divided into two groups: (i) Execution Unit (EU) (ii) Bus Interface Unit (BIU) Internal Architecture of 8086 •8086 has two blocks BIU and EU. •The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. •EU executes instructions from the instruction system byte queue. •Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. •BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. •EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. BUS INTERFACR UNIT: •It provides a full 16 bit bidirectional data bus and 20 bit address bus. •The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: •Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. •The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. •This queue permits prefetch of up to six bytes of instruction code. Whenever the queue of the

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BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. •These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. •After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. •The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. •These intervals of no bus activity, which may occur between bus cycles are known as Idle state. •If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. •The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. •For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. •The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. EXECUTION UNIT The Execution unit is responsible for decoding and executing all instructions. •The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. •During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. •If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. •When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. •Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue. General Registers The CPU has eight 16-bit general registers. They are divided into two files of four registers each. They are: (a) The data register file and (b) The pointer and index register file

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AX, BX, CX and DX registers are the data registers. The upper and lower half of the data registers is individually addressable. AX register can be addressed as AL and AH registers, BX register can be addressed as BL and BH register, CX register can be addressed as CL and CH register, DX register can be addressed as DL and DH. The data registers can be used in most arithmetic and logic operations. Some instructions however require these registers for specific use. The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source Index (SI) and Destination Index (DI) registers all are of 16-bits. They can also be used in most arithmetic and logic operations. These registers are usually used to hold offset addresses for addressing within a segment. Offset addressing reduces program size by eliminating the need for each instruction to specify frequently used addresses. The pointer and index register files are further divided into the pointer sub-file (containing the Stack Pointer and the Base Pointer registers) and the index sub-file (containing the Source index and Destination index registers). The Pointer registers are used to access the current stack segment. The index registers are used to access the current data. (Stack segment and data segment are specific areas of memory. Their application will be explained in later chapters). Unless otherwise specified in the instruction, stack pointer registers refer to the current stack segment while index register refers to the current data segment. The BP and SP registers are both used to point to the stack, a linear array in the memory used for subroutine parameters, subroutine return addresses, and the data temporarily saved during execution of a program. The implicit register usage is as follows:

Most microprocessors have a single stack pointer register called the SP. 8086 / 8088 has an additional pointer into the stack called the BP register. While the SP is used similar to the stack pointer in other machine (for pointing to subroutine and interrupt return addresses), the BP register is used to hold an old stack pointer value, or it can mark a place in the subroutine stack independent of the SP register. Using the BP register to mark the stack saves the juggling of a single stack pointer to reference subroutine parameters and addresses. SI and DI are both 16-bits wide and are used by string manipulation instructions and in building some of the more powerful 8086/8088 data structures and addressing modes. Both the SI and the DI registers have auto incrementing and auto-decrementing capabilities. Flag Register The Execution Unit has a 16-bit flag register which indicates some conditions affected by the execution of an instruction. Some bits of the flag register control certain operations of the EU. The flag register in the EU contains nine active flags

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Six of the nine flags are used to indicate some condition produced by an instruction. These condition flags are also called status flags of 8086/8088 microprocessor. These are the Carry flag, Parity flag, Auxiliary carry flag, Zero flag, and Sign flag. The other three Control flags are Trap Flag, Direction Flag and Interrupt flag. Condition Flags Carry Flag (CF) This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of the most significant bit position or if there is a borrow to the MSB after subtraction. This flag is also affected when other arithmetic and logical instruction are executed. Parity Flag (PF) This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the result). This flag can be used to check for data transmission error. Auxiliary Carry Flag (AF) This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibble to the lower. The auxiliary carry flag is used for decimal adjust operation. The AF flag is of significance only for byte operations during which the lower order byte of the 16-bit word is used. Zero Flag (Z) This flag is set when the result of an operation is zero. The flag is reset when the result is not zero. Overflow Flag (O) This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result exceeded the storage capacity of the destination, and a significant digit has been lost. Sign flag (S) This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this flag is set the data in assumed to be negative and when this flag is zero it is assumed to be positive. Control Flags Control flags are used to control certain operations of the processor. The application of these flags are different from that of six conditional flags. The conditional flags are set or reset by the EU on the basis of the result of some arithmetic or logic operations. The control flags are deliberately set or reset with specific instructions included in the program. Trap flag (T) This is used for single stepping through a program. It is used for debugging the programs. (Discusses with interrupts). Interrupt Flag (I) It is used to allow / prohibit the interruption of a program. When the flag set, it enables the interrupt from INTR. When the flag is reset (0), it disables the interrupt. Direction Flag (D) It is used for string instruction (Discussed with the specific instructions later in the book). If the direction flag is set, the pointers are decremented else the pointers are incremented. Instruction Pointer (IP) The Instruction Pointer is a 16-bit register. This register is always used as the effective memory

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address, and is added to the Code segment with a displacement of four bits to obtain the physical address of the opcode. The code segment cannot be changed by the move instruction. The instruction pointer is incremented after each opcode fetch to point to the next instruction. The segment registers point to the four immediately addressable segments. The four segment registers are

Code Segment register [points to the instruction opcode] Data Segment register [points to the data memory] Stack Segment register [points to the Stack memory] Extra Segment register [points to the data memory]

Assembler Directives Assembler directives are the commands to the assembler that direct the assembly process. They indicate how an operand is treated by the assembler and how assembler handles the program. They also direct the assembler how program and data should be arranged in the memory. The important point to be noted here is they do not generate any machine code i.e. they do not contribute to the final size of machine code. And, they are assembler specific. .MODEL directive This directive is used to specify how many code and data segments are necessary for the program. The syntax is: .MODEL memory_model. The memory model can be chosen based on our requirement as follows:

.STACK directive This directive is optional and is used to define the size of the stack segment. Syntax: .STACK <size> For example, we can define a 100 bytes stack segment as .STACK 100d .DATA directive This directive is used to define data segment necessary for our program. Data can be of different types like byte, word, double word or quad word. They can be declared using directives as follows: DB – Define Byte DW – Define Word DD – Define Double Word DQ – Define Quad Word DT – Define Ten Bytes There is one special directive to define blocks of larger size. It is DUP. Syntax: label type size DUP (value to initialize in all locations) .CODE directive This directive is used to indicate the beginning of instructions i.e. the assembly code. The assembly language program is end with END directive

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ASSUME directive This is specific to MASM Assembler. It is used to give symbolic names to the different segments. For example, Assume cs:code, ds:data, ss:stack at the first line of your program indicates there are three segments in the program and data is the name given to data segment, code is the name of code segment and stack is the name for stack segment. Remember data, code and stack are user given names. SEGMENT and ENDS directives They are used to mark the beginning and end of the particular segment. Syntax: segment_name SEGMENT . . . segment_name ENDS For example, data segment can be declared as: DATA SEGMENT X DB 10H Y DB 20H Z DB ? DATA ENDS Similarly code and data segments can also be declared. PROC and ENDP directives They are used to define procedures in assembly language programs. They mark the beginning and end of the procedure. Syntax: Proc_name PROC <NEAR/FAR> . . . body of the procedure . . . RET Proc_name ENDP Observe ENDP is always preceded by either RET or IRET instruction. MACRO and ENDM directives They are used to define macros in assembly language programs. MACROS are a set of instructions which are intended to do a particular task. Where ever assembler finds the name of the macro in the main program, it replaces the set of instructions present in the macro at that place.

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8086 Instruction set types Data Copy / Transfer Instructions : MOV : This instruction copies a word or a byte of data from some source to a destination. The destination can be a register or a memory location. The source can be a register, a memory location, or an immediate number. MOV AX,BX MOV AX,5000H MOV AX,[SI] MOV AX,[2000H] MOV AX,50H[BX] MOV [734AH],BX MOV DS,CX MOV CL,[357AH] Direct loading of the segment registers with immediate data is not permitted. PUSH : Push to Stack This instruction pushes the contents of the specified register/memory location on to the stack. The stack pointer is decremented by 2, after each execution of the instruction. E.g. PUSH AX • PUSH DS • PUSH [5000H POP : Pop from Sack This instruction when executed, loads the specified register/memory location with the contents of the memory location of which the address is formed using the current stack segment and stack pointer. The stack pointer is incremented by 2

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Eg. POP AX POP DS POP [5000H] XCHG : Exchange byte or word This instruction exchange the contents of the specified source and destination operands Eg. XCHG [5000H], AX XCHG BX, AX IN: Copy a byte or word from specified port to accumulator. Eg. IN AL,03H IN AX,DX OUT: Copy a byte or word from accumulator specified port. Eg. OUT 03H, AL OUT DX, AX Arithmetic Instructions: The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication and comparing two values. ADD : The add instruction adds the contents of the source operand to the destination operand. Eg. ADD AX, 0100H ADD AX, BX ADD AX, [SI] ADD AX, [5000H] ADD [5000H], 0100H ADD 0100H ADC : Add with Carry This instruction performs the same operation as ADD instruction, but adds the carry flag to the result. Eg. ADC 0100H ADC AX, BX ADC AX, [SI] ADC AX, [5000] ADC [5000], 0100H SUB : Subtract The subtract instruction subtracts the source operand from the destination operand and the result is left in the destination operand. Eg. SUB AX, 0100H SUB AX, BX SUB AX, [5000H] SUB [5000H], 0100H

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SBB : Subtract with Borrow The subtract with borrow instruction subtracts the source operand and the borrow flag (CF) which may reflect the result of the previous calculations, from the destination operand Eg. SBB AX, 0100H SBB AX, BX SBB AX, [5000H] SBB [5000H], 0100H INC : Increment This instruction increases the contents of the specified Register or memory location by 1. Immediate data cannot be operand of this instruction. Eg. INC AX INC [BX] INC [5000H] DEC : Decrement The decrement instruction subtracts 1 from the contents of the specified register or memory location. Eg. DEC AX DEC [5000H] NEG : Negate The negate instruction forms 2’s complement of the specified destination in the instruction. The destination can be a register or a memory location. This instruction can be implemented by inverting each bit and adding 1 to it. Eg. NEG AL AL = 0011 0101 35H Replace number in AL with its 2’s complement AL = 1100 1011 = CBH CMP : Compare This instruction compares the source operand, which may be a register or an immediate data or a memory location, with a destination operand that may be a register or a memory location Eg. CMP BX, 0100H CMP AX, 0100H CMP [5000H], 0100H CMP BX, [SI] CMP BX, CX MUL :Unsigned Multiplication Byte or Word This instruction multiplies an unsigned byte or word by the contents of AL. Eg. MUL BH ; (AX) (AL) x (BH) MUL CX ; (DX)(AX) (AX) x (CX) MUL WORD PTR [SI] ; (DX)(AX) (AX) x ([SI]) IMUL :Signed Multiplication This instruction multiplies a signed byte in source operand by a signed byte in AL or a signed word in source operand by a signed word in AX. Eg. IMUL BH IMUL CX IMUL [SI]

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DIV : Unsigned division This instruction is used to divide an unsigned word by a byte or to divide an unsigned double word by a word.

Logical Instructions AND : Logical AND This instruction bit by bit ANDs the source operand that may be an immediate register or a memory location to the destination operand that may a register or a memory location. The result is stored in the destination operand. Eg. AND AX, 0008H AND AX, BX OR : Logical OR This instruction bit by bit ORs the source operand that may be an immediate , register or a memory location to the destination operand that may a register or a memory location. The result is stored in the destination operand. Eg. OR AX, 0008H OR AX, BX NOT : Logical Invert This instruction complements the contents of an operand register or a memory location, bit by bit. Eg. NOT AX NOT [5000H] XOR : Logical Exclusive OR This instruction bit by bit XORs the source operand that may be an immediate , register or a memory location to the destination operand that may a register or a memory location. The result is stored in the destination operand. Eg. XOR AX, 0098H XOR AX, BX TEST : Logical Compare Instruction The TEST instruction performs a bit by bit logical AND operation on the two operands. The result of this ANDing operation is not available for further use, but flags are affected. Eg. TEST AX, BX TEST [0500], 06H SAL/SHL : SAL / SHL destination, count. SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in the specified destination to the left and 0 is stored at LSB position. The MSB is shifted into the carry flag. The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts is indicated by count. Eg. SAL CX, 1 SAL AX, CL

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SHR : SHR destination, count This instruction shifts each bit in the specified destination to the right and 0 is stored at MSB position. The LSB is shifted into the carry flag. The destination can be a byte or a word. It can be a register or in a memory location. The number of shifts is indicated by count. Eg. SHR CX, 1 MOV CL, 05H SHR AX, CL SAR : SAR destination, count This instruction shifts each bit in the specified destination some number of bit positions to the right. As a bit is shifted out of the MSB position, a copy of the old MSB is put in the MSB position. The LSB will be shifted into CF. Eg. SAR BL, 1 MOV CL, 04H SAR DX, CL ROL Instruction : ROL destination, count This instruction rotates all bits in a specified byte or word to the left some number of bit positions. MSB is placed as a new LSB and a new CF. Eg. ROL CX, 1 MOV CL, 03H ROL BL, CL ROR Instruction : ROR destination, count This instruction rotates all bits in a specified byte or word to the right some number of bit positions. LSB is placed as a new MSB and a new CF. Eg. ROR CX, 1 MOV CL, 03H ROR BL, CL RCL Instruction : RCL destination, count This instruction rotates all bits in a specified byte or word some number of bit positions to the left along with the carry flag. MSB is placed as a new carry and previous carry is place as new LSB. Eg. RCL CX, 1 MOV CL, 04H RCL AL, CL RCR Instruction : RCR destination, count This instruction rotates all bits in a specified byte or word some number of bit positions to the right along with the carry flag. LSB is placed as a new carry and previous carry is place as new MSB. Eg. RCR CX, 1 MOV CL, 04H RCR AL, CL ROR Instruction : ROR destination, count This instruction rotates all bits in a specified byte or word to the right some number of bit positions. LSB is placed as a new MSB and a new CF. Eg. ROR CX, 1 MOV CL, 03H ROR BL, CL

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RCL Instruction : RCL destination, count This instruction rotates all bits in a specified byte or word some number of bit positions to the left along with the carry flag. MSB is placed as a new carry and previous carry is place as new LSB. Eg. RCL CX, 1 MOV CL, 04H RCL AL, CL RCR Instruction : RCR destination, count This instruction rotates all bits in a specified byte or word some number of bit positions to the right along with the carry flag. LSB is placed as a new carry and previous carry is place as new MSB. Eg. RCR CX, 1 MOV CL, 04H RCR AL, CL Branch Instructions : Branch Instructions transfers the flow of execution of the program to a new address specified in the instruction directly or indirectly. When this type of instruction is executed, the CS and IP registers get loaded with new values of CS and IP corresponding to the location to be transferred. The Branch Instructions are classified into two types i. Unconditional Branch Instructions. ii. Conditional Branch Instructions. Unconditional Branch Instructions : In Unconditional control transfer instructions, the execution control is transferred to the specified location independent of any status or condition. The CS and IP are unconditionally modified to the new CS and IP. CALL : Unconditional Call This instruction is used to call a Subroutine (Procedure) from a main program. Address of procedure may be specified directly or indirectly. There are two types of procedure depending upon whether it is available in the same segment or in another segment. i. Near CALL i.e., ±32K displacement. ii. For CALL i.e., anywhere outside the segment. On execution this instruction stores the incremented IP & CS onto the stack and loads the CS & IP registers with segment and offset addresses of the procedure to be called. RET: Return from the Procedure. At the end of the procedure, the RET instruction must be executed. When it is executed, the previously stored content of IP and CS along with Flags are retrieved into the CS, IP and Flag registers from the stack and execution of the main program continues further. INT N: Interrupt Type N. In the interrupt structure of 8086, 256 interrupts are defined corresponding to the types from 00H to FFH. When INT N instruction is executed, the type byte N is multiplied by 4 and the contents of IP and CS of the interrupt service routine will be taken from memory block in 0000 segment. JMP: Unconditional Jump This instruction unconditionally transfers the control of execution to the specified address using an 8-bit or 16-bit displacement. No Flags are affected by this instruction.

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IRET: Return from ISR When it is executed, the values of IP, CS and Flags are retrieved from the stack to continue the execution of the main program. LOOP : LOOP Unconditionally This instruction executes the part of the program from the Label or address specified in the instruction upto the LOOP instruction CX number of times. At each iteration, CX is decremented automatically and JUMP IF NOT ZERO structure. Conditional Branch Instructions When this instruction is executed, execution control is transferred to the address specified relatively in the instruction, provided the condition implicit in the Opcode is satisfied. Otherwise execution continues sequentially. JZ/JE Label Transfer execution control to address ‘Label’, if ZF=1. JNZ/JNE Label Transfer execution control to address ‘Label’, if ZF=0 JS Label Transfer execution control to address ‘Label’, if SF=1. JNS Label Transfer execution control to address ‘Label’, if SF=0. JO Label Transfer execution control to address ‘Label’, if OF=1. JNO Label Transfer execution control to address ‘Label’, if OF=0. JNP Label Transfer execution control to address ‘Label’, if PF=0. JP Label Transfer execution control to address ‘Label’, if PF=1. JB Label Transfer execution control to address ‘Label’, if CF=1. JNB Label Transfer execution control to address ‘Label’, if CF=0. JCXZ Label Transfer execution control to address ‘Label’, if CX=0 REP : Repeat Instruction Prefix This instruction is used as a prefix to other instructions, the instruction to which the REP prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is automatically decremented by one). i. REPE / REPZ - repeat operation while equal / zero. ii. REPNE / REPNZ - repeat operation while not equal / not zero. These are used for CMPS, SCAS instructions only, as instruction prefixes. MOVSB / MOVSW :Move String Byte or String Word Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to another set of destination locations.The starting byte of source string is located in the memory location whose address may be computed using SI (Source Index) and DS (Data Segment) contents. The starting address of the destination locations where this string has to be relocated is given by DI (Destination Index) and ES (Extra Segment) contents.

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CMPS : Compare String Byte or String Word The CMPS instruction can be used to compare two strings of byte or words. The length of the string must be stored in the register CX. If both the byte or word strings are equal, zero Flag is set.The REP instruction Prefix is used to repeat the operation till CX (counter) becomes zero or the condition specified by the REP Prefix is False. SCAN : Scan String Byte or String Word This instruction scans a string of bytes or words for an operand byte or word specified in the register AL or AX. The String is pointed to by ES:DI register pair. The length of the string s stored in CX. The DF controls the mode for scanning of the string. Whenever a match to the specified operand, is found in the string, execution stops and the zero Flag is set. If no match is found, the zero flag is reset. LODS : Load String Byte or String Word The LODS instruction loads the AL / AX register by the content of a string pointed to by DS: SI register pair. The SI is modified automatically depending upon DF, If it is a byte transfer (LODSB), the SI is modified by one and if it is a word transfer (LODSW), the SI is modified by two. No other Flags are affected by this instruction. STOS : Store String Byte or String Word The STOS instruction Stores the AL / AX register contents to a location in the string pointer by ES : DI register pair. The DI is modified accordingly, No Flags are affected by this instruction. The direction Flag controls the String instruction execution, The source index SI and Destination Index DI are modified after each iteration automatically. If DF=1, then the execution follows autodecrement mode, SI and DI are decremented automatically after each iteration. If DF=0, then the execution follows autoincrement mode. In this mode, SI and DI are incremented automatically after each iteration. Flag Manipulation and a Processor Control Instructions These instructions control the functioning of the available hardware inside the processor chip. These instructions are categorized into two types: 1. Flag Manipulation instructions. 2. Machine Control instructions. Flag Manipulation instructions The Flag manipulation instructions directly modify some of the Flags of 8086. i. CLC – Clear Carry Flag. ii. CMC – Complement Carry Flag. iii. STC – Set Carry Flag. iv. CLD – Clear Direction Flag. v. STD – Set Direction Flag. vi. CLI – Clear Interrupt Flag. vii. STI – Set Interrupt Flag. Machine Control instructions The Machine control instructions control the bus usage and execution i. WAIT – Wait for Test input pin to go low. ii. HLT – Halt the process. iii. NOP – No operation. iv. ESC – Escape to external device like NDP v. LOCK – Bus lock instruction prefix.

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8086 Addressing Modes for accessing data

Addressing modes provide convenience in accessing data needed in an instruction.

8086 Addressing Modes for accessing data

ImmediateAddressing mode(for sourceoperand only)

Register addressing Memory addressing I/O port addressing

Immediate Addressing

Before After

Ex1: MOV DX, 1234H DX ABCDH 1234H

Before After

Ex2: MOV CH, 23H CH 4DH 23H

Register Addressing

Before After

Ex1: MOV CX, SI CX 1234H 5678H

SI 5678H 5678H

Before After

Ex2: MOV DL, AH Dl 89H BCH

AH BCH BCH

Memory Addressing

Direct Addressing Indirect Addressing

Memory Indirect Addressing

RegisterIndirect

Based Addressingwithdisplacement

IndexedAddressing withdisplacement

BasedIndexedaddressing

Based Indexedaddressing withdisplacement

Memory Direct Addressing

Before After

Ex1: MOV BX, DS:5634H BX ABCDH 8645H

DS:5634H 45H LS byteDS:5635H 86H MS byte

Before After

Ex2: MOV CL, DS:5634H CL F2H 45H

DS:5634H 45HDS:5635H 86H

Ex3: MOV BH, LOC Before After

Program.DATA

LOC DB 78H

BH C5H 78H

Register Indirect Addressing

Before After

Ex1: MOV CL, [SI] CL 20H 78H

SI 3456H

DS:3456H 78H

Before After

Ex2: MOV DX, [BX] DX F232H 3567H

BX A2B2H

DS:A2B2H 67H LS byteDS:A2B3H 35H MS byte

Before After

Ex3: MOV AH, [DI] AH 30H 86H

DI 3400H

DS:3400H 86H

Only SI, DI and BX can be used inside [ ] from memory addressing point of view. Fromuser point of view [BP] is also possible. This scheme provides 3 ways of addressing anoperand in memory.

Based Addressing with displacement

Before After

Ex1: MOV DH, 2345H[BX] DH 45H 67H

2345H is 16-bit displacement BX 4000H

4000 + 2345 = 6345H DS:6345H 67H

Before After

Ex2: MOV AX, 45H[BP] AX 1000H CDABH

45H is 8-bit displacement BP 3000H

3000 + 45 = 3045H SS:3045H ABH LS byteIt is SS when BP is used SS:3346H CDH MS byte

Base register can only be BX or BP. This scheme provides 4 ways of addressing anoperand in memory.

Indexed Addressing with displacement

Before After

Ex1: MOV CL, 2345H[SI] CL 60H 85H

2345H is 16-bit displacement SI 6000H

6000 + 2345 = 8345H DS:8345H 85H

Before After

Ex2: MOV DX, 37H[DI] DX 7000H B2A2H

37H is 8-bit displacement DI 5000H

5000H+ 37H = 5037H DS:5037H A2H LS byteDS:5038H B2H MS byte

Index register can only be SI or DI. This scheme provides 4 ways of addressing anoperand in memory.

Based Indexed Addressing

Before After

Ex1: MOV CL, [SI][BX] CL 40H 67H

SI 2000H

BX 0300H

2000H + 0300H = 2300H DS:2300H 67H

Before After

Ex2: MOV CX, [BP][DI] CX 6000H 6385H

BP 3000H

DI 0020H

2000H + 0300H = 2300H SS:3020H 85H LS byteIt is SS when BP is used SS:3021H 63H MS byte

This scheme provides 4 ways of addressing an operand in memory. One register must bea Base register and the other must be an Index register.For ex. MOV CX, [BX][BP] is an invalid instruction.

Based Indexed Addressing with Displacement

Before After

Ex1: MOV DL, 37H[BX+DI] DL 40H 12H

37H is 8-bit displacement BX 2000H

DI 0050H

2000H + 0050H + 37H = 2300H DS:2087H 12H

Before After

Ex2: MOV BX, 1234H[SI+BP] BX 3000H 3665H

SI 4000H

BP 0020H

4000H + 0020H +1234 = 5254H SS:5254H 65H LS byteIt is SS when BP is used SS:5255H 36H MS byte

This scheme provides 8 ways of addressing an operand in memory.

Memory modes as derivatives of Based Indexed Addressing with Displacement

Instruction BaseRegister

IndexRegister

Displacement

Addressing mode

MOV BX, DS:5634H No No Yes Direct AddressingMOV CL, [SI] No Yes No Register IndirectMOV DX, [BX] Yes No NoMOV DH, 2345H[BX Yes No Yes Based Addressing with

DisplacementMOV DX, 35H[DI] No Yes Yes Indexed Addressing with

displacementMOV CL, 37H[SI+BX] Yes Yes No Based Indexed AddressingMOV DL, 37H[BX+DI] Yes Yes Yes Based Indexed Addressing

with displacement

I/O port Addressing

I/O port Addressing

Fixed port addressingOr Direct Port addressing

Variable port addressingOr Indirect port addressing

Fixed Port Addressing

Before AfterEx. 1: IN AL, 83H AL 34H 78H

Input port no. 83H 78H

Before AfterEx. 2: IN AX, 83H AX 5634H F278H

Input port no. 83H 78HInput port no. 84H F2H

Before AfterEx. 3: OUT 83H, AL AL 50H

Output port no. 83H 65H 50H

Before AfterEx. 4: OUT 83H, AX AX 6050H

Output port no. 83H 65H 50HOutput port no. 84H 40H 60H

IN and OUT instructions are allowed to use only AL or AX registers. Port address in therange 00 to FFH is provided in the instruction directly.

Variable Port Addressing

I/O port address is provided in DX register. Port address ranges from 0000 to FFFFH.Data transfer with AL or AX only.

Before AfterEx. 1: IN AL, DX AL 30H 60H

DX 1234H

Input port no. 1234H 60H

Before AfterEx. 2: IN AX, DX AX 3040H 7060H

DX 4000H

Input port no. 4000H 60HInput port no. 4001H 70H

Before AfterEx. 3: OUT DX, AL AL 65H

DX 5000H

Output port no. 5000H 80H 65H

Before AfterEx. 4: OUT DX, AX AX 4567H

DX 5000H

Output port no. 5000H 25H 67HOutput port no. 5001H 36H 45H

UNIT-3

Pin Configuration

AD0 - AD15 (I/O): Address Data Bus These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) and data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus, pins D0-D7. A0 bit is Low during T1 state when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. These lines are active high and float to tri-state during interrupt acknowledge and local bus "Hold acknowledge". shows the timing of AD0 – AD15 lines to access data and address.

A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status During T1 state these lines are the four most significant address lines for memory operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, and T4 states. S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is indicated through this bus.

S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus. S3 & S4: Lines are decoded as follows:

BHE /S7 (O): Bus High Enable/Status During T1 state theBHE should be used to enable data onto the most significant half of the data bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4 states. The signal is active Low and floats to 3-state during "hold" state. This pin is Low during T1 state for the first interrupt acknowledge cycle. RD (O): READ The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is active low during T2 and T3 states and the Tw states of any read cycle. This signal floats to tri-state in "hold acknowledge cycle". TEST (I) TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues. Otherwise the processor waits in an "idle" state. This input is synchronized internally during each clock cycle on the leading edge of CLK. INTR (I): Interrupt Request It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector look up table located in system memory. It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized. This signal is active HIGH. NMI (I): Non-Muskable Interrupt An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector look up table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current instruction. This input is internally synchronized. Reset (I) Reset causes the processor to immediately terminate its present activity. To be recognised, the signal must be active high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. Ready (I) Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock

generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met. CLK (I): Clock Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33% duty cycle to provide optimized internal timing. MN/MX (I): Maximum / Minimum This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself generates all bus control signals. In maximum mode the three status signals are to be decoded to generate all the bus control signals. Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum mode; MN/MX = 1. The corresponding 8 pins function descriptions for maximum mode is explained later. M/ IO (O): Status line This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a bus cycle and remains valid until the final T4 of the cycle. M/ IO floats to 3 - state OFF during local bus "hold acknowledge". WR (O): Write Indicates that the processor is performing a write memory or write IO cycle, depending on the state of the M / IOsignal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW, and floats to 3-state OFF during local bus "hold acknowledge ". INTA (O): Interrupt Acknowledge It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and T4 of each interrupt acknowledge cycle. ALE (O): Address Latch Enable ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated. DT/ R (O): DATA Transmit/Receive In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the direction of data flow through the transceiver. This signal floats to tri-state off during local bus "hold acknowledge". DEN (O): Data Enable It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and IO access. It will be low beginning with T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. It floats to tri-state off during local bus "hold acknowledge". HOLD & HLDA (I/O): Hold and Hold Acknowledge Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as being Low, the processor will lower the HLDA and when the processor needs to run another cycle, it will again drive the local bus and control lines. Maximum Mode The following pins function descriptions are for the 8086/8088 systems in maximum mode (i.e.. MN/MX= 0). Only the pins which are unique to maximum mode are described below.

S2, S1, S0 (O): Status Pins These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the beginning of a bus cycle

QS0, QS1 (O): Queue – Status Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS1 provide status to allow external tracking of the internal 8086 instruction queue. Queue status allows external devices like In-circuit Emulators or special instruction set extension co-processors to track the CPU instruction execution. Since instructions are executed from the 8086 internal queue, the queue status is presented each CPU clock cycle and is not related to the bus cycle activity. This mechanism allows (1) A processor to detect execution of a ESCAPE instruction which directs the coprocessor to perform a specific task and (2) An in-circuit Emulator to trap execution of a specific memory location.

LOCK (O) It indicates to another system bus master, not to gain control of the system bus while LOCK is active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the completion of the instruction. This signal is active Low and floats to tri-state OFF during 'hold acknowledge". RQ / 0 GT and RQ / 1 GT (I/O): Request/Grant These pins are used by other processors in a multi processor organization. Local bus masters of other processors force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they may be left un-connected.

Minimum Mode 8086 System:

A minimum mode of 8086 configuration depicts a stand alone system of computer where no other processor is connected. This is similar to 8085 block diagram with the following difference. The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two control signals data transmit/ receive are connected to the direction input of transceiver (Transmitter/Receiver) and DEN* signal works as enable for this block. Read Cycle Timing Diagram for Minimum Mode

In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for Read

operation. To validate the data, DEN* signal goes low. The Address/ Status bus carries A16 to

A19 address lines during BHE* (low) and for the remaining time carries Status information. The

Address/Data bus carries A0 to A15 address information during ALE going high and for the

remaining time it carries data. The RD* line going low indicates that this is a Read operation.

The curved arrows indicate the relationship between valid data and RD* signal.

The TW is Wait time needed to synchronize the fast processor with slow memory etc. The Ready

pin is checked to see whether any peripheral needs more time for data transmission.

Write Cycle Timing Diagram for Minimum Operation

This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating it is a Data Transmission operation for the processor to memory / peripheral. Again DEN* line goes low to validate data and WR* line goes low, indicating a Write operation.

Maximum Mode 8086 System

In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type 8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are shared resources between the two processors. The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788. The three status outputs S0*, S1*, S2* from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals perform the same task as the minimum mode operation. However the DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter. Memory Read Timing in Maximum Mode

Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* are active and are used to generate control signal. Memory Write Timing in Maximum Mode

Here the maximum mode write signals are shown. Please note that the T states correspond to the time during which DEN* is LOW, WRITE Control goes LOW, DT/R* is HIGH and data output in available from the processor on the data bus.

GT /RQ Timings in Maximum Mode

Request / Grant pin may appear that both signals are active low. But in reality, Request signal goes low first (input to processor), and then the processor grants the request by outputting a low on the same pin.

Semiconductor memories are of two types: RAM and ROM. The semiconductor memories are arranged as two dimensional arrays of memory locations. For example, 1K X 8 memory chip contains 1024 locations and each of them is one byte wide. i.e. 1024 bytes of information can be stored in that chip. Each location should have an address. So, there has to be certain number of address lines on the memory chips. If we designate it as n, then n = log2N, where N is the number of locations that could be addresses in that chip. For 1K chip n would be 10, for 2K it is 11, for 4k it will be 13 etc. If a microprocessor has x address lines and if a RAM/EPROM IC is to be interfaced which has y lines (x > y), then we connect y lines from microprocessor to those of memory chip. Remaining x-y lines of microprocessor are used for address decoding. Main aim of this decoding circuit is to select one location for the address sent from microprocessor. The general procedure for interfacing static memory to 8086 is as follows: 1. Arrange the available memory chips so that they form a 16 – bit data bus and there should be a provision to access bytes as well as words. 2. Connect address lines, control signals like read, write of the microprocessor with those of memory chip. 3. Remaining address lines along with A0 and BHE are used for decoding the required chip select signals for odd and even banks. Absolute decoding is preferred even though we may have to go for linear decoding sometimes when an application demands. As far as possible, there should not be any windowing in memory map unless otherwise specified and try to avoid foldback. E1. Interface two 4K X 8 EPROMs and two 4K X 8 RAM chips with 8086. Select suitable maps. First we have to write the memory map fro the problem given. It will reveal the logic to be used for decoding circuit. Since the first instruction is fetched from FFFF0h after the microprocessor is reset, we will make that address to be present in EPROM and write the memory map as follows. And, to avoid windowing let us keep the locations to be present in the RAM as immediate addresses. Locations having addresses from FFFFFH to FE000H are allocated to EPROM1 and 2. Immediate address map FDFFFH to FD000H is allocated to RAM1 and 2. The line which is differentiating EPROM from RAM if A13. Let us use it along with A0 and BHE to identify odd and even banks

Since there is continuous address map, we can use a decoder to decode the chip select signals. The inputs for the decoder would be a13, A0 and BHE.

As the table shows, when the decoder output O0 is enabled it selects both even and odd banks in RAM. Then A0 and BHEcan be used accordingly to select only even or only odd bank. Similarly, EPROM is selected by O4. The complete Interface diagram is shown below:

E2: Interface two chips of 16K X 8 EPROMs and two chips of 32 X 8 RAM chips to 8086 microprocessor. Select the starting address of EPROM suitably, but the RAM address must start at 00000H. First let us write the memory map. If you observe the memory map, it shows that the address map is not contiguous. Hence we will use logic gates instead of decoder to design decoding logic.

E3: It is required to interface two chips of 32K X 8 ROM and four chips of 32K X 8 RAM with 8086 according to following map. ROM1 and 2: F0000H – FFFFFH, RAM1 and 2: D0000H – DFFFFH, RAM3 and 4: E0000H – EFFFFH The necessary memory map is shown below and Interface diagrams is

8255 Programmable Peripheral Interface and Interfacing

The 8255 is a widely used, programmable parallel I/O device. It can be programmed to transfer data under data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical (when multiple I/O ports are required). It is an important general purpose I/O device that can be used with almost any microprocessor. The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B, with the remaining 8 bits as Port C. The 8 bits of port C can be used as individual bits or be grouped into two 4 bit ports : CUpper (CU) and CLower (CL). The functions of these ports are defined by writing a control word in the control register. 8255 can be used in two modes: Bit set/Reset (BSR) mode and I/O mode. The BSR mode is used to set or reset the bits in port C. The I/O mode is further divided into 3 modes: mode 0, mode 1 and mode 2. In mode 0, all ports function as simple I/O ports. Mode 1 is a handshake mode whereby Port A and/or Port B use bits from Port C as handshake signals. In the handshake mode, two types of I/O data transfer can be implemented: status check and interrupt. In mode 2, Port A can be set up for bidirectional data transfer using handshake signals from Port C, and Port B can be set up either in mode 0 or mode 1.

Control Logic of 8255 RD(Read) : This signal enables the Read operation. When the signal is low, microprocessor reads data from a selected I/O port of 8255. WR(Write) : This control signal enables the write operation. RESET (Reset) : It clears the control registers and sets all ports in input mode. CS, A0, A1 : These are device select signals. is connected to a decoded address and A0, A1 are connected to A0, A1 of microprocessor.

BSR Mode of 8255

6.1.3 I/O Modes of 8255 Mode 0 : Simple Input or Output In this mode, Port A and Port B are used as two simple 8-bit I/O ports and Port C as two 4-bit I/O ports. Each port (or half-port, in case of Port C) can be programmed to function as simply an input port or an output port. The input/output features in mode 0 are : Outputs are latched, Inputs are not latched. Ports do not have handshake or interrupt capability. Mode 1 : Input or Output with handshake In mode 1, handshake signals are exchanged between the microprocessor and peripherals prior to data transfer. The ports (A and B) function as 8-bit I/O ports. They can be configured either as

input or output ports. Each port (Port A and Port B) uses 3 lines from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions. Input and output data are latched and Interrupt logic is supported. Mode 2 : Bidirectional Data Transfer This mode is used primarily in applications such as data transfer between the two computers or floppy disk controller interface. Port A can be configured as the bidirectional port and Port B either in mode 0 or mode 1. Port A uses five signals from Port C as handshake signals for data transfer. INTERFACING ANALOG TO DIGITAL DATA CONVERTERS The function of an A/D converter is to produce a digital word which represents the magnitude of some analog voltage or current. The specifications for an A/D converter are very similar to those for D/A converter. The resolution of an A/D converter refers to the number of bits in the output binary word. An 8-bit converter for example has a resolution of 1 part in 256. Accuracy and linearity specifications have the same meaning for an A/D converter as they do for a D/A converter. Another important specification for an ADC is its conversion time. This is simply the time it takes the converter to produce a valid output binary code for an applied input voltage. When we refer to a converter as high speed, we mean that it has a short conversion time. The analog to digital converter is treated as an input device by the microprocessor that sends an initialising signal to the ADC to start the analog to digital data conversation process. The start of conversion signal is a pulse of a specific duration. The process of analog to digital conversion is a slow process, and the microprocessor has to wait for the digital data till the conversion is over. After the conversion is over, the ADC sends end of conversion (EOC) signal to inform the microprocessor that the conversion is over and the result is ready at the output buffer of the ADC. These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and reading the digital output of the ADC are carried out by the CPU using 8255 I/O ports. The time taken by the ADC from the active edge of SOC pulse (the edge at which the conversion process actually starts) till the active edge of EOC signal is called as the conversion delay of the ADC. Or broadly speaking the time taken by the converter to calculate the equivalent digital data output from the instant of the start of conversion is called conversion delay. It may range any where from a few microseconds in case of fast ADCs to even a few hundred milliseconds in case of slow ADCs. A number of ADCs are available in the market, The selection of ADC for a particular application is done, keeping in mind the required speed, resolution range of operation, power supply requirements, sample and hold device requirements and the cost factors are considered. The available ADCs in the market use different conversion techniques for the conversion of analog signals to digital signals. Parallel converter or flash converter, Successive approximation and dual slope integration techniques are the most popular techniques used in the integrated ADC chips. Whatever may be the technique used for conversion, a general algorithm for ADC interfacing contains the following steps. 1. Ensure the stability of analog input, applied to the ADC. 2. Issue start of conversion (SOC) pulse to ADC. 3. Read end of conversion (EOC) signal to mark the end of conversion process. 4. Read digital data output of the ADC as equivalent digital output. It may be noted that analog input voltage must be constant at the input of the ADC right from the start of conversion till the end of conversion to get correct results. This may be ensured by a sample and hold circuit which samples the analog signal and holds it constant for a specified

time duration. The microprocessor may issue a hold signal to the sample and Hold circuit. If the applied input changes before the complete conversion process is over, the digital equivalent of the analog input calculated by the ADC may not be correct. ADC 0808/0809 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive approximation converters. Successive approximation technique is one of the fast techniques for analog to digital conversion. The conversion delay is 100 µs at a clock frequency of 640 kHz, which is quite low as compared to other converters. These converters do not need any external zero or full scale adjustments as they are already taken care of by internal circuits. These converters internally have a 3:8 analog multiplexer so that at a time eight different analog inputs can be connected to the chips. Out of these eight inputs only one can be selected for conversion by using address lines ADD A, ADD B and ADD C, as shown. Using these address inputs, multichannel data acquisition systems can be designed using a single ADC. The CPU may drive these lines using output port lines in case of multichannel applications. In case of single input applications, these may be hard wired to select the proper

input.

Interfacing ADC 0808

Digital to Analog Conversion DAC 0800 is an 8-bit Digital to Analog Converter chip. It comes in a 16 pin DIP. It has 8 digital inputs. DAC 0808 generates analog current output.Current to voltage converter is used externally. Current output is generated in about 100 milli seconds.

DMA Controller 8257

The Direct Memory Access or DMA mode of data transfer is the fastest amongst all the modes of data transfer. In this mode, the device may transfer data directly to/from memory without any interference from the CPU. The device requests the CPU (through a DMA controller) to hold its data, address and control bus, so that the device may transfer data directly to/from memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU. Intel’s 8257 is a four channel DMA controller designed to be interfaced with their family of microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access using local bus request input i.e. HOLD in minimum mode. In maximum mode of the microprocessor RQ/GT pin is used as bus request input. On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in maximum mode) from the CPU, the requesting devices gets the access of the bus, and it completes the required number of DMA cycles for the data transfer and then hands over the control of the bus back to the CPU. Internal Architecture of 8257 The internal architecture of 8257 is shown in figure. The chip support four DMA channels, i.e. four peripheral devices can independently request for DMA data transfer through these channels at a time. The DMA controller has 8-bit internal data buffer, a read/write unit, a control unit, a priority resolving unit along with a set of registers. Register Organization of 8257

The 8257 performs the DMA operation over four independent DMA channels. Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and terminal count register. There are two common registers for all the channels, namely, mode set register and status register. Thus there are a total of ten registers. The CPU selects one of these ten registers using address lines Ao-A3. Table shows how the Ao-A3 bits may be used for selecting one of these registers.

DMA Address Register Each DMA channel has one DMA address register. The function of this register is to store the address of the starting memory location, which will be accessed by the DMA channel. Thus the starting address of the memory block which will be accessed by the device is first loaded in the DMA address register of the channel. The device that wants to transfer data over a DMA channel, will access the block of the memory with the starting address stored in the DMA Address Register. Terminal Count Register Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit register isused for ascertaining that the data transfer through a DMA channel ceases or stops after the required number of DMA cycles. The low order 14-bits of the terminal count register are initialised with the binary equivalent of the number of required DMA cycles minus one. After each DMA cycle, the terminal count register content will be decremented by one and finally it becomes zero after the required number of DMA cycles are over. The bits 14 and 15 of this register indicate the type of the DMA operation (transfer). If the device wants to write data into the memory, the DMA operation is called DMA write operation. Bit 14 of the register in this case will be set to one and bit 15 will be set to zero. Table gives detail of DMA operation selection and corresponding bit configuration of bits 14 and 15 of the TC register.

Mode Set Register The mode set register is used for programming the 8257 as per the requirements of the system. The function of the mode set register is to enable the DMA channels individually and also to set the various modes of operation. The DMA channel should not be enabled till the DMA address register and the terminal count register contain valid information, otherwise, an unwanted DMA request may initiate a DMA cycle, probably destroying the valid memory data. The bits Do-D3 enable one of the four DMA channels of 8257. for example, if Do is ‘1’, channel 0 is enabled. If bit 4 is set, rotating priority is enabled, otherwise, the normal, i.e. fixed priority is enabled.

If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel. To enable the channel again, this bit must be reprogrammed. If the TC STOP bit is programmed to be zero, the channel is not disabled, even after the count reaches zero and further request are allowed on the same channel. The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without immediate software intervention between the two successive blocks. The channel 2 registers are used as usual, while the channel 3 registers are used to store the block reinitialisation parameters, i.e. the DMA starting address and terminal count. After the first block is transferred using DMA, the channel 2 registers are reloaded with the corresponding channel 3 registers for the next block transfer, if the update flag is set. The extended write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by activating them earlier, this is useful in interfacing the peripherals with different access times. If the peripheral is not accessed within the stipulated time, it is expected to give the ‘NOT READY’ indication to 8257, to request it to add one or more wait states in the DMA CYCLE. The mode set register can only be written into. Status Register The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the terminal count status for the four individual channels. If any of these bits is set, it indicates that the specific channel has reached the terminal count condition.

These bits remain set till either the status is read by the CPU or the 8257 is reset. The update flag is not affected by the read operation. This flag can only be cleared by resetting 8257 or by resetting the auto load bit of the mode set register. If the update flag is set, the contents of the channel 3 registers are reloaded to the corresponding registers of channel 2 whenever the channel 2 reaches a terminal count condition, after transferring one block and the next block is to be transferred using the autoload feature of 8257. The update flag is set every time, the channel 2 registers are loaded with contents of the channel 3 registers. It is cleared by the completion of the first DMA cycle of the new block. This register can only read. Data Bus Buffer, Read/Write Logic, Control Unit and Priority Resolver The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external system bus under the control of various control signals. In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the Ao-A3 lines and either writes the contents of the data bus to the addressed internal register or reads the contents of the selected register depending upon whether IOW or IOR signal is activated. In master mode, the read/write logic generates the IOR and IOW signals to control the data flow to or from the selected peripheral. The control logic controls the sequences of operations and

generates the required control signals like AEN, ADSTB, MEMR, MEMW, TC and MARK along with the address lines A4-A7, in master mode. The priority resolver resolves the priority of the four DMA channels depending upon whether normal priority or rotating priority is programmed. Signal Description of 8257 DRQo-DRQ3 : These are the four individual channel DMA request inputs, used by the peripheral devices for requesting the DMA services. The DRQo has the highest priority while DRQ3 has the lowest one, if the fixed priority mode is selected. DACKo-DACK3 : These are the active-low DMA acknowledge output lines which inform the requesting peripheral that the request has been honoured and the bus is relinquished by the CPU. These lines may act as strobe lines for the requesting devices. Do-D7: These are bidirectional, data lines used to interface the system bus with the internal data bus of 8257. These lines carry command words to 8257 and status word from 8257, in slave mode, i.e. under the control of CPU. The data over these lines may be transferred in both the directions. When the 8257 is the bus master (master mode, i.e. not under CPU control), it uses Do-D7 lines to send higher byte of the generated address to the latch. This address is further latched using ADSTB signal. the address is transferred over Do-D7 during the first clock cycle of the DMA cycle. During the rest of the period, data is available on the data bus.

IOR: This is an active-low bidirectional tristate input line that acts as an input in the slave mode. In slave mode, this input signal is used by the CPU to read internal registers of 8257.this line acts output in master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle.

IOW : This is an active low bidirection tristate line that acts as input in slave mode to load the contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it is a control output that loads the data to a peripheral during DMA memory read cycle (write to peripheral). CLK: This is a clock frequency input required to derive basic system timings for the internal operation of 8257. RESET : This active-high asynchronous input disables all the DMA channels by clearing the mode register and tristates all the control lines. Ao-A3: These are the four least significant address lines. In slave mode, they act as input which select one of the registers to be read or written. In the master mode, they are the four least significant memory address output lines generated by 8257. CS: This is an active-low chip select line that enables the read/write operations from/to 8257, in slave mode. In the master mode, it is automatically disabled to prevent the chip from getting selected (by CPU) while performing the DMA operation. A4-A7 : This is the higher nibble of the lower byte address generated by 8257 during the master mode of DMA operation. READY: This is an active-high asynchronous input used to stretch memory read and write cycles of 8257 by inserting wait states. This is used while interfacing slower peripherals. HRQ: The hold request output requests the access of the system bus. In the noncascaded 8257 systems, this is connected with HOLD pin of CPU. In the cascade mode, this pin of a slave is connected with a DRQ input line of the master 8257, while that of the master is connected with HOLD input of the CPU. HLDA : The CPU drives this input to the DMA controller high, while granting the bus to the device. This pin is connected to the HLDA output of the CPU. This input, if high, indicates to the DMA controller that the bus has been granted to the requesting peripheral by the CPU. MEMR: This active –low memory read output is used to read data from the addressed memory locations during DMA read cycles. MEMW : This active-low three state output is used to write data to the addressed memory location during DMA write operation. ADST : This output from 8257 strobes the higher byte of the memory address generated by the DMA controller into the latches. AEN: This output is used to disable the system data bus and the control the bus driven by the CPU, this may be used to disable the system address and data bus by using the enable input of the bus drivers to inhibit the non-DMA devices from responding during DMA operations. If the 8257 is

I/O mapped, this should be used to disable the other I/O devices, when the DMA controller addresses is on the address bus. TC: Terminal count output indicates to the currently selected peripherals that the present DMA cycle is the last for the previously programmed data block. If the TC STOP bit in the mode set register is set, the selected channel will be disabled at the end of the DMA cycle. The TC pin is activated when the 14-bit content of the terminal count register of the selected channel becomes equal to zero. The lower order 14 bits of the terminal count register are to be programmed with a 14-bit equivalent of (n-1), if n is the desired number of DMA cycles. MARK : The modulo 128 mark output indicates to the selected peripheral that the current DMA cycle is the 128th cycle since the previous MARK output. The mark will be activated after each 128 cycles or integral multiples of it from the beginning if the data block (the first DMA cycle), if the total number of the required DMA cycles (n) is completely divisible by 128. Vcc : This is a +5v supply pin required for operation of the circuit. GND : This is a return line for the supply (ground pin of the IC). Interfacing 8257 with 8086 Once a DMA controller is initialised by a CPU property, it is ready to take control of the system bus on a DMA request, either from a peripheral or itself (in case of memory-to memory transfer). The DMA controller sends a HOLD request to the CPU and waits for the CPU to assert the HLDA signal. The CPU relinquishes the control of the bus before asserting the HLDA signal.

Once the HLDA signal goes high, the DMA controller activates the DACK signal to the requesting peripheral and gains the control of the system bus. The DMA controller is the sole master of the bus, till the DMA operation is over. The CPU remains in the HOLD status (all of its signals are tristate except HOLD and HLDA), till the DMA controller is the master of the bus. In other words, the DMA controller interfacing circuit implements a switching arrangement for the address, data and control busses of the memory and peripheral subsystem from/to the CPU to/from the DMA controller.

8051 MICROCONTROLLER:

8-bit microcontroller

8-bit CPU,Reg A,Reg B 15-bit PC and Data Pointer(DPTR) 8-bit PSW 8-bit SP Internal ROM and EPROM (8751) Internal RAM of 256 bytes

Architecture of 8051:

Registers in 8051

Math Register

* indicates that each bit a of the register can be programmed.

Interrupt Register

Timer Control Register

Assembler- Assembly level language to Machine codeCompiler- High level language to Machine codeSimulator- software to simulate the function of a microcontrollerEmulator- Combination of software and hardware to simulate function of a microcontroller

Timer Counter Register

8051 Internal Data Memory

It has 256 byte of internal RAM

SFR MAP

F8

F0 b

E8

E0 ACC

D8

D0 PSW

C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2

C0

B8 IP

B0 IP3

A8 IE

A0 P2

98 SCON SBUF

90 P1

88 TCON TMOD TLO TLO THO TH1 T

80 PO SP DPL DPH PCON

These n in the 8052 microcontroller.

Addressing Modes:Ex: ADD A, #77 (immediate addressing) A=A + 77(decimal)

1) Immediate Addressing Mode: Where data is available in the instruction itself.

2) Bank Register Addressing: Add A, ROsince it has 4 different banks each bank each having 8 bytes and the register RO of which bank is selected by the SFR PSW.

PSW: RSI and RSO selects which bank is to be selected.

3)Direct Addressing Mode: Add A,80 A A+(Data of 80 in SFR)ie, A A + PO

4)Indirect Addressing Mode: Registers R0, R1, DPTR r used to store address of the 8-bit and 16-bit.

Add A, @ RO Indirect memory addressingA A + R0

5) Register Indirect Addressing Add A, @ DPTRIn this address in the DPTR may be internal or external memory address.Ex. MOV A,30HThis takes 2 instruction cycles ie, 24 clock cycles.MOV A,@ ROThis instruction takes only 1 instruction cycle ie, 12 clock cycles.

External Memory Access:

40 Pin DIP Package of 8051

How to latch 1 to P3 X ?This latching is done in the following process.

That to latch P3 to 1, first write to latch and load 1 into it. Hence the output of the gate is the alternate output function which latches the other functions.

8051 I/O port Structure Port 0 AD0- AD7 Port 1

This can be used as normal I/O port or address bus Mux switches between normal I/O port and address/data bus

This port is used for normal I/O port only

Pure bidirectional port Quasi bidirectional port

For external memory read operation,SFR PO is over written by FFH

While accessing 16-bit external memory

Port 2 (A8-A15) Port 3 I/O Port + Alternative function

Discussed in previous class

Port can be used as normal I/O port and address bus

While addressing 16-bit external memory, P2 SFR value remains unchanged.

ALL THE PORTS HAVE LIMITED CURRENT SOURCING CAPABILITY.

External Memory Access

ROM (Pragramming Memory) RAM CData

Always 16-bit address 8-bit or 16-bit address

Always external Memory is accessedIf PC > FFFH then ROM is accessed

If the address is stored in a 8-bit register then it points to 8-bit address MOV A,@RO

000-FFFH is internal Memory

1000-FFFFH is external Memory

access internal memory

For 16-bit addressMOV A, @ DPTR

How MOV A,@DPTR works

For 8-bit Memory address access, P2 Pins o/p the SFR register contents and helps in memory pages.

The higher order 8-bit address is taken the address available in the P2 SFSR and the lower order 8-bit address is

the data available in register RO.

Timer/Counter in 8051

8051 has two 16-bit Timer/counter registers. 8052 has these two plus one more:Timer 2. All thesecan be configured to operate either as times or event counters.In the ”Timer” function, the register is incremented every machine cycle. Now one can think of itas counting machine cycles (instruction cycles) and the clock rate is 1

12oscillator frequency (∵ one

instruction cycle = 12 clock cycles). In ”Counter” function, the register is incremented in response toa 1 to 0 transition at its corresponding external input pins, ie. T0, T1 or (in 8052)T2. In this function,the external inputs is sampled during S5P2 of every machine cycle. When the samples show a highin one cycle and a low in the next cycle, the count is incremented. The new count value appears inthe register during S3P1 of the cycle following the one in which the transition was detected. Sinceit takes 2 machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum countrate is 1/24 of the oscillator frequency.Timer 0 and Timer 1 have 4 operating nodes. Timer 2 in 8052 has 3 modes of operation: ”Capture”,”auto-reload” and ”bandrate generator”.

Timer mode control (TMOD) Special function Register

Gate C/T M1 M0 C/TGate M1 M0

Timer - 1 Timer - 0

7 6 5 4 3 2 1 0

Timer/Counter Control logic

to timerstages

osc .freq . -- 12d

CounterT1 /0 Input pin

TR1 /0 Bit in TCON

Gate bit in TMOD

INT1 /0 Input pin

Timer Mode-0

Setting timer x mode bits to 00 in the TMOD register results in using the THX register as a 8-bitcounter and TLX as a 5-bit register (lower bits). The upper 3-bits of TLX are indeterminate andshould be ignored. The timer overflow flag in TCON is set whenever THX goes from FFh to 00h.

PulseInput TLX 5 bits THX 8 bits TFX

Interrupt

Timer Mode-1

Mode-1 is similar to mode-0 except TLX is configured as a full 8-bit counter. When the mode bitsare set to 01 in TMOD.PulseInput TLX 8 bits THX 8 bits TFX

Interrupt

The Timer Control (TCON) Special Function Register

TF1 TR1 TF0 TR0 IT1IE1 IE0 IT0

7 6 5 4 3 2 1 0

TF1 → Timer 1 overflow flag. Set when timer rolls from all 1’s to all 0. Cleared when processorvectors to execute int. Since routine at 00/Bh

TR1 → Timer 1 run control bit. Set to 1 by program to enable time to count. Clear to 0 by program(TRO - for Timer 0)

Timer Mode-2

(Auto-reload feature) TLX is used as a 8-bit counter only. THX is used to hold a value that is loadedinto TLX everytime TLX overflows from FFh to 00h. The time flag is also set when TLX overflows.The mode shows auto reload feature where TLX will be initialized to the content of THX after TLXoverflows.PulseInput

TLX 8 bits

THX 8 bits

Reload TLX

TFXInterrupt

Timer Mode-3

Timer 1 in Mode-3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in Mode3 establishes TL0 and TH0 as two sperate counters.

PulseI/P

f/12

TRI Bitin TCON

TLO 8 bits

TH0 8 bits

TF0

TF1

Interrupt

Interrupt

Control bit TR1 and TF1 are used by Timer-0

Timer-1 can still be used in Mode-0,1 and 2 but no interrupt will be generated by Timer-1 whileTimer-0 is in Mode-3.

Timer 2

Like Timer-0 and 1, it can operate either as a timer or as a event counter.T2CON

TF2 EXF2 RCLK TCLK TR2EXEN2 C/T2 CP /RL2

7 6 5 4 3 2 1 0

This is selected by bits C/T2 in special function register T2CON. It has there operating modes:”Capture”, ”auto-load” and ”band rate generator”.

RCLK + TCLK CP /RL2 TR 2 Mode

0

0

1

x

0

1

x

x

1

1

1

0

16-bit Auto-reload

16-bit capture

Bandrate gen

off

Serial Interface:

The serial port is full duplex.SBUF → Special function Register.Mode - 0 Shift register mode.Serial data enters and exists through RXD. 8-bits are transmitted/recieved. Pin TXD is connected tothe internal shift frequency pulse source to supply shift pulses to external circuits. The shift frequencyor bandrate is fixed at 1/2 of the oscillator frequency.

Mode - 1 Standard UART10 bits are transmitted (through TXD) or recieved through (RXD), a start bit(0), 8 data bits (LSBfirst), and a stop bit(1). Once recieved, the stop bits goes into RB8 in special function register SCON.The band rate is variable.

1 2 3 4 5 6 7 8

StartBit

Data bits Minimumone stop bit

Idle state

Receiver samples data in center of bit times

Bit time =

Idle state

f

1

t

Mode - 2 Multiprocessor Mode.11 bits are transmitted through TXD or recieved through RXD, a start bit (0), 8 data bits (LSBfirst), a programmable 9th bit and a stop bit(1).On transmission, the 9th data bit (TB8 in SCON) can be assigned the value 0 or 1. Or, for example,the parity bit (P in the PSN) could be moved into TB8. On receive, the 9th bit goes into RB8 inSFR SCON, which the stop bit is ignored. The bandwidth is programmable to either 1/32 or 1/64 ofoscillator frequency.

fband =2SMOD

64fosc

Mode - 311 bits are transmitted through TXD or received through RXD: a start bit, 8 data bits (LSB first),a programmable 9th bit, and a stop bit (1). In fact, Mode 3 is same as Mode 2 in all respects exceptthe band rate. The band rate in Mode 3 is variable.

Serial Port Control Register

SCON

SM1 SM2 REN RB8TB8 TI RISM0

(MSB ) (LSB )

SM0 SMI MODE Description Band rate0 0 0 shift register fosc/120 1 1 8-bit UART Variable1 0 2 9-bit UART f/32, f/641 1 3 9-bit UART Variable

SM2 Enables multiprocessor communication in Mode 2 and 3.REN Enables serial reception.TB8 9th data bit that will be transmitted in Mode 2 and 3.RB8 9th data bit that was received. In mode-1, a SM2=0, RB8 is the stop bit thatwas received. In mode-0, RB8 is not used.T1 Transmit interrupt flagR1 Receive interrupt flag

The Power Mode Control (PCON) Special function reg.

PCONSMOD GF0GF1 PD IDL

7 6 5 4 3 2 1 0

fband =2SMOD

32× fosc

12 × [256 − TH1]

Timer-1 is used to generate band rate for mode-1 using overflow flag of the timer to determine theband frequency. Typically Timer-1 is used in mode-2 as an auto load 8-bit that generates the bandfrequency.If Timer-1 is not run in timer mode-2 then the band rate is

Fband =2SMOD

32× timer 1 overflow frequency

fclock = 11.0592MHzfband = 9600

TH1 = 256 −(

20

32× 11.0592 × 106

12 × 9600

)= 253 = 0FDG

Multiprocessor Communication

Mode 2 and 3 have a special provision for multiprocessor communication. In this mode, 9 data bitsare received/transmitted. The port can be programmed such that when the stop bit is received, theserial interrupt will be activated only if RB8=1. This feature is enabled by setting bit SM2 in SCON.A way to use this feature is given here.

8051

Master

Add 1

Slave 1

Add 2

Slave 2

8051

RxTx

RxTx

TxRx

Master communication withone slave at a time

When a master processor wants to send a data byte to a slave, the master sends the address of theslave first. There may be many slave processors. An address byte differs from a data byte in thatthe 9th bit is 1 in an address byte and 0 in a data byte. An address byte interrupts all slaves whenSM2=1. But a data byte does not interrupt the slaves if they have SM2=1. The address byte ischecked by each slave and the target/addressed slave clears its SM2 so that it can receive the data

byte. The slaves that are not addressed leave their SM2’s set and go on with their business, ignoringthe incoming data bytes. SM2 has no effect in mode 0, and in mode 1, it can be used to check thereliability of the stop bit. In mode 1, if SM2=1, then receive interrupt will not be activated unless avalid stop bit is received.

Interrupts

8051 provides 5 interrupt sources. The 8052 provides 6.

IE0 InterruptINT0

IT0

0

1

TF0 Interrupt

IE1INT1

IT1

0

1

Interrupt

InterruptTF1

TI

RI

TF2

EXF2

Interrupt

Interrupt

INT0 and INT1 are external interrupts and can be level triggered or edge triggered (negative) de-pending upon IT0/IT1 in TCON SFR.IT0 Set → falling edge triggered for INT0IT0 Cleared → low level triggered for INT0IE0/1E1 Interrupt 0/1 edge flag. Set by hardware when external interrupt edge detected. Clearedwhen interrupt processed.Timer 0 and Timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in theirrespective Timer/Counter register (except Timer 0 in Mode 3). When a timer interrupt is generated,the flag that generated it is cleared by on chip hardware when the interrupt service routine is vectorto. The serial port interrupt is generated by the logical OR of RI and TI. Neither of these flags iscleared by hardware when the interrupt service routine is vectored to. These have to be cleared bysoftware.All of the bits that generate interrupts can be set or cleared by software, with the same result asthough it had been cleared by hardware. That is, interrupts can be generated or pending interruptscan be canceled in software.Each of these interrupts can be individually enabled or disabled by setting or clearing bit in the SFRIE. IE contains a global disable bit, EA which disable all interrupts at once.

Interrupt Enable Register(IE)

EA ET2 ES EX1ET1 ET0 EX0

(MSB ) (LSB )

EA = 0 no interrupt is acknowledged.

= 1 each int source is individually enabled or disabled

ET2 = 0 disables Timer 2 overflow int

= 1 enables Timer 2 overflow int

ES = 0 Serial port int is disabled

= 1 Serial port int is enabled

ET1 = 0 Timer 1 overflow int is disabled

= 1 Timer 1 overflow int is enabled

EX1 = 0 External int 1 (INT1) is disabled.

= 1 External int 1 (INT1) is enabled.

ET0 = 0/1 Disables Timer 0 OF int

EX0 = 0/1 Disables/enables external int (INT0)

Priority structure

Each interrupt source can be individually programmed to one of two priority levels by setting orcleaning a bit in special function register IP. A low priority interrupt can itself be interrupted by ahigh priority interrupt, but not by another low priority interrupt. If two requests of different prioritylevels are received simultaneously, the request of higher priority level is serviced. If requests of samepriority level are received simultaneously, an internal polling sequence determines which request hasto be serviced. Thus within each priority level, there is a second priority structure determined by thepolling sequence, as follows:

Source Priority within level1. IE0 (Highest)2. TF0 ↓3. IE1 ↓4. TE1 ↓5. RI+TI ↓6. TF2+EXF2 (Lowest)

How the interrupts are handled Interrupt flags are sampled in S5P2 of each instruction cycle.The samples are polled during the following instruction cycle (machine cycle). If one of the flags was

in a set condition at S5P2 of the preceding cycle, the polling will find it and the interrupt system willgenerate an LCALL to the appropriate service routine, provided this hardware generated LCALL isnot blocked by any of the following conditions:

1. An interrupt of equal or higher priority level is already in progress.

2. The current polling is not the final machine cycle of the instruction in progress

3. The instruction in progress is RET1 or any write to IE or IP registers.

If an interrupt flag is a active but not being responded to for one of the above conditions, if the flagis not still active when the blocking condition is removed, the denied interrupt will not be serviced.This is because the interrupt flag once active but not serviced is not remembered. Every polling cycleis new

C1 C2 C3 C4 C5 C6

Int .goes active

Intlatched

Int arepolled

Long call to interrupt vectoraddress

InterruptServiceRoutine

After a interrupt is vectored to, some interrupt flags are cleared and some are not by hardware.For example: Serial port and Timer 2 interrupt flags are not cleared automatically. This has tobe done by user’s software. IEU and IE1 are cleared if the interrupts are transition activated.TF0 and TF1 are cleared by hardware generated LCALL pushes PC into the stack but not PSW.

Source Vector address

IE0 −→ 0003HTF0 −→ 000BHIE1 −→ 0013HTF1 −→ 001BH

RI+TI −→ 0023HTF2+EXF2 −→ 002BH

External InterruptINTO and INT1Level triggered or Transition triggered

(Low) (1-to-0 transition)IT0/IT1=0 IT0/IT1=1Low or high should be maintained at the pin for at least 12 clock cycles (1 machine cycle).Special function Register (IP) Interrupt Priority Register (IP)

PT2 PS PX1PT1 PT0 PX0

(MSB ) (LSB )

PT2 → Timer 2 1-high priority 0-Low priorityPS → Serial Port Interrupt 1-high priority 0-Low priorityPT1 → Timer 1 Interrupt 1-high priority 0-Low priorityPX1 → External Int. 0 1-high priority 0-Low priorityPT0 → Timer 0 Int. 1-high priority 0-Low priorityPX0 → External Int 1 1-high priority 0-Low priority

Software generated interruptsWhen any interrupt flag is set to 1 by any means, an interrupt is generated unless blocked. Thismeans that the program itself can cause interrupts of any kind to be generated by simply setting thedesired interrupt flag to 1 using program instruction.Example of interrupt UseSingle-Step operationThe following program enables simple step operationJNB P3.2, FDHJB P3.2, FDHRETIResetNon-maskable InterruptHolding RST pin high for at least 2 machine cycles while the osc is running.After RST is made lowPC ← 0000HSP ← 07HPostlatches ← FFHSBUF ← XXAll other SFR ← 00RAM content is not changed.

Power-on ResetWhen power is switched on (Vcc), the capacitor behaves as a short circuit and RST pin remains highfor considerable amount of time to enable the micro controller to go into RESET mode.

Vcs

8051

VccFµ10

Ωk2.8

RST

Vcc

Power-saving modes of operationOften, power saving becomes important for microcontroller-based applications.The CHMOS versionof 8051 provides reduced power modes of operation as a standard feature.CHMOS → (Complementary High density MOS)- A chip with high density of CMOS transistors.CHMOS Power reduction modes CHMOS version has two power-reducing modes, idle and powerdown. The internal circuitry which implements these features is given below.

osc

XTAL2 XTAL1

Clock

IN

PD

InterruptInternal PortTImer Port

CPU

Idle and power down modes are activated by setting the corresponding bits (IDL and PD respectively)in PCON special function register.

GF0GF1 PD IDL

(MSB ) (LSB )

SMODNot bitaddressable

PCON87H

PD - Power down bits. Setting this bit activates power down operationIDL - Idle mode bit. Setting this bit activates idle mode operation.

Idle ModeAn instruction that sets PCON0 causes that to be the last instruction executed before going intothe idle mode. In the idle mode, the internal clock signal is gated off to the CPU, but not to theinterrupt, Timer and Serial port functions. The CPU status is preserved entirely. SP,PC,PSW,Acc,and all other registers maintain thier data during the idle mode. The port pins hold their logicalstatus they had at the time idle was activated. ALE and PSEN are hold at logic high levels.There are two ways to terminate idle. Activation of any enabled interrupt will cause PCON0 to becleared by hardware, terminating the idle mode. After RET1 is executed, the next instruction startsfrom the one following the instruction which enabled the idle mode.The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normaloperation or during the idle mode. For example, an instruction that activated idle can also set andor both flags. When idle is terminated by an interrupt, the ISR can examine the flag bits.The other way of terminating the idle mode is with a hardware reset.(Reset should be high for two ma-chine cycle or 24 clock cycles). The signal at the RST pin clears IDL bit directly and asynchronously.At this time the CPU resumes the program execution from where it left off; that is , at the instructionfollowing the one that involved idle mode. Two to three machine cycles should be executed beforethe internal reset algorithm takes control.Power down modeAn instruction that sets PCON.1 causes that to be the last instruction executed before going into thepower down more. In the power down mode, the on-chip oscillator is stopped. With the clock frozen,all functions are stopped, but the on-chip RAM and special function register are held. The port pinsoutput the values held by thier respective SFRs, ALE and PSEN output.The only exit from Power down mode of operation in by a hardware reset. Reset redefines all SFRs,but does not change the on-chip RAM.Vcc may be reduced to as low as 2V during Power down mode. However Vcc should be restored to therated value and allow clock to stabilize (≤ 10ms)before the Power down mode is exited, ie, hardwareReset is pressed.

8051 Instruction Set

Some notes

Rn Register R0-R7 of the currently selected register bank.

direct 8-bit internal data location address(Internal data with address 0-127 or SFR)

@Ri 8-bit internal Data RAM location addressed

data 8-bit constant included in instruction(immediate 8-bit data)

data 16 16-bit immediate data included in the instruction.

add 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same2k byte page of Program Memory as the first byte of the following instruction.

addr 16 16-bit destination address. Used by LCALL and LJUMP. A branch anywhere within 64kbyte of Program Memory space.

rel Signed (2’s complement) 8-bit offset byte used by SJUMP and all conditional jumps. Range is-128 to +127 bytes relative to first byte of the following instruction

bit Direct addressed bit in internal RAM or SFR.

Arithmetic Instructions

Mnemonics Description Bytes Instruction CyclesADD A,Rn A ← A + Rn 1 1ADD A,direct A ← A + Direct 2 1ADD A,@Ri A ← A + @Ri 1 1ADD A,data A ← A+data 1 1ADDC A,Rn A ← A+ Rn+C bit 1 1ADDC A, direct A ← A+(direct)+C bit 2 1ADDC A,@Ri A ← A+@Ri+C bit 1 1ADDC A,data A ← A+data+C-bit 2 1SUBB A,Rn A ← A-Rn-C-bit 1 1SUBB A,direct A ← A-(direct)-C-bit 2 1SUBB A,@Ri A ← A-@Ri-C-bit 1 1SUBB A,data A ← A-data-C-bit 2 1INC A A ← A+1 1 1INC Rn Rn ← Rn+1 1 1INC direct direct ←(direct)+1 2 1INC @Ri @Ri ←@Ri+1 1 1DEC A A ← A-1 1 1DEC Rn Rn ← Rn-1 1 1DEC direct direct ←(direct)-1 2 1DEC @Ri @Ri ← @Ri-1 1 1INC DPTR DPTR ← DPTR+1 1 2MUL AB A ← lowbyte (A*B) 1 4

B ← highbyte (A*B)DIV AB A ← quotient (A/B) 1 4

B ←remainder (A/B)DA A decimal adjust acc 1 1

Logical Instructions

Mnemonics Description Bytes Instruction CyclesANL A,Rn A ← A.Rn 1 1ANL A,direct A ← A.Direct 2 1ANL A,@Ri A ← A.@Ri 1 1ANL A,data A ← A.data 2 1ANL direct,A (direct) ← (direct)A 2 1ANL direct, data (direct) ← (direct).data 3 2ORL A,Rn A ← A+Rn 1 1ORL A,direct A ← +(direct) 2 1ORL A,@Ri A ← A+@Ri 1 1ORL A,data A ← A+data 2 1ORL direct,A (direct) ← (direct)+A 2 1ORL direct,data (direct) ← (direct)+data 3 2XRL A,Rn A ← A⊕ Rn 1 1XRL A,direct A ← A⊕ (direct) 2 2XRL A,@Ri A ← A⊕ @ Ri 1 1XRL A,data A ← A⊕ data 2 1XRL direct,A A ← direct ⊕ A 2 1XRL direct,data direct ← direct⊕ data 3 2CLR A A ← 00H 1 1CPL A A ← A 1 1RL A Rotate Left 1 1RLC A Rotate left through carry 1 1RR A Rotate right 1 1RRC A Rotate right through carry 1 1SWAP A Swap nibbles within the ACC 1 1

Data transfer Instructions

Mnemonics Description Bytes Instruction CyclesMOV A, RnMOV A, directMOV A, @RiMOV A, dataMOV Rn, AMOV Rn, directMOV Rn, dataMOV direct, AMOV direct, RnMOV direct, directMOV direct, @RiMOV direct, dataMOV direct, AMOV @ Ri, AMOV @ Ri, directMOV @ Ri, dataMOV DPTR,data16 AMOV A, @A+DPTR Code byte move to A

relative to DPTRMOV A, @A+PC Code byte move to A

relative to PCMOVX A, @Ri External data memory

move to A (8-bit addr)MOVX A, @DPTR External data memory

move to A (16-bit addr)MOVX @Ri, A Move A to ext data

memory (8-bit addr)MOVX @DPTR, A Move A to ext data

memory (16-bit addr)PUSH directPOP directXCH A, RnXCH A, directXCH A, @RiXCHD A, @Ri

Bit Operations / Jump instructions

Mnemonics Description Bytes Instruction CyclesCLR C Carry ← 0CLR bit bit ← 0SETB C Carry ← 1SETB bit bit ← 1CPL C C ← C

CLR bit bit ← bitANL C,bit C ← C.bit

ANL C, /bit C ← C.bitORL C,bit C ← C+bit

ORL C,/bit C ← C + bitMOV C,bit C ← bitMOV bit, C bit ← CJC rel Jump if C=1JNC rel Jump if C=0JB bit, rel Jump if bit = 1JNB bit, rel Jump if bit = 0JBC bit, rel Jump if b=1 and b ←0ACALL addr11 Absolute jumpLCALL addr16 Long jumpRET Return from subroutineRET1 Return from interruptAJUMP addr11 Absolute jump 2 2LJUMP addr16 Long jump 3 2SJMP rel Short jumpJMP @ A+ DPTR Jump relative to DPTRJZ relJNZ relCJNE A, direct, rel Compare with Acc and

jump if not equalCJNE A, data, relCJNE Rn,data, relCJNE @Ri,data, relDJNZ Rn, rel Decrementreg and jump if not 0DJNZ direct, rel

Direct bit addressing

Values between 0 and 127 (00H and 7FH) define bits in a block of 16 bytes of on-chip RAM betweenaddresses 20H-2FH. They are numbered consecutively from the lowest-order bytes lowest order bitthrough the highest order bit.Bit addresses between 128 and 255 (80H and 0FFH) correspond to bits in a number of special functionregisters mostly used for I/O or peripheral device control. These positions are numbered with adifferent scheme than RAM. The five high-order address bits match those of the registers own address

while the three low-order bits identifies the bit position within that register.

External Addressing using MOVX and MOVE

A Reg

R0 or R1

DPTR + A

PC + A

MOVX @ RT

MOVX @ DPTR

MOVC A, @ A + DPTR

MOVC A,@ A + PC

Read ReadWrite

ExtRAM Int &

ExtRAM

DPTR

Jump and Call Program Range

Relative Range:

Jump that replaces the program counter content with a new address that is greater than the ad-dress of the instruction following the jump by 127 or less than the address of the instruction followingjump by 128 are called relative jumps. The address following the jump is used to calculate the relativejump because the PC is incremented to the next instruction before the current instruction is extended.

Relative jump has two advantages. First, only 1 byte of data (2’s complement) need to be speci-fied for jumping ahead(positive range 0-127) or jumping back (negative range -128). Specifying only1 byte saves program bytes and speeds up program execution. Second, the program that is writtenusing relative jumps can be relocated anywhere in the program namely without reassembling the codeto generate absolute addresses.

The disadvantage of relative jump is the short jump range (-128 to 127). This can be problem-atic in large programs where multiple relative jump may be require if higher jump range is required.Instructions using relative range jump are SJMP rel, and all conditional jumps.

Short Absolute Range:

Short Absolute range makes use of the concept of dividing memory into logical divisions called pages.Program memory may be regarded as one continuous stretch of addresses from 0000H to 0FFFFH orit can be divided into a series of pages of any convenient binary size.

The 8051 program memory is arranged on 2k byte pages giving a total of 32 (20H) pages. The

hexadecimal address of each page is shown in the following table.

Page Address Range Page Address Range00 0000 - 07FF 10 8000 - 87FF01 0800 - 0FFF 11 8800 - 8FFF02 1000 - 17FF 12 9000 - 97FF03 1800 - 1FFF 13 9800 - 9FFF04 2000 - 27FF 14 A000 - A7FF05 2800 - 2FFF 15 A800 - AFFF06 3000 - 37FF 16 B000 - B7FF07 3800 - 3FFF 17 B800 - BFFF08 4000 - 47FF 18 C000 - C7FF09 4800 - 4FFF 19 C800 - CFFF0A 5000 - 57FF 1A D000 - D7FF0B 5800 - 5FFF 1B D800 - DFFF0C 6000 - 67FF 1C E000 - E7FF0D 6800 - 6FFF 1D E800 - EFFF0E 7000 - 77FF 1E F000 - F7FF0F 7800 - 7FFF 1F F800 - FFFF

It can be seen that the upper 5 bits of the program counter hold the page number and the lower 11bits of the program counter hold the address within each page. Thus an absolute address is formedby taking page number of the instruction following the branch and attaching the absolute page rangeaddress of 11 bits to it to form the 16-bit address.

Difficulty is encountered when the next instruction (the instruction following the jump instruction)starts at X800H or X000H. This places the jump or call address on the same page as the next in-struction. This does not give rise to any problem on forward jump, but results in error if the branchis backward in the program. This should be checked by assembler and the user should be instructedto relocate the program suitably.

Short absolute range jump is also relocatable as the relative jump. Instructions using short abso-lutes range areACALL addr 11AJMP addr 11

Long Absolute Jump:

Address that can access the entire program from 0000H to FFFFH use long-range addressing. Longrange addresses require more bytes of code to specify and relocatable only at the beginning of 64 Kbyte pages. Since the normal code memory is only 64k bytes, the program must be reassembled everytime a long-range address changes and then branches are not generally relocatable.Instructions using long absolute range areLCALL addr 16LJMP addr 16JMP @ A+DPTR

Example of Conditional Jump

Org 0100H

Loop: MOV A, 10HMOV RO, A

ADDA: ADD A, ROJNC ADDA

MOV A, 10HADDR: ADD A,RO

JNB 0D7H, ADDRJBC 0D7H, LOOP

Example of External DataORG OMOV RO,043HMOV A, 12MOVX @RO, AMOVX A, 34MOVX A, @RO

Character transmission using a time delay

A program called Senddata takes the character in A register, transmit it, delays for transmission time,and then returns to the calling program. Time 1 must be used to set the bandrate, which is 2400

band in this program. The delay for one character is10

2400sec = 0.00416s or 4.16msec. The software

delay of 5msec is used. Time 1 generates a bandrate close to 2400. Using a 12 MHz crystal, the reloadvalue is 256− 12× 106/(32× 12× 2400), which is 242.98 or 243. This gives rise to an actual bandrateof 2404. SMOD is programmed to be 0.; Send data, using a 12 Mhz Crystal for VART timing.; 2400 nominal band rate fir an actual band rate of 2404.; Delay between characters for 5 msec.

EQU BAUDNUM, 0F3HEQU DELAY, 0A6HEQU DLYLSB, 05HEQU DLYMSB, 00H

ORG 0000HANL PCON, 7FHANL TMOD, 3FHORL TMOD, 20HMOV THI, BAUDNUMSETB TRIMOV SCON, 40H

XMIT: MOV SBUF, ’A’ACALL XMITTIMESJMP XMIT

XMITTIME: MOV A, DLY LSBMOV B, DLY MSBACALL SOFTIMERET

SOFTIME: PUSH 07HPUSH ACCORL A,BCJNE A, 00H, OKPOP ACCSJMP DONE

OK: POP ACC

8031: No on chip program memory128 KB of on chip RAM

8032: No ROM, 256KB on chip RAM8051: 4K byte of Masked ROM (factory programmable)

128 KB of on chip RAMUpto 12 or 16 MHz

8052: 8K byte of ROM, 256Kb RAM8751: 4K byte of EPROM (UV Erasable)

Upto 12 or 16 MHzATMELAT 89C51: 4K byte of Reprogrammable flash memory

128K byte of RAM(on-chip)From 0-24MHz

Interrupt driven data reception

BAUDNUM EQU 0F3HORG 0000HSJUMP OVER

ORG 0023H

RECEIVE: CLR RIMOV PI, SBUFRETI

Gate C/T M1 M0 Gate C/T M1 M0

10

TMOD Register

OVER: ANL PCON, 7FH ; Set SMOD=0ANL TMOD, 0FH ; Alter Timer=1 conf onlyORL TMOD, 20H ; Timer 1 in mode -2MOV TH1, BAUDNUM ; Reload valueSETB TR1, ; Run Timer - 1MOV SCON, 40H ; Serial Mode - 1SETB REN, ; Enable serial receptionORL IE, 90H ; Enable Interrupt

WAIT: SJMP WAIT, ; Wait for recieving dataEND

Interrupt driven character transmissionBAUDNUM EQU 0F3HORG 0000HSJMP OVER

SERIAL CLR TIMOV SBUF,’A’RET1

OVER: ANL PCON,7FH ; SMOD=0ANL PCON,7FH ; SMOD=0ANL TMOD,0FH ;ORL TMOD,20H ; Timer-1 in mode - 2MOV TH1,BAUDNUM ; Reload valueSETB TR1, ; Rum Timer-1MOV SCON,40H ; Serial mode-1ORL IE,90H ; Enable serial intMOV SBUF,’A’ ; Send data

WAIT: SJMP WAIT,END