1

EKT 441MICROWAVE COMMUNICATIONS

CHAPTER 6:MICROWAVE AMPLIFIERS

2

INTRODUCTION

Most RF and microwave amplifiers today used transistor devices such as Si or SiGe BJTs, GaAs HBTs, GaAs or InP FETs, or GaAs HEMTs.

Microwave transistor amplifiers are rugged, low cost, reliable and can be easily integrated in both hybrid an monolithic integrated circuitry.

3

General Amplifier Block Diagram

...33

221 TOHtvatvatvatv iiio

Input and output voltage relation of the amplifier can be modeled simply as:

Vcc

PLPin

The active component

vi(t)vs(t)

vo(t)

DC supply

ZLVs

Zs AmplifierInput MatchingNetwork

Output MatchingNetwork

ii(t)

io(t)

4

Amplifier Classification

Amplifier can be categorized in 2 manners. According to signal level:

Small-signal Amplifier. Power/Large-signal Amplifier.

According to D.C. biasing scheme of the active component: Class A. Class B. Class AB. Class C.

There are also other classes, such as Class D (D stands fordigital), Class E and Class F. These all uses the transistor/FET asa switch.

Our approach in this chapter

5

Small-Signal Versus Large-Signal Operation

ZL

Vs

Zs

Sinusoidal waveform

Usually non-sinusoidal waveform

Large-signal: ...23

221 TOHtvatvatvatv iiio

Nonlinear

Small-signal: tvatv io 1Linear

vo(t)

vi(t)

6

Small-Signal Amplifier (SSA) All amplifiers are inherently nonlinear. However when the input signal is small, the input and output

relationship of the amplifier is approximately linear.

This linear relationship applies also to current and power. An amplifier that fulfills these conditions: (1) small-signal operation (2)

linear, is called Small-Signal Amplifier (SSA). SSA will be our focus. If a SSA amplifier contains BJT and FET, these components can be

replaced by their respective small-signal model, for instance the hybrid-Pi model for BJT.

tvaTOHtvatvatvatv iiiio 13

32

21 ...

When vi(t)0 (< 2.6mV) tvatv io 1 (1.1)Linear relation

7

Example 1.1 - An RF Amplifier Schematic (1)

ZLVs

Zs AmplifierInput MatchingNetwork

Output MatchingNetwork

DC supply

LL3

R=L=100.0 nH

LL2

R=L=100.0 nH

RRD1R=100 Ohm

CCD1C=0.1 uF

CCD2C=100 pF

PortVCCNum=3

LL4

R=L=12.0 nH

CC2C=0.68 pF

CCc1C=100.0 pF

RRB2R=1.5 kOhm

RRB1R=1 kOhm

LLC

R=L=100.0 nH

RRCR=470 Ohm

PortInputNum=1

PortOutputNum=2L

L1

R=L=4.7 nH

CC1C=3.3 pF

CCc2C=100.0 pF

pb_phl_BFR92A_19921214Q1

RF power flow

8

Typical RF Amplifier Characteristics

To determine the performance of an amplifier, the following characteristics are typically observed.

1. Power Gain. 2. Bandwidth (operating frequency range). 3. Noise Figure. 4. Phase response. 5. Gain compression. 6. Dynamic range. 7. Harmonic distortion. 8. Intermodulation distortion. 9. Third order intercept point (TOI).

Important to small-signalamplifier

Important parameters oflarge-signal amplifier(Related to Linearity)

9

Power Gain

For amplifiers functioning at RF and microwave frequencies, usually of interest is the input and output power relation.

The ratio of output power over input power is called the Power Gain (G), usually expressed in dB.

There are a number of definition for power gain as we will see shortly. Furthermore G is a function of frequency and the input signal level.

dB log10 PowerInput PowerOutput

10

GPower Gain (1.2)

10

Why Power Gain for RF and Microwave Circuits? (1)

Power gain is preferred for high frequency amplifiers as the impedance encountered is usually low (due to presence of parasitic capacitance).

For instance if the amplifier is required to drive 50Ω load the voltage across the load may be small, although the corresponding current may be large (there is current gain).

For amplifiers functioning at lower frequency (such as IF frequency), it is the voltage gain that is of interest, since impedance encountered is usually higher (less parasitic).

For instance if the output of IF amplifier drives the demodulator circuits, which are usually digital systems, the impedance looking into the digital system is high and large voltage can developed across it. Thus working with voltage gain is more convenient.

Power = Voltage x Current

11

Why Power Gain for RF and Microwave Circuits? (2)

Instead on focusing on voltage or current gain, RF engineers focus on power gain.

By working with power gain, the RF designer is free from the constraint of system impedance. For instance in the simple receiver block diagram below, each block contribute some power gain. A large voltage signal can be obtained from the output of the final block by attaching a high impedance load to it’s output.

LO

IF Amp.BPF

LNABPF

RF Portion(900 MHz)

IF Portion(45 MHz)

RF signalpower

1 W

15 W

IF signalpower

75 W

7.5 mW

400Ω

t

v(t) 4.90 V

RV

averageP 2

2

12

Harmonic Distortion (1)

ZL

Vs

Zs

When the input driving signal issmall, the amplifier is linear. Harmonic components are almost non-existent.

Harmonics generation reduces the gainof the amplifier, as some of the outputpower at the fundamental frequency isshifted to higher harmonics. This result in gain compression seen earlier!

ff1 harmonics

ff1 2f1 3f1 4f10

Small-signaloperationregion

Pout

Pin

13

Harmonic Distortion (2)

ZL

Vs

Zs

When the input driving signal istoo large, the amplifier becomesnonlinear. Harmonics areintroduced at the output.

Harmonics generation reduces the gainof the amplifier, as some of the outputpower at the fundamental frequency isshifted to higher harmonics. This result in gain compression seen earlier!

ff1

f

harmonics

f1 2f1 3f1 4f10

Pout

Pin

14

Power Gain, Dynamic Range and Gain Compression

Dynamic range (DR)

1dB compressionPoint (Pin_1dB)

Saturation

DeviceBurnout

Ideal amplifier

1dBGain compressionoccurs here

Noise Floor

-70 -60 -50 -40 -30 -20 -10 0 10

Pin

(dBm)20

Pout

(dBm)

-20

-100

10

2030

-30

-40

-50

-60

Power gain Gp = Pout(dBm) - Pin(dBm)= -30-(-43) = 13dB

Linear RegionNonlinear Region

Pin Pout

Input and output at same frequency

15

Bandwidth

Power gain G versus frequency for small-signal amplifier.

f / Hz0

G/dB3 dB

Bandwidth

Po dBm

Pi dBm Po dBm

Pi dBm

16

Intermodulation Distortion (IMD)

...33

221 TOHtvatvatvatv iiio

tvi tvo

ignored

ff1 f2

|Vi|

These are unwanted components, caused by the term 3vi

3(t), which falls in the operating bandwidth of the amplifier.

ff1-f2

2f1-f2 2f2-f1

f2f1 2f1f1+f2 2f2

3f1 3f2

2f1+f2 2f2+f1

|Vo|IMD

Operating bandwidthof the amplifier

Two signals v1, v2 with similar amplitude, frequencies f1 and f2 near each other

Usually specified in dB

17

Noise Figure (F)

Vs

• The amplifier also introduces noise into the output in addition to the noise from the environment.• Assuming small-signal operation.

Noise Figure (F)= SNRin/SNRout

• Since SNRin is always larger than SNRout, F > 1 for an amplifier which contribute noise.

SNR:Signal to NoiseRatio

Smaller SNRin

Larger SNRout

Zs

ZL

18

Power Components in an Amplifier

ZLVs

Zs Amplifier

Vs

Zs

ZLZ1

Z2

VAmp

+

-

PAoPL

PRo

PAs

PRs

Pin

2 basic source-load networksApproximate

Linear circuit

19

Power Gain Definition

From the power components, 3 types of power gain can be defined.

GP, GA and GT can be expressed as the S-parameters of the amplifier and the reflection coefficients of the source and load networks. Refer to Appendix 1 for the derivation.

AsL

T

AsAo

A

inL

p

PPG

PP

G

PPG

powerInput Availableload todeliveredPower Gain Transducer

powerInput AvailablePower load AvailableGain Power Available

Amp. power toInput load todeliveredPower Gain Power

The effective power gain

(2.1a)

(2.1b)

(2.1c)

20

Naming Convention

ZLVs

Zs Amplifier

2 - port Network

1 2

SourceNetwork

LoadNetwork

s L

2221

1211ssss

In the spirit of high-frequency circuit design, where frequency responseof amplifier is characterizedby S-parameters andreflection coefficient isused extensivelyinstead of impedance, power gain can be expressedin terms of these parameters.

21

TWO-PORT POWER GAIN

Figure 7.1: A two port network with general source and load impedance.

22

Power Gain Definition

From the power components, 3 types of power gain can be defined.

GP, GA and GT can be expressed as the S-parameters of the amplifier and the reflection coefficients of the source and load networks. Refer to Appendix 1 for the derivation.

AsL

T

AsAo

A

inL

p

PPG

PP

G

PPG

powerInput Availableload todeliveredPower Gain Transducer

powerInput AvailablePower load AvailableGain Power Available

Amp. power toInput load todeliveredPower Gain Power

The effective power gain

(2.1a)

(2.1b)

(2.1c)

23

TWO-PORT POWER GAIN

Power Gain = G = PL / Pin is the ratio of power dissipated in the load ZL to the power delivered to the input of the two-port network. This gain is independent of Zs although some active circuits are strongly dependent on ZS.

Available Gain = GA = Pavn / Pavs is the ratio of the power available from the two-port network to the power available from the source. This assumes conjugate matching in both the source and the load, and depends on ZS but not ZL.

Transducer Power Gain = GT = PL / Pavs is the ratio of the power delivered to the load to the power available from the source. This depends on both ZS and ZL.

If the input and output are both conjugately matched to the two-port, then the gain is maximized and G = GA = GT

24

TWO-PORT POWER GAIN

2221212221212

2121112121111

VSVSVSVSV

VSVSVSVSV

L

L

0

0

22

211211

1

1

1 ZZZZ

SSSS

VV

in

in

L

Lin

From the definition of S parameters:

[7.1a]

[7.1b]

Eliminating V2- from [7.1a]:

[7.2]

0

0

11

211222

2

2

1 ZZZZ

SSSS

VV

out

out

S

Sout

[7.3]

25

TWO-PORT POWER GAIN

in

inin ZZ

11

0

inS

SSVV

1

121

By voltage division:

ininS

inS VVV

ZZZVV

11111

Using:

Solving for V1+:

[7.4]

[7.5]

[7.6]

26

TWO-PORT POWER GAIN

22

2

0

22

10

11

18

12

1in

inS

SSinin Z

VV

ZP

22

22

22221

0

2

222

2221

0

2

1

11

118

1

12

inSL

SLS

L

LL

S

SZ

V

S

SZ

VP

2

0

2

2 12 LL Z

VP

The average power delivered to the network:

The power delivered to the load is:

[7.7]

[7.8]

[7.9]

27

TWO-PORT POWER GAIN

2

222

2221

11

1

Lin

L

in

L

S

SPPG

2

2

0

2

1

18

S

Ssinavs Z

VPP

Sin

outL

outL

inSout

SoutsLavn

S

SZ

VPP

22

22

22221

0

2

11

118

The power gain can be expressed as:

The available power from the source:

The available power from the network:

[7.10]

[7.11]

[7.12]

28

TWO-PORT POWER GAIN

2211

2221

0

2

11

18

outS

Ssavn

S

SZ

VP

2

112

2221

11

1

Sout

S

avs

avnA

S

SPPG

22

22

22221

11

11

inSL

LS

avs

LT

S

SPPG

The power available from the network:

The available power gain:

The transducer power gain:

[7.13]

[7.14]

[7.15]

29

Summary of Important Power Gain Expressions and the Gain Dependency Diagram

s

s

L

L

ss

ss

11

22

2

22

11

1

1

1

2

12

22

2221

11

1

L

LP

s

sG

2

22

11

221

2

11

1

s

sA

s

sG

21

222

2221

2

11

11

sL

sLT

s

sG

Note:All GT, GP, GA, 1 and 2

depends on the S-parameters.

(2.2a)

21122211ssss

(2.2b)

(2.2c)

(2.2d)

(2.2e)

s L

1 2

GA GP

GT

2221

1211ssss

The Gain Dependency Diagram

30

TWO-PORT POWER GAIN

221SGT

A special case of the transducer power gain occurs when both input and output are matched for zero reflection (in contrast to conjugate matching).

Another special case is the unilateral transducer power gain, GTU where S12=0 (or is negligibly small). This nonreciprocal characteristic is common to many practical amplifier circuits. Γin = S11 when S12 = 0, so the unilateral transducer gain is:

2

222

11

22221

11

11

inS

LSTU

SS

SG

[7.16]

[7.17]

31

TWO-PORT POWER GAIN

Figure 7.2: The general transistor amplifier circuit.

32

TWO-PORT POWER GAIN

222

2

2210

2

2

1

1

1

1

L

LL

Sin

SS

SG

SG

G

The separate effective gain factors:

[7.18a]

[7.18b]

[7.18c]

33

TWO-PORT POWER GAIN

If the transistor is unilateral, the unilateral transducer gain reduces to GTU = GSG0GL , where:

222

2

2210

211

2

1

1

1

1

L

LL

S

SS

SG

SG

SG

[7.19c]

[7.19b]

[7.19a]

34

Example 1 – Familiarization with the Gain Expressions

An RF amplifier has the following S-parameters at fo: s11=0.3<-70o, s21=3.5<85o, s12=0.2<-10o, s22=0.4<-45o. The system is shown below. Assuming reference impedance (used for measuring the S-parameters) Zo=50, find:

(a) GT, GA, GP. (b) PL, PA, Pinc.

Amplifier

2221

1211ssss

ZL=73

40

5<0o

35

Example 1 Cont... Step 1 - Find s and L . Step 2 - Find 1 and 2 . Step 3 - Find GT, GA, GP. Step 4 - Find PL, PA.

151.0146.022

1111 j

L

Ls

Ds

358.0265.0111

222 j

sssDs

111.0

os

osZZZZ

s 187.0

oL

oLZZZZ

L

742.1311

12

1

2

22

22

21

L

L

ss

G

739.1411

1

22

211

221

2

s

sA

s

sG

562.1211

11

21

222

2221

2

sL

sLT

s

sG

WPs

sZ

VA 078.0Re8

2

WZPP osZZsZZ

Ain 0714.012

11

WPGP inPL 9814.0

Try to derive These 2 relations

Again note that this is ananalysis problem.

36

STABILITY

In the circuit of Figure 7.2, oscillation is possible if either the input or output port impedance has the negative real part; this would imply that |Γin|>1 or |Γout|>1.

Γin and Γout depends on the source and load matching networks, the stability of the amplifier depends on ΓS and ΓL as presented by matching networks.

Unconditionally stable: The network is unconditionally stable if |Γin| < 1 and |Γout| < 1 for all passive source and load impedance (ex; |ΓS| < 1 and |Γ| < 1).Conditionally stable: The network is conditionally stable if |Γin| < 1 and |Γout| < 1 only for a certain range of passive source and load impedance. This case also referred as potentially unstable.

The stability condition of an amplifier circuit is usually frequency dependent.

37

STABILITY CIRCLES

11 22

211211

L

Lin S

SSS

11

11

2112

22

S

S

out SSSS

The condition that must be satisfied by ΓS and ΓL if the amplifier is to be unconditionally stable:

[7.20a]

[7.20b]

The determinant of the scattering matrix:

21122211 SSSS [7.21]

38

STABILITY CIRCLES

2222

2112

2222

1122

SSSR

SSSC

L

L

2211

2112

2211

2211

SSSR

SSSC

S

S

The output stability circles:

The input stability circles:

[7.22a]

[7.22b]

[7.23a]

[7.23b]

39

STABILITY CIRCLES

Figure 7.3: Output stability circles for conditionally stable device.(a) |S11| < 1 (b) |S11| > 1

40

STABILITY CIRCLES

If the device is unconditionally stable, the stability circles must be completely outside (or totally enclose) the Smith chart.

11

11

22

11

SRC

SRC

SS

LL[7.24a]

[7.24b]

41

STABILITY TEST

12

1

2112

2222

211

SSSS

K

121122211 SSSS

Rollet’s condition:

the auxiliary condition:

11

21121122

211

SSSSS

the μ test:

[7.25]

[7.26]

[7.27]

42

Example 2

The S parameters for the HP HFET-102 GaAs FET at 2 GHz with a bias voltage of Vgs = 0 are given as follow (Z0 = 50 Ohm):

S11 = 0.894 < -60.6S21 = 3.122 < 123.6S12 = 0.020 < 62.4S22 = 0.781 < -27.6

Determine the stability of this transistor using the K- test and the μ test, and plot the stability circles on the Smith Chart

43

Example 2

12

1

2112

2222

211

SSSS

K

121122211 SSSS

11

21121122

211

SSSSS

For the μ test:

Remember, criteria for unconditional stability is:For the K- test:

44

Example 2

1607.02

1

2112

22

22

2

11

SSSS

K

1696.021122211

SSSS

186.01

21121122

2

11

SSSSS

For the μ test:

Calculation results:For the K- test:

Which indicates potential instability

45

Example 2

Input stability circle and radius

Calculation for the input and output stability circles:Output stability circle center and radius:

50.0

47361.1

22

22

2112

22

22

1122

SSSR

SSSC

L

L

199.0

68132.1

22

11

2112

22

11

2211

SSSR

SSSC

S

S

46

STABILITY

Figure 7.4: Example of stability circles

47

SINGLE STAGE TRANSISTOR AMPLIFIER DESIGN

Lout

Sin

222

22

212 1

1

11

max

L

L

ST

SSG

Maximum power transfer from the input matching network to the transistor and the maximum power transfer from the transistor to the output matching network will occur when:

Then, assuming lossless matching sections, these conditions will maximize the overall transducer gain:

[7.28a]

[7.28b]

[7.29]

48

SINGLE STAGE TRANSISTOR AMPLIFIER DESIGN

In the general case with a bilateral transistor, Γin is affected by Γout, and vice versa, so that the input and output sections must be matched simultaneously.

S

SL

L

LS

SSSS

SSSS

11

211222

22

211211

1

1[7.30a]

[7.30b]

49

SINGLE STAGE TRANSISTOR AMPLIFIER DESIGN

2

2

2

2

22

1

2

1

2

11

24

24

CCBB

CCBB

L

S

The solution is:

[7.31a]

[7.31b]

50

SINGLE STAGE TRANSISTOR AMPLIFIER DESIGN

11222

22111

2211

2222

2222

2111

1

1

SSC

SSC

SSB

SSB

The variables are defined as:

[7.32a]

[7.32b]

[7.32c]

[7.32d]

51

SINGLE STAGE TRANSISTOR AMPLIFIER DESIGN

222

2212

11 11

11

max SS

SGTU

12

12

21max

KKSS

GT

12

21

SS

Gmsg

When S12 = 0, it shows that ΓS = S11* and ΓL = S22*, and the maximum transducer gain for unilateral case:

The maximum stable gain with K = 1:

[7.33]

[7.34]

[7.35]

When the transistor is unconditionally stable, K > 1, and the max transducer power gain can be simply re-written as:

52

Example 3

Design an amplifier for a maximum gain at 4.0 GHz. Calculate the overall transducer gain, G, and the maximum overall transducer gain GTMAX. The S parameters for the GaAs FET at 4 GHz given as follow (Z0 = 50 Ohm):

S11 = 0.72 < -116S21 = 2.60 < 76S12 = 0.03 < 57S22 = 0.73 < -68

53

Example 3 (Cont)

195.12

1

2112

22

22

2

11

SSSS

K

162488.021122211

SSSS

Determine the stability of this transistor using the K- test

Since || < 1 and K > 1, the transistor is unconditionally stable at 4.0 GHz.

54

Example 3 (cont)

For the maximum gain, we should design the matching sections for a conjugate match to the transistor. Thus, ΓS = Γin* and ΓL = Γout*, ΓS and ΓL can be determined from;

61876.02

4

123872.02

4

2

2

2

2

12

1

2

1

2

21

CCBB

CCBB

L

S

55

Example 3

dBS

GS

20.617.41

12

11

dBSG 30.876.62

210

dBS

GL

L

L22.267.1

11

2

22

2

So the overall maximum transducer gain will be;

The effective gain factors can calculated as:

dBGT

7.1622.230.820.6max

56

UNILATERAL FOM

22 )1(1

)1(1

UGG

UTU

T

• In many practical cases |S12| is small enough to be ignored, the device then can be assumed to be unilateral, which greatly simplifies design procedure

• Error in the transducer gain caused by approximating |S12| as zero is given by the ratio GT/GTU, and be bounded by:

Where U is defined as the unilateral figure of merit

)1)(1(2

22

2

11

22112112

SSSSSS

U

57

Example 4

An FET is biased for minimum noise figure, and has the following S parameters at 4 GHz:

S11 = 0.60 < -60S21 = 1.90 < 81S12 = 0.05 < 26S22 = 0.50 < -60

For design purposes, assume the device is unilateral and calculate the max error in GT resulting from this assumption.

58

Example 4 (cont)

22 )1(1

)1(1

UGG

UTU

T

059.0)1)(1(

2

22

2

11

22112112

SSSSSS

U

To compute the unilateral figure of merit;

Then the ratio of GT/GTU is bounded as;

130.1891.0 TU

T

GG

59

Example 4 (cont)

In dB, this is;

dBGGTUT

53.050.0

Where GT and GTU are now in dB. Thus we should expect less than about ± 0.5 dB error in gain.

60

CONSTANT GAIN CIRCLES

• In many cases it is desirable to design for less than the max obtainable gain, to improve bandwidth or to obtain a specific value for an amplifier gain.

• Mismatches are purposely introduced to reduce the overall gain• Procedure is facilitated by plotting constant gain circles on the Smith

Chart• Represents loci of ΓS and ΓL, that give fixed values of GS and GL. • To simplify the discussion, we will only treat the case of a unilateral

device

61

CONSTANT GAIN CIRCLES

2

11

2

11

S

S

S SG

2

22

2

11

L

L

L SG

2

111

1max S

GS

The expression for the GS and GL for the unilateral case is given by:

These gains are maximized when ΓS = S11* and ΓL = S22* :

2

221

1max S

GL

62

CONSTANT GAIN CIRCLES

)1(11 2

112

11

2

max

SSG

GgS

S

S

S

S

Now we define normalized gain factors gS and gL as;

Thus we have a that: 0 ≤ gS ≤ 1, and 0 ≤ gL ≤ 1. A fixed value of gS and gL

represents circles in the ΓS and ΓL planes.

)1(11 2

222

22

2

max

SSG

GgL

L

L

L

L

63

CONSTANT GAIN CIRCLES

211

211

211

11

11

11

11

Sg

SgR

SgSgC

S

SS

S

SS

222

222

222

22

11

11

11

Sg

SgR

SgSgC

L

LL

L

LL

Input constant gain circles:

Output constant gain circles:

[7.37a]

[7.37b]

[7.38a]

[7.38b]

64

Example 5

Design an amplifier to have a gain of 11 dB at 4 GHz. Plot constant gain circles for GS = 2 dB and 3 dB; and GL = 0 dB and 1 dB. The FET has the following S parameters (Z0 = 50 Ω):

S11 = 0.75 < -120S21 = 2.50 < 80S12 = 0.00 < 0

S22 = 0.60 < -85

65

Example 5 (cont)

Since S12 = 0 and |S11| < 1 and |S22| < 1, the transistor is unilateral and unconditionally stable. We calculate the max matching section gains as;

The gain of the mismatched transistor is;

dBS

GS

6.329.21

12

11

max

dBS

GL

9.156.11

12

22

max

dBSG 0.825.62

210

66

Example 5 (cont)

So the max unilateral transducer gain is

Thus we have 2.5 dB more available gain than required by specs, since the design only requires 11 dB gain. However, the question also asked us to analyze the effect of having:

Condition 1: GS = 3 dB and GL = 0 dBCondition 2: GS = 2 dB and GL = 1 dB

(Note that these conditions must happens at the same time in order to keep the gain at 11 dB.)

dBGUT

5.130.89.16.3max

67

Example 5 (cont)

875.0max

S

S

S GGg

For condition 1 (input side), when GS = 3 dB:

166.011

11

120706.011

2

11

2

11

2

11

11

SgSg

R

SgSgC

S

S

S

S

S

S

68

Example 5 (cont)

For condition 1 (output side), when GL = 0 dB:

440.011

11

70440.011

2

22

2

22

2

22

22

SgSg

R

SgSgC

L

L

L

L

L

L

640.0max

L

L

L GGg

69

Example 5 (cont)

70

LOW NOISE AMPLIFIER DESIGN

In receiver applications especially, it is often required to have a preamplifier with as low a noise figure as possible since, the first stage of a receiver front end has the dominant effect on the noise performance of the overall system.

Generally it is not possible to obtain both minimum noise figure and maximum gain for an amplifier, so some sort of compromise must be made. This can be done by using constant gain circles and circles of constant noise figure to select a usable trade of between noise figure and gain.

2

min optSS

N YYGRFF [7.39]

71

LOW NOISE AMPLIFIER DESIGN

2

0

min 14 opt

N ZRFFN

1

1

12

N

NNR

NC

optF

optF

For a fixed noise figure, F, the noise figure parameter, N, is given as:

The circles of constant noise figure:

[7.40]

[7.41a]

[7.41b]

72

Example 6

An GaAs FET amplifier is biased for minimum noise figure and has the following S-parameters (Z0 = 50 Ω):

S11 = 0.75 < -120S21 = 2.50 < 80S12 = 0.00 < 0

S22 = 0.60 < -85Γopt = 0.62 < 100

Fmin = 1.6 dBRN = 20 Ω

For design purposes, assume the unilateral. Then design an amplifier having 2.0 dB noise figure with the max gain that is compatible with this noise figure.

73

Example 6 (cont)

0986.014

2

0

min

opt

NZR

FFN

Next use the formulas to compute the center and radius of the 2 dB noise figure circle:

The gain of the mismatched transistor is

24.0

1

1

10056.01

2

N

NNR

NC

opt

F

opt

F

74

Example 6 (cont)

The noise figure circle is plotted in the figure. Min noise figure (Fmin = 1.6 dB) occurs for ΓS = Γopt = 0.62<100o

It can be seen that GS = 1.7 dB gain circle just intersects the F = 2.0 dB noise figure circle, and any higher gain will result in a worse noise figure.

GS (dB) gS CS RS

1.0 0.805 0.52<60o 0.300

1.5 0.904 0.56<60o 0.205

1.7 0.946 0.58<60o 0.150

75

Example 6 (cont)

For the output section we choose ΓL = S22* = 0.5<60o for a max GL of:

dBGGGGLSTU

53.80max

dBS

GL

25.133.11

12

22

dBSG 58.561.32

210

76

Example 6 (cont)