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Mid semester Presentation Mid semester Presentation
Data Packages Generator & Flow Management
Supervisor: Mony OrbachSupervisor: Mony Orbach
D0317D0317One-Semester ProjectOne-Semester Project
Liran Tzafri Liran Tzafri Michael GartsbeinMichael Gartsbein
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Background – Desired Background – Desired SystemSystem
Parallel Processing SystemParallel Processing SystemBased on Altera FPGA Based on Altera FPGA
Using Nios coreUsing Nios core
Sampling Sampling SystemSystem
PreprocessingPreprocessingSystemSystem
Data Data StreamStream
Analog Analog InputInput
N
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Equivalent SystemEquivalent System
Data Data StreamStream
Parallel Processing System Based on Altera FPGA Using Nios core
Parallel accelerator Parallel accelerator AlgorithmAlgorithm
MultiCore Embedded SystemMultiCore Embedded System
PCIPCI
ProcStarII boardProcStarII boardBased on STRATIX IIBased on STRATIX II
Data PackagesData Packages
Generator & Generator & Flow Flow ManagementManagement
Our Project
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Block DiagramBlock Diagram
PCI
BUS
Hardware processing
Transmitter
Reciever
Analyzer
Software
processing
Generator
The Host Application
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The Host ApplicationThe Host Application System flow:System flow:
Host Application generates times of arrival (TOA) vector in software
The Host App sends the vectors to the hardware system and gets the results
The communication is through PCI bus It will also make processing in software The results are analized
In multi processors system we will try to use different load balancing schemes
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Project ObjectivesProject Objectives
Programming the Host application, which Programming the Host application, which will generate the datawill generate the data
Creating modular designCreating modular design Defining the interface and protocol to the Defining the interface and protocol to the
board with the relevant groupsboard with the relevant groups Adding software processing to the Host Adding software processing to the Host
program for comparison with hardwareprogram for comparison with hardware Testing simulations resultsTesting simulations results
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Stratix 2 FPGA on Altera board
PCI bus
Host PC’s fan
ToolsTools
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ToolsTools
Stratix 2 FPGA Altera boardAltera board Gidel’s Proc wizard and IP coresGidel’s Proc wizard and IP cores …… Host PCHost PC Visual Studio 2005Visual Studio 2005
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Host Application Host Application InterfaceInterface
InputsInputs Packet noise parametersPacket noise parameters Missing elements parameters Missing elements parameters Region of interestRegion of interest Operation modeOperation mode
OutputsOutputs System throughputSystem throughput Vectors after hardware or software Vectors after hardware or software
processingprocessing
This image is for illustation only
Packet Structure :Packet Structure :Packet Generator OutputPacket Generator Output**
Packet Structure :Packet Structure :Packet Receiver InputPacket Receiver Input**
*For further details see the Packet Structure document
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Packet Generator\Packet Generator\Receiver InterfaceReceiver Interface
InputsInputs Was the data series identifiedWas the data series identified Average periodAverage period Number of values assigned to the data seriesNumber of values assigned to the data series Indexes of these valuesIndexes of these values
OutputsOutputs TOA vectors of random length between 8 to 1024TOA vectors of random length between 8 to 1024 Each TOA is a DWORD (32 bits)Each TOA is a DWORD (32 bits) Each vector has 1 to 3 data series with a random Each vector has 1 to 3 data series with a random
period between 10 to 10000, and noiseperiod between 10 to 10000, and noise Percentage of noise in each vector is an input to the Percentage of noise in each vector is an input to the
Host AppHost App Percentage of missing data from each vector is an Percentage of missing data from each vector is an
input to the Host Appinput to the Host App
Host App Operation Modes
In order to check the performance of the system, there will be two modes of operation: Correctness test: Checks correctness
for finite number of packets Performance test: Packets will be sent
continuously, elaborated in next slides
Packet Send Chain
Packets are generated continuously, by the Packet Generator®. Here, the Packet contains only the data (TOAs), an ID, and the length
The Packets are forwarded to the Packetizer®, which adds a “header” and “footer” to the packet, according to the interface
Packet Send Chain (Cont.)
The Packetizer® then forwards a bit stream to the RxTx entity
The data is then sent immediately to the hardware (using DMA and Gidel’s API)
Several sending techniques will be examined in order to maximally utilize the PCI bus
Packet Receive Chain
While there is data in hardware, it is read continuously, and stored in a local FIFO
The Depacketizer® entity transforms the DWORD stream from the FIFO into packets
Performance of the system is checked: number of packets processed compared with the run time
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This page was left blank This page was left blank on purposeon purpose
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Special ProblemsSpecial Problems Problem:Problem: Naming the project with a Naming the project with a
meaningful namemeaningful name Solution:Solution: Packet I/O Software Management Packet I/O Software Management
Application (PISMA)Application (PISMA)
Problem:Problem: Integration and synchronicity Integration and synchronicity between different project parts/groups between different project parts/groups Solution:Solution: Defining an all-accepted Interface Defining an all-accepted Interface
Problem:Problem: Debugging hardware and software Debugging hardware and software simultaneouslysimultaneouslySolution:Solution: … …
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ScheduleSchedule
Date Assignment1.10-19.10
Learning the system blocks and Gidel’s API
20.10-12.11
Checking feasibility and communication between units
7.11-22.11
Design of the Host program
20.11 Characterization presentation
23.11-3.12
4.12-12.12
22.12
16.1
Implementing the packet generator
Creating basic I/O loop with the hardware
Defining the interface with other groups
Mid semester presentation
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Schedule (cont.)Schedule (cont.)
Date Assignment2.1-11.1 Transition from Simple to Multi FIFO
12.1-16.1 Integration of Pulse Deinterleaver Algorithm in software
17.1-22.1 Create the Depacketizer® Entity
23.1-24.1 Implement the system’s two modes of operation
25.1-10.2
11.2-17.2
18.2-20.2
Debug of system
Test of system
Final presentation