Aug 31, '02 VDAT'02: Low-Power Design 1
Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set
Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set
Tezaswi Raja, Rutgers [email protected]
Vishwani D. Agrawal, Agere [email protected]
http://cm.bell-labs.com/cm/cs/who/va
Michael L. Bushnell, Rutgers [email protected]
Bangalore, August 31, 2002
Aug 31, '02 VDAT'02: Low-Power Design 2
Problem StatementProblem Statement
•Design a digital circuit for minimum transient energy consumption by eliminating hazards
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Theorem 1Theorem 1•For correct operation with minimum
energy consumption, a Boolean gate must produce no more than one event per transition
Ref: Agrawal, et al., Proc. VLSI Design’99
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• Given that events occur at the input of a gate (inertial delay = d ) at times t1 < . . . < tn , the number of events at the gate output cannot exceed
Theorem 2Theorem 2
min ( min ( n n , 1 + ), 1 + )ttnn – t – t11
----------------dd
ttnn - t - t11 + d + d
tt11 t t22 t t33 t tnn t tnn + +
dd
timetime
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Minimum Transient Design
Minimum Transient Design
•Minimum transient energy condition for a Boolean gate:
| t| tii - t - tjj | < d | < d
Where tWhere tii and t and tjj are arrival times of input are arrival times of input
events and d is the inertial delay of gateevents and d is the inertial delay of gate
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Linear Program (LP)Linear Program (LP)
•Variables: gate and buffer delays
•Objective: minimize number of buffers
•Subject to: overall circuit delay
•Subject to: minimum transient condition for multi-input gates
•AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)
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Limitations of This LPLimitations of This LP
•Constraints are written by path enumeration.
•Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits.
•Example: c880 has 6.96M constraints.
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A New LP ModelA New LP Model
•Introduce two new variables per gate output:
• ti Earliest time of signal transition at gate i.
• Ti Latest time of signal transition at gate i.
t1, T1
tn, Tn
.
.
.
ti, Ti
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New Linear ProgramNew Linear Program
•Gate variables d4..d12
•Buffer Variables d15..d29
•Corresponding window variables t4..t29 and T4..T29.
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Multiple-Input Gate ConstraintsMultiple-Input Gate Constraints
For Gate 7:T7 > T5 + d7; t7 < t5 + d7; d7 > T7 - t7;
T7 > T6 + d7; t7 < t6 + d7;
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Single-Input Gate ConstraintsSingle-Input Gate Constraints
T16 + d19 = T19 ;
t16 + d19 = t19 ;
Buffer 19:
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Overall Delay ConstraintsOverall Delay Constraints
T11 < maxdelay
T12 < maxdelay
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Validation of the ModelValidation of the Model
For Gate 6 (path-enumeration model):d1 + d3 – d2 < d6
d2 – d3 – d1 < d6
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Validation of the ModelValidation of the Model
For Gate 6 (new model):T6 > T2 + d6; t6 < t2 + d6; d6 > T6 - t6;
T6 > T3 + d6; t6 < t3 + d6; .. (Ineq. set A)
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Validation of the ModelValidation of the Model
Buffer Constraints:T2 = t2 = d2 ; T3 = t3 = d3 ; (Ineq. set B)
Substituting Ineq. set B in Ineq. set At6 – d2 < d6 ..( 1 )
t6 – d1 – d3 < d6 ..( 2 )
d6 < T6 – d2 ..( 3 )
d6 < T6 – d1 – d3 ..( 4 )
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Validation of New ModelValidation of New ModelAdding ineq. ( 1 ) and ( 4 ), and using (A)
d1 + d3 – d2 < T6 – t6 < d6
Adding ineq. ( 2 ) and ( 3 ), and using (A)d2 – d3 – d1 < T6 – t6 < d6
•These are the same inequalities as for the old path-enumeration model.
•Similar derivation can be done for maxdelay constraints.
•Hence the new model constraints are equivalent to the old ones.
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Why New Model is Superior?Why New Model is Superior?
•Path constraints from old model4 × 4 × …4 = 4n
•Constraints from new model15 × n = 15n
•Hence new constraint set is linear in size of circuit.
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Comparison of ConstraintsComparison of Constraints
Number of gates in circuit
Nu
mb
er
of
con
str
ain
ts
c880
3,611
6.96x106
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Results: Procedure OutlineResults: Procedure Outline
C++ Program
AMPL*
Power Estimator
Combinational circuit netlist
Results
Constraint-set
Optimized delays
*Fourer, Gay and Kernighan, AMPL: A Modeling Languagefor Mathematical Programming, 1993.
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Results: 1-Bit AdderResults: 1-Bit Adder
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Estimation of PowerEstimation of Power•Circuit is simulated by an event-driven
simulator for both optimized and un-optimized gate delays.
•All transitions at a gate are counted as Events[gate].
•Power consumed Events[gate] x # of fanouts.
•Reference: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ISLPED`97).
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Original 1-Bit AdderOriginal 1-Bit Adder
Colo
r co
des
for
num
ber
of
transi
tions
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Optimized 1-Bit AdderOptimized 1-Bit Adder
Colo
r co
des
for
num
ber
of
transi
tions
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Results: 1-Bit AdderSimulated over all possible vector transitions
•Average power = optimized/unit delay = 244 / 308 = 0.792
•Peak power = optimized/unit delay = 6 / 10 = 0.60
Power Savings :
Peak = 40 %
Average = 21 %
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Results: 4-Bit ALUResults: 4-Bit ALU
maxdelay Buffers inserted
7 5
10 2
12 1
15 0
Power Savings :
Peak = 33 %, Average = 21 %
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Power Dissipation of ALU4Power Dissipation of ALU4En
erg
y in
nan
ojo
ule
s
0
1
2
3
4
5
6
7
0.0 0.5 1.0 1.5 2.0microseconds
Original ALUdelay ~ 3.5ns
Minimum energy ALUdelay ~ 10ns
1 micron CMOS, 57 gates, 14 PI, 8 PO100 random vectors simulated in Spice
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Benchmark CircuitsBenchmark CircuitsCircuit
C432
C880
C6288
c7552
Maxdel.(gates)
1734
2448
4794
4386
No. ofBuffers
9566
6234
294120
366111
Average
0.720.62
0.680.68
0.400.36
0.380.36
Peak
0.670.60
0.540.52
0.360.34
0.340.32
Normalized Power
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ConclusionConclusion• Obtained an LP constraint-set that is linear in the size of
the circuit. LP solution:
• Eliminates glitches at all gate outputs,
• Holds I/O delay within specification, and
• Combines path-balancing and hazard-filtering to
minimize the number of delay buffers.
• New LP produces results exactly identical to old LP
requiring exponential constraint-set.
• Results show peak power savings up to 40% and
average power savings up to 21%.
