MIPS-Lite Multicycle Control - Ryerson Universitycourses/coe608/lectures/Multi... · 2014-04-07 ·...

© G. Khan Computer Organization & Architecture – coe608: Multi-cycle Control Page: 1

MIPS-Lite Multicycle Control

COE608: Computer Organization and Architecture

Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan

Electrical and Computer Engineering

Ryerson University

Overview

• Introduction • MIPS Multicycle Datapath • Multicycle Control • Microprogramming Concepts • Microprogrammed Control

Sections 4.4 and 4.6


Multicycle Approach

• We will be reusing the functional units. ♦ ALU used to compute address & increment PC. ♦ Memory used for instruction and data. • Control signals will not be determined solely

by the instructions • Control unit design by using classical FSM

design is impractical due to large number of inputs and states it may have.

• An extension to the classical approach is used by experienced designer in designing control logic circuits: 1. Sequence register and decoder method. 2. One flip-flop per state method. 3. Microprogram controller. 4. PLA controller.

The PLA and micro-program control uses PLD and ROM/PROM. Modification of PROM or replacing the ROM modifies the micro-program control.


Single Cycle Datapath

Long Cycle Time • All instructions take as much time as the

slowest. • Real memory is not like our idealized memory

Cannot always get the job done in one (short) cycle

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

RdRegDst

Extender

Mux

Mux

3216imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr

AL

U

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

RdRegDst

Extender

Mux

Mux

3216imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr

AL

U

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

PC Inst Memory mux ALU Data Mem mux

PC Reg File Inst Memory mux ALU mux

PC Inst Memory mux ALU Data Mem

PC Inst Memory cmp mux

Reg File

Reg File

Reg File

Arithmetic & Logical

Load

Store

Branch

setup

setupPC Inst Memory mux ALU Data Mem mux

PC Reg File Inst Memory mux ALU mux

PC Inst Memory mux ALU Data Mem

PC Inst Memory cmp mux

Reg File

Reg File

Reg File

Arithmetic & Logical

Load

Store

Branch

setup

setup


Single Cycle Control

op<0>

op<5> .op<5> .<0>

op<5> .<0>

op<5> .<0>

op<5> .<0>

R-type lw sw beq jumpRegWrite

ALUSrc

MemtoRegMemWrite

BranchJump

RegDst

ALUop<1>ALUop<0>

op<0>

op<5> .op<5> .<0>

op<5> .<0>

op<5> .<0>

op<5> .<0>

R-type lw sw beq jumpRegWrite

ALUSrc

MemtoRegMemWrite

BranchJump

RegDst

ALUop<1>ALUop<0>

R-type lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWriteBranchJump

ALUop (Symbolic)

1001000

“R-type”

0111000

Add

x1x0100

Add

x0x0010

Subtract

xxx0001

xxx

op 00 0000 10 0011 10 1011 00 0100 00 0010

ALUop <1> 1 0 0 0 xALUop <0> 0 0 0 1 x

R-type lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWriteBranchJump

ALUop (Symbolic)

1001000

“R-type”

0111000

Add

x1x0100

Add

x0x0010

Subtract

xxx0001

xxx

op 00 0000 10 0011 10 1011 00 0100 00 0010

ALUop <1> 1 0 0 0 xALUop <0> 0 0 0 1 x


Abstract View

Similar to an FSM where state changes with a change in the PC value.

PC

Nex

t PC

Reg

iste

rFe

tch ALU Reg

.W

rt

Mem

Acc

ess

Dat

aM

emInst

ruct

ion

Fetc

h

Res

ult S

tore

ALU

ctr

Reg

Dst

ALU

Src

ExtO

p

Mem

Wr

Equ

al

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

MainControl

ALUcontrol

op

fun

Ext

PC

Nex

t PC

Reg

iste

rFe

tch ALU Reg

.W

rt

Mem

Acc

ess

Dat

aM

emInst

ruct

ion

Fetc

h

Res

ult S

tore

ALU

ctr

Reg

Dst

ALU

Src

ExtO

p

Mem

Wr

Equ

al

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

MainControl

ALUcontrol

op

fun

Ext

MainControl

op6

ALUControl(Local)

func

2

6

ALUop

ALUctr3

RegDstALUSrc

:MainControl

op6

ALUControl(Local)

ALUControl(Local)

func

2

6

ALUop

ALUctr3

RegDstALUSrc

:


Reducing the Cycle Time Cut combinational dependency graph and insert registers/latches Do the same work in two fast cycles rather than one slower cycle.

Multicycle Approach Break instructions into steps

storage element

Acyclic

Combinational

Logic

storage element

storage element

Acyclic Combinational Logic (A)

storage element

storage element

Acyclic Combinational Logic (B)

=>

storage element

Acyclic

Combinational

Logic

storage element

storage element

Acyclic Combinational Logic (A)

storage element

storage element

Acyclic Combinational

=>


Partitioning Single-Cycle Datapath

Multicycle Datapath

PC

Nex

t PC

Ope

rand

Fetc

h Exec Reg

. Fi

le

Mem

Acc

ess

Dat

aM

emInst

ruct

ion

Fetc

h

Res

ult S

tore

AL

Uct

r

Reg

Dst

AL

USr

c

Ext

Op

Mem

Wr

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

PC

Nex

t PC

Ope

rand

Fetc

h Exec Reg

. Fi

le

Mem

Acc

ess

Dat

aM

emInst

ruct

ion

Fetc

h

Res

ult S

tore

AL

Uct

r

Reg

Dst

AL

USr

c

Ext

Op

Mem

Wr

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

PC

Nex

t PC

Ope

rand

Fet

ch

Ext

AL

U

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

Inst

ruct

ion

Fet

ch

Res

ult S

tore

AL

Uct

r

Reg

Dst

AL

USr

c

Ext

Op

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

IR

A

B

R

M

RegFile

Mem

ToR

eg

Equ

al

PC

Nex

t PC

Ope

rand

Fet

ch

Ext

AL

U

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

Inst

ruct

ion

Fet

ch

Res

ult S

tore

AL

Uct

r

Reg

Dst

AL

USr

c

Ext

Op

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

IR

A

B

R

M

RegFile

Mem

ToR

eg

Equ

alS


R-type Instructions

(Add, Sub, etc. .) Logical Register Transfer ADDU R[rd] <= R[rs] + R[rt]; PC <= PC + 4

Physical Register Transfers IR <= Mem [PC]

ADDU A<= R[rs]; B <= R[rt] S <= A +/- B

R[rd] <= S; PC <= PC + 4

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

A

B

S

M

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

A

B

S

MM

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem


Load Instructions Logical Register Transfer LW R[rt] <= Mem (R[rs] + sx(Im16)); PC <= PC + 4 Physical Register Transfers

IR <= Mem [PC] LW A<= R[rs] ; S <= A + SignEx(Im16) ; M <= Mem [S] ; R[rd] <= M ; PC <= PC + 4

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

A

B

S

M

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

AA

BB

SS

MM

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem


Store Instructions

Logical Register Transfer SW MEM(R[rs] + sx(Imm16)) <= R[rt]; PC <= PC + 4

Physical Register Transfers IR <= Mem[PC]

SW A<= R[rs] ; B <= R[rt]; S <= A + SignEx(Imm16) ; Mem[S] <= B; PC <= PC + 4

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

A

B

S

M

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

AA

BB

SS

MM

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem


Branch Instructions

Logical Register Transfer BEQ if R[rs] = = R[rt] then PC <= PC + sx(Imm16) || 00 else PC <= PC + 4

Physical Register Transfers IR <= Mem [PC]

BEQ & not EQUAL PC <= PC + 4 BEQ & EQUAL PC <= PC + sx(Imm16) || 00 ;

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

A

B

S

M

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

AA

BB

SS

MM

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

.Mem


Multiple Cycle Datapath

Miminizes Hardware: One memory and one adder

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr32

AL

U

3232

ALUOp

ALUControl

InstructionR

eg32

IRWr

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mux

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01

RegDst

Mux

0

1

32

PC

MemtoReg

Extend

ExtOp

Mux

0

132

0

1

23

4

16Imm 32

<< 2

ALUSelB

Mux

1

0

32

Zero

ZeroPCWrCond PCSrc

32

IorD

AL

U O

ut

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr32

AL

U

323232

ALUOp

ALUControl

ALUControl

InstructionR

eg32

IRWr

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mux

0

1

Mux

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01 Mux 01

RegDst

Mux

0

1

Mux

0

1

32

PC

MemtoReg

ExtendExtend

ExtOp

Mux

0

1

Mux

0

132

0

1

23

4

1616Imm 32

<< 2<< 2

ALUSelB

Mux

1

0

3232

Zero

ZeroPCWrCond PCSrc

32

IorD

AL

U O

ut


Control Model

State specifies control points for Register Transfer Transfer occurs upon exiting state (falling edge) i.e. control outputs are of Mealy type.

Control State

Next StateLogic

Output Logic

inputs (conditions)

outputs (control points)

Control State

Next StateLogic

Output Logic

inputs (conditions)

outputs (control points)

State X

Register TransferControl Points

Depends on Input

State X

Register TransferControl Points

Depends on Input


Control Specification

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQ & EqualBEQ & ~Equal

PC <= PC + 4 PC <= PC +SX || 00

SW

“instruction fetch”

“decode / operand fetch”

Exe

cute

Mem

ory

Wri

te-b

ack

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4


PC <= PC + 4 PC <= PC +SX || 00

SW


“decode / operand fetch”

Exe

cute

Mem

ory

Wri

te-b

ack


Mapping RTs to Control Points

State Assignments

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4


PC <= PC + 4 PC <= PC +SX || 00

SW


“decode”

Exe

cute

Mem

ory

Wri

te-b

ack

imem_rd, IRen

ALUfun, Sen

RegDst,RegWr,

PCen

Aen, Ben

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4


PC <= PC + 4 PC <= PC +SX || 00

SW


“decode”

Exe

cute

Mem

ory

Wri

te-b

ack

imem_rd, IRen

ALUfun, Sen

RegDst,RegWr,

PCen

Aen, Ben

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4


PC <= PC + 4 PC <= PC +SX || 00

SW


“decode”

Exe

cute

Mem

ory

Wri

te-b

ack

0000

0001

0100

0101

0110

0111

1000

1001

1010

0011 00101011

1100

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4


PC <= PC + 4 PC <= PC +SX || 00

SW


“decode”

Exe

cute

Mem

ory

Wri

te-b

ack

0000

0001

0100

0101

0110

0111

1000

1001

1010

0011 00101011

1100


Five Execution Steps

• Instruction Fetch • Instruction Decode and Register

Fetch • Execution, Memory Address

Computation, or Branch Completion

• Memory Access or R-type instruction completion

• Write-back step

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction for branches

Action for jumps

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or

Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR


Performance Evaluation What is the average CPI? State diagram provides CPI for each type of instruction. The workload gives the frequency of each instruction type Type CPIi Frequency CPIi x freqIi

for type Arith/Logic 4 40% 1.6 Load 5 20% 1.0 Store 4 20% 0.8 Branch 3 20% 0.6

Average CPI: 4.0


FSM for Datapath Control

PCWritePCSource = 10

ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond

PCSource = 01

ALUSrcA =1ALUSrcB = 00ALUOp= 10

RegDst = 1RegWrite

MemtoReg = 0MemWriteIorD = 1

MemReadIorD = 1

ALUSrcA = 1ALUSrcB = 10ALUOp = 00

RegDst =0RegWrite

MemtoReg=1


MemReadALUSrcA = 0

IorD = 0IRWrite

ALUSrcB = 01ALUOp = 00


Instruction fetchInstruction decode/

register fetch

Jumpcompletion

BranchcompletionExecution

Memory addresscomputation

Memoryaccess

Memoryaccess R-type completion

Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op = 'B

EQ')

(Op

='J

')

(Op = 'SW')

(Op

='L

W')

4

01

9862

753

Start



PCSource = 01


RegDst = 1RegWrite


MemReadIorD = 1

ALUSrcA = 1AL PCWrite

PCSource = 10


PCSource = 01


RegDst = 1RegWrite


MemReadIorD = 1


RegDst =0RegWrite

MemtoReg=1


MemReadALUSrcA = 0

IorD = 0IRWrite



Instruction fetchIn

USrcB = 10ALUOp = 00

RegDst =0RegWrite

MemtoReg=1


MemReadALUSrcA = 0

IorD = 0IRWrite



Instruction fetchInstruction decode/

register fetch

Jumpcompletion



Memoryaccess


Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R

struction decode/register fetch

Jumpcompletion



Memoryaccess


Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op = 'B

EQ')

(Op

='J

')

(Op = 'SW')

(Op

='L

W')

4

01

9862

753

Start


Microprogram Control Design

The state diagrams define the controller for an instruction set processor are highly structured.

• Use this structure to construct a simple “micro-sequencer”

• Control reduces to programming this very simple device using the concept of: microprogramming

sequencer

control

datapath control

micro - PC

sequencer

control

datapath control

micro - PC

Sequencer

Micro instruction


Processor Instruction Interpretation

MainMemory

executionunit

controlmemory

CPU

ADDSUBAND

DATA

.

.

.

User program plus Data

this can change!

AND microsequence

e.g., FetchCalc Operand AddrFetch Operand(s)CalculateSave Answer(s)

one of these ismapped into oneof these

MainMemory

executionunit

controlmemory

CPU

ADDSUBAND

DATA

.

.

.

User program plus Data

this can change!

AND microsequence

e.g., FetchCalc Operand AddrFetch Operand(s)CalculateSave Answer(s)

one of these ismapped into oneof these


Microprogramming

Horizontal vs. Vertical

“Horizontal” Microcode

• Control field for each control point in the

machine. • Lots of control states but provide more

control over the parallelism in the datapath.

“Vertical” Microcode • Compact microinstruction format for each

class of µ-operation. • Local decode to generate all control

points. • Extra level of decoding can slow down the

machine.

µseq µaddr A-mux B-mux bus enables register enablesµseq µaddr A-mux B-mux bus enables register enables

src dst

DEC

DEC

other control fields next states inputs

MUX

src dst

DEC

DEC

other control fields next states inputs

MUX


Microprogram-based Control

Control is the hard part of processor design • Datapath is fairly regular and well-

organized • Memory is highly regular • Control is irregular and global

Sequencer-based Control Unit

Opcode

State Reg

Inputs

Outputs

Control Logic MulticycleDatapath

1

Address Select Logic

Adder

Types of “branching”• Set state to 0• Dispatch (state 1)• Use incremented state

number

Opcode

State Reg

Inputs

Outputs


1


Adder


number

Opcode

State Reg

Inputs

Outputs


1


Adder


number


Designing a Microinstruction Set

• Start with list of control signals.

• Group signals together that make sense (vs. random): called “fields”

• Places fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)

• Create a symbolic legend for µ-instruction format, showing name of field values and how they set the control signals

• Use computers to design computers. µ-assembler to get binary code.

• To minimize the width, encode operations that will never be used at the same time.


Microinstruction Fields and Control Signals

Field name Value Signals active Comment

Add ALUOp = 00 Cause the ALU to add.ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for

branches.Func code ALUOp = 10 Use the instruction's function code to determine ALU control.

SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.A ALUSrcA = 1 Register A is the first ALU input.B ALUSrcB = 00 Register B is the second ALU input.

SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input.Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input.Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input.Read Read two registers using the rs and rt fields of the IR as the register

numbers and putting the data into registers A and B.Write ALU RegWrite, Write a register using the rd field of the IR as the register number and

Register RegDst = 1, the contents of the ALUOut as the data.control MemtoReg = 0

Write MDR RegWrite, Write a register using the rt field of the IR as the register number andRegDst = 0, the contents of the MDR as the data.MemtoReg = 1

Read PC MemRead, Read memory using the PC as address; write result into IR (and lorD = 0 the MDR).

Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR.lorD = 1

Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as thelorD = 1 data.

ALU PCSource = 00 Write the output of the ALU into the PC.PCWrite

PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contentsPCWriteCond of the register ALUOut.

jump address PCSource = 10, Write the PC with the jump address from the instruction.PCWrite

Seq AddrCtl = 11 Choose the next microinstruction sequentially.Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.

Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.


Sequencer-based Control Unit

Signal Mux-select . Sequencing 00 Next µaddress = 0 01 Next µ-address = dispatch ROM-1 10 Next µ-address = dispatch ROM-2 11 Next µ-address = µ-address + 1

State

Op

Adder

1

PLA or ROM

Mux3 2 1 0

Dispatch ROM 1Dispatch ROM 2

0

AddrCtl

Address select logic

Instruction register�opcode field

Dispatch ROM 1 Dispatch ROM 2Op Opcode name Value Op Opcode name Value

000000 R-format 0110 100011 lw 0011000010 jmp 1001 101011 sw 0101000100 beq 1000100011 lw 0010101011 sw 0010


Microprogram Details

Microprogram: Signals specified symbolically using microinstructions.

State number Address-control action Value of AddrCtl0 Use incremented state 31 Use dispatch ROM 1 12 Use dispatch ROM 2 23 Use incremented state 34 Replace state number by 0 05 Replace state number by 0 06 Use incremented state 37 Replace state number by 0 08 Replace state number by 0 09 Replace state number by 0 0

LabelALU

control SRC1 SRC2Register control Memory

PCWrite control Sequencing

Fetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch


Microprogram Details

Micro Instructions for Fetch and Decode

Label ALU Control

SRC1 SRC2 Reg. Control

Mem PCWrite Control

Sequence

Fetch Add PC 4 ReadPC

ALU Seq

Add PC Ext shift

Read Dispatch-1

Mem: Fetch Instruction into IR ALU, SRC1, SRC2: Compute PC + 4 PCWrite Control: Write the output of ALU to PC Sequencing: go to the next microinstruction.

Next Microinstruction is Decode ALU, SRC1, SRC2: PC + signext(IR[0:15]) << 2 Register Control: Read registers into A and B. Sequencing: Use dispatch-1 to select one of the following four labels

♦ Mem1 ♦ Rformat1 ♦ BEQ1 ♦ JUMP1

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