MIPS R4000 Technical Overview

64 Bits/100 MHz or Bust

Earl Killian

August2, 1991

Overview

1 9mips

• Integrated I and D primary caches (8K->32K).

• Improved pipeline «1/2 # of gates/cycle).

• Flexible system and secondary cache interface.

• Integrated floating point.

• Multi-processor support.

• 64 bit Integer Datapath and 64 bit TLB.

, 1.6 August2. 1991 2

R4000 Block Diagram

I I':

Decode Data Tag."..:

I ｬｾｾ SCache

128 data

..< .• ····1·············:... -· •.•: ... -...•.-.---

......

I\64 data LJliacr e

ｃｉ］］｜ｩｾ＿［ i"nc:t,\-===--rr::====:::::;,I PCacheGRORE:}gisters

FPRegisterFile Control .... ｾｪｊＱＲｂＭ ..

IGacne

FPPipelineLBypass··

·FP·Statas Register

FPMultiply

FPDivide

FPAdd,Sqrt,:Cvt. ..'

System,SCacheControl

Pipeline-- Control

RC.lnetementer:····· .'............_..... - -....

:':':Reoistef-Rile .•••••••i...·:.·..·....·.- ,j\(iUJ_···>·.·.·.>•.-···.·.··.>· .:.

ﾷ［Ｎ｢ｾ｀ＮＹＱｰｴｑｴｾﾷｾｉＬｩＮｧｧ･ｲﾷﾷﾷﾷﾷ

ｻｬｬＱｴ･ｧ･ｲﾷＧＮｌｩｩｬＧｬＺｾｭｩｶＮｬ ••••• i ••;\. ... ｾｹｳｬｮｴ64 addr/data

August2,1991 3

R4000 Technology

• 1.0 micron CMOS technology.

• 2 Layer Metal technology.

• 1.3 Million transistors.

• 100 MHz internal clock.

August2, 1991 4 .mips1.7

MIPS R3000 Pipeline

Instruction Fetch

Register Access

ALU

Memory (cache)

Write (register)

1.8

August2. 1991

MIPS R3000 Pipeline

+--+1 R3000 System Clock (-30 n5, 1990)

August 2. 1991

5

6

--sｾｾｾ

l.. Ｎｾｾ,ｾ W ｾｾ ｾｾ ｾ+, J J

ｾ 1ｾ

ｾ M I W ｾ,_I ｾ ｾ

ldW'If IWlIlv _.Nl ｾ

MIPS R4000 Pipeline

August2, 1991

Instruction Fetch

Register Fetch

Execution

Data Access

Tag Check

Write Back (register)

7 Gmips

MIPS R4000 Pipeline

ｾ Ｍ Ｍ Ｍ Ｋ1 R4000 System Clock (-20 ns, 1991)

August2. 1991 8 1.9

R3000 vs. R4000 Pipeline Details

ｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＢＢＢＧＧＧＧＧＧｾＢ ..ＬＧＧＧＧｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＢＢＢＢＢＢＢＢＢＢＧＧﾧｾ 18 ｾ ICache ｦ ｔ ｃ ｾ IDee ｾ OP ｾs s s s: s ｾＮ

ｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＢｾＢＢＢＢｾＢＢＢＧｾＬＢＢＢＢＢＢＢＧＧﾧＮＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧｾＧＧＧＧＧＧＧＧＧＧＧＧＬ .."..ＬＧｾＧＧＧＧＢＢＢＢＢＢＢＢＢＢＢＧｾＢＢＢＢｾＢＢＢＢＢＢＢＢｾs § § s s §or- § Ｎｾ

ｾ IT ｾ RF ｾ DA ｾ DT ｾ ｄｃ｡｣ｨ･ｾＱ ｃｾ WB ｾｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ ｾ Ｇ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ Ｇ Ｇ Ｍ Ｇ Ｇ Ｇ ｾ ｾ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ

§ IA § §LA§§ § § §§ ｾ ｾ ｾｾＢＢＢＢＢＢＢＢｾ ｾＢＢＢＧｾ

ｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＧＢｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＢＧｾＢＢＢＢＢＢＢＧＢｾＢＢＢＢＢＧＧＧＧＧＧＧｬＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧＧｬ

ｾ IF ｾ IS ｾ RF ｾ EX ｾ DF ｾ OS ｾ TC ｾ WB ｾｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ Ｌ Ｇ Ｌ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｌ ｾ Ｂ Ｂ Ｂ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ ｬ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ ｾ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｂ ｾ Ｂ Ｂ Ｂ Ｂ Ｇ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ

ﾧ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ Ｂ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾｾ ICache ｾ IDee ｾＧｏｐ ｾ DCache ｾ ｌ ａ ｾｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｌ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｌ Ｌ ｾ Ｌ Ｇ Ｂ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ ｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾｾ IT ｾ RF ｾ IA ｾ DT ｾ TC ｾ WB ｾｾ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｇ ｩ Ｇ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｂ Ｌ Ｌ ｾ Ｌ Ｇ Ｂ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｂ Ｂ Ｂ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ ｾ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｇ Ｎ ﾧ

§ ITC §§ §ｾ ｾｾＢＢＢＢＢＢＢＢＧｾ

August2, 1991 9 ｾｭｩｰｳ

R3000 vs. R4000 Cache Access

18

R

ICache TC IDee

RFIA

DA

A

OP

DT

M

DCacheTC

W

WB

R3000 vs. R4000: Address Translation

A M W

OP

DA DT

IF IS RF EX WB

ICache IDee OP

IT RF fA TC WB

ITC

August2, 1991 11 ｾｭｩｰｳ

18

R3000 vs. R4000: Other operations

R A M W

IF IS

ICache

IT

18 ICache TC

IT

OP

DA DT WB

• August2. 1991 12 GIDips 1.11

R3000 vs. R4000: ALU operations

18

IF

ICache

August2, 1991

IDec OPIA

DCache

DT

13

Hypothetical MIPS Superscalar Pipeline

1.12 AupR2, 1991 14 emlps

MIPS R3000 Branch Delay

• One Branch Delay Cycle

• MIPS Architectural Branch Delay

BD = 1

August2,1991 15

R4000 v.s. Superscalar: Branch Delay

IF IS RF EX F OS TC:WB

IF IS RF X OF OS TCWB·N._,"·....,..·.,., """.",

IF IS RF EX DF' DS TC'WB

I IS RF EX OF OS' TCWB .

IF IS RF EX DF DS TCWB

BO=3

R

RI

I

M W

M W

A M W. ·.· ﾷＬＮＬＮＬﾷｾＮ｟Ｎｵ .... .•..... <.,.,.",.. ".,.,.,.,•..,,, ＢＢＢＢＧＬＮＬＪＮｾＬＮＬＮＬＮ B0 = 2 or 3

A M WＮＬＮｾＮＭ ...__Ｚ Ｎ ｾ Ｚ Ｎ Ｚ Ｚ Ｎ Ｇ Ｎ ｾ Ｂ ｾ Ｇ ［ Ｍ Ｚ Ｎ ":-:.;"" ··x·.·. .;.: ...:-.,•. -.;.J.......;.:.:.• -:w.«-;.(- 0'

RAM W-v Ｎ Ｍ Ｚ Ｍ ｸ Ｚ Ｎ ｾ ｾ Ｉ ｾ ｾ ｾ •ＮＬＺＺＮＺＮＧＩＬＮＭＮＮＮＭＮＧｨｯｴＭｾＺＮｎ｟ＮＺﾷＮﾷﾷﾷﾷﾷＮＺＧｏｃＭﾷ［ﾷｾｾ［ＮｾｾｩｫｾｾＭ［Ｌ［ＭＬＮｾＢＢｾＧＺｾｾｾｾｾｾＢＢ I ...

RAM W

August 2. 1991 16 Omips 1.13

MIPS R3000 Load Delay

LD = 1

• One Load Delay Cycle

• MIPS Architectural Load Delay

August 1991 17 Omips

R4000 v.s. Superscalar: Load Delay

IF

LD=2

LD = 2 or 3

RRI

I

AA

RRII

M

MA

A

R. ,,' ::";

R

wW

M W

M W

A M W, . : _·.:u "";,;>..-.:._: ..:.:__" ｾ ｟ＢＧＧＧＺｾＮｾＧＧ［ＮＧＨ • ; ＮＮＬＮＮＪＢＺｾＳｴＢｖｎｎＩＬＺＮＢＮﾷＮﾷ _ ·.-- ｾｾｾ［Ｎ［ＭｬｏＧＩＬＮｾ .. ｾｾｾｾﾷｾＺ

A M W'

1.14 August2."1991 18

R3000, R4000 v.s. Superscalar: Dependent ALU ops

R

I

W

M w AD=O

AD=O

R A

ＨａｾW

R A W AD = aor 1I R M WI R A M W

August2,1991 19 ｾ ｭ ｩ ｰ ｳ

R4000 v.s. Superscalar: Other Issues

• R4000 can issue twice as many load/store insts.

• Fewer functional units required.

• Simpler pipeline controller.

• Fewer requirements on compiler.

August2, 1991 20 ｾｭｩｰｳ 1.15

R4000 Configurations

SMALL

R4000167pin

MEDIUM

SCache

128

R4000447 pin

August2, 1991

R4000 Configurations

"DRAM

LARGE

21

SCache

128

-mips

"SCaclia

DRAM

1.18 August. 2. 1991

110R4000447pin

22

R4000447pin

-mips

Flexible System Interface

• 64 bit wide System Interface for Addr/Data.

• Configurable clock divisors.

• Configurable transmit/receive data patterns.

• Overlapped operation for write backsecondary cache systems.

August2. 1991 23 Smips

Configurable Clock Rates for 50 MHz interface

+2 --7 100MHz.

SysAD < A D D D D +3 --7 150MHz.R4000 Clock

SysAD < A D D D +4 --7 200MHz.R4000 Clock

August2. 1991 24 Smips 1.17

Configurable TransmiVReceive Patterns

SysAD< A XD X .0 X

SysAD < A XD X'----JX 0 X,----,XnX-----."X 0 )

August2. 1991 25 Omips

Overlapped Operation v.s. Non-Overlapped Operation

Overlapped

Read Latency

Non-Overlapped

Read AddressWrite AddressRead Data (block)Write Data (block)

｟ｾｂＥＮｦＪｾｾ It t-------Read Latency

1.18 Aup8t2. 1991 26 Omlps

Conclusionj

• Third Generation RISC.Integrated Caches.Integrated Floating Point.64-Bit Datapath and TLB.

• Pipeline chosen for performance and economy.

• Flexible system interface for wide range of applications.

August2, 1991 27 ｾｭｩｰｳ

1.19