MKEL 1173 Advanced Digital DesignAdvanced Digital Design Behavioural RTL Modelling In FSMD HDL...

MKEL 1173Advanced Digital Design Advanced Digital Design

Digital System RTL Design

MKEL 1173Advanced Digital Design Advanced Digital Design

Digital System RTL Design – FSMD

Advanced Digital Design

Controller – Datapath partition

Digital system is sequential circuit made up of interconnected FFs and gates usually partitioned into two units

control unit (CU)

datapath unit (DU)

DU consists of registers, bussing and processing logic.

CU issues control signals that sequence microDU.

Chapter 6 – FSMD

Datapath partition

Digital system is sequential circuit made up of interconnected

DU consists of registers, bussing and processing logic.

CU issues control signals that sequence micro-operations in

2


CU and DU relationship

Computation &Processing units

Storage/ Registers

Bussing and Steering Logic

DU

Data input

FSM

ps ns

CU

Externalcontrol inputs

feedbacksignals

Chapter 6 – FSMD

Computation &Processing units

Storage/ Registers

Bussing and Steering Logic

Data output

additionalcircuitry

Commands orControl signals

Status signals

3


Structural RTL Modelling

In FSM+D HDL model, control and datapath units are partitioned into two separate sections of HDL code control unit based on FSM

datapath components described explicitly with separate HDL code

this style of HDL-based Register structural RTL modelling

Chapter 6 – FSMD

HDL model, control and datapath units are partitioned into two separate sections of HDL code

datapath components described explicitly with separate HDL code

egister Transfer Level design is known as

4


Structural RTL Modelling – cont.

Data-dominated designs involve mainly data transfers and arithmetic operations (RTL operations) these designs typically computation

datapath section that processes computations dominates design

structural RTL design is suitable for data

Chapter 6 – FSMD

cont.

designs involve mainly data transfers and arithmetic operations (RTL operations)

computation-intensive

datapath section that processes computations dominates design

design is suitable for data-oriented digital system

5


Behavioural RTL Modelling

In FSMD HDL model, control and datapath sections are not separate parts of HDL code RTL operations are embedded within FSM model

datapath components implicitly defined

datapath is not explicitly described in code

o RTL operations are listed within corresponding FSM state

this style of HDL-based RTL design is known as this style of HDL-based RTL design is known as modelling

Chapter 6 – FSMD

HDL model, control and datapath sections are not

RTL operations are embedded within FSM model

datapath components implicitly defined in HDL code

datapath is not explicitly described in code

RTL operations are listed within corresponding FSM state

based RTL design is known as behavioural RTL based RTL design is known as behavioural RTL

6


Behavioural RTL Modelling

FSMD HDL modelling approach is suited for applications characterized by algorithm that shows dominance of decision

conditions and branching structures

Chapter 6 – FSMD

Behavioural RTL Modelling – cont.

HDL modelling approach is suited for control-oriented

characterized by algorithm that shows dominance of decision conditions and branching structures

7


FSMD

FSM with data effective technique in design of digital hardware that mainly performs

data processing

extension of conventional FSM

Within state expression, HDL model can have comparison operations, arithmetic, or logic operations on variables instead of just logic signals, RTL data operations such as data transfer

among registers and data manipulation operations can be specified in state blocks

FSM serves as control circuit that examines command and status signals generates control signals to specify operations in datapath

Chapter 6 – FSMD

effective technique in design of digital hardware that mainly performs

Within state expression, HDL model can have comparison operations, arithmetic, or logic operations on variables

instead of just logic signals, RTL data operations such as data transfer among registers and data manipulation operations can be specified in

FSM serves as control circuit that examines command and

generates control signals to specify operations in datapath

8


RTL Design Abstraction

Registers are basic components (primitives).

Datapaths defined by their registers and operations performed on the stored data.

Elementary operation performed on stored data is called micro-operation copy content of one register into another copy content of one register into another

add content of two registers

store result into register

shift and count

increment content of register

Chapter 6 – FSMD

Registers are basic components (primitives).

Datapaths defined by their registers and operations performed

Elementary operation performed on stored data is called

copy content of one register into anothercopy content of one register into another

9


RTL Design Abstraction – cont.

Almost all synchronous sequential digital systems can be viewed as a set of registers and operations that transfer data.

Movement and processing of stored data are termed RTL operations each RTL operation consists of elementary micro

RTL operations specified by three basic elements

• register set

• operations performed on register data

• sequence of operations

Digital system can be described and modeled by

RTL code uses notational system called Register Transfer Notation (RTN)

regA ← ƒ(reg1, reg2, …, reg

Chapter 6 – FSMD

cont.

Almost all synchronous sequential digital systems can be viewed as a set of registers and operations that transfer data.

Movement and processing of stored data are termed RTL

each RTL operation consists of elementary micro-operations

RTL operations specified by three basic elements

operations performed on register data

Digital system can be described and modeled by RTL code.

RTL code uses notational system called Register Transfer

, regn)

10


RTL Operation Examples

Notation Operation

X ← Y transfer contents of regY to

Rbus = Mbus connect output of Mbus to Rbus

X ← 0 clear regX

X ← Y + Z add contents of regY and regZ,

X ← Y | Z OR contents of regY with regZ,

Chapter 6 – FSMD

DR ← M[AR] load into DR the contents of

X ← M[00FFh] load into X the contents of

R1 ← R1 >> 1 right shift reg R1, with 0 into

X ← Y, A ← B Parallel transfers

(cond)/A ← B if cond =1 then transfer contents

S0: A ← B When in state S0, load regA

P: (a.b)/R2 ← R3 When in state P, if a AND b

to regX

connect output of Mbus to Rbus

regZ, load into regX

regZ, load into regX

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of memory pointed to by AR

memory at hex addr 00FF

into MSB

contents of regB into regA

regA with content of regB

b is true then load regR2 with contents of regR3


FSMD Example

A digital system is modelled by ASM6-1 R1, R2, R3 are 16-bit wide registers

x, y are 8-bit input data, start is control input

done is output

Initially, done is reset, input x is stored in y stored in R3.

Computation begins when start

On completion of computation, indicating that output is valid in register

RTL operations are performed in each state for e.g. in S1

R1 contents are shifted left by 1 bit

R2 is loaded with R12

Chapter 6 – FSMD

A digital system is modelled by ASM-chart in Fig.

bit wide registers

is control input

is stored in R1, input

0

start is asserted high.

On completion of computation, done is set, indicating that output is valid in register R1.

RTL operations are performed in each state

contents are shifted left by 1 bit

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FSMD Example – cont.

Verilog code using 1-segment codingmodule FSMDFig6_1 (input clk, reset, start,Input [7:0] x, y,output reg done,output reg [15:0]R1 );

reg [2:0] state;reg [15:0] R2, R3;parameter [2:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5;

Chapter 6 – FSMD

parameter [2:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5;always @ (negedge reset, negedge clk) begin

if (!reset) state <= S0;else case ( state )S0: begin

R1 <= {8’d0, x};R3 <= {8’d0, y};done <= 0;if (start) state <= S1;

endS1: begin

R1 <= R1<<1;R2 <= R1 * R1;state <= S2;

end

segment coding

S0=0, S1=1, S2=2, S3=3, S4=4, S5=5;

S2: beginR3 <= R3/3;state <= S3;

endS3: begin

R2 <= R3/R2;state <= S4;

endS4: begin

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S0=0, S1=1, S2=2, S3=3, S4=4, S5=5; S4: beginR1 <= R1/3;state <= S5;

endS5: begin

R1 <= R1 – R2;done <= 1;if (!start) state <= S0;

enddefault: state <= S0;endcaseend

endmodule


FSMD Example – cont.

Simulation result

Chapter 6 – FSMD 14


FSMD Synthesis

Since datapath components are implicitly defined in FSMD Verilog code we have no control on construction of datapath

we rely on synthesis software

In the example, synthesis tool may infer 3 dividers, since there are divider operations performed in states S2, S3, and S4.S4.

If this divider resource is shared, then more efficient design may be obtained.

Thus, FSMD method of modelling applied in this case (which is clearly a compute-intensive case) is not the right approach to define this digital system.

Chapter 6 – FSMD

Since datapath components are implicitly defined in FSMD

we have no control on construction of datapath

In the example, synthesis tool may infer 3 dividers, since there are divider operations performed in states S2, S3, and

If this divider resource is shared, then more efficient design

Thus, FSMD method of modelling applied in this case (which intensive case) is not the right approach

15


FSMD Exercise

Obtain ASM-chart for FSMD module FSMD_2module FSMD_2 (input rst, clk, p, q,output reg [7:0] A, B,output reg [15:0]R1 );

reg [1:0] s;parameter [1:0} S0 = 0, Sa = 1, Sb = 2, Sc = 3;

always @ (negedge rst, posedge clk)

Chapter 6 – FSMD

always @ (negedge rst, posedge clk)if ( !rst ) s <= S0;else case (s)

S0: begins <= Sa;if (p) A <= B;else A <= ~A;

endSa: begin

s <= Sb;if (p && !q) A <= 0;else if (!p && q) A <= ~B;

end

for FSMD module FSMD_2Sb: begin

s <= Sc;done <= 1;if (!p && !q) B <= A + B;else B <= A;

endSc: begin

s <= S0;done <= 1;

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done <= 1;end

endcase

endmodule


FSMD Design – GCD Calculator

Design specifications computes greatest common divisor (gcd) of a pair of 4

positive numbers

has start signal

initializes operand registers p, q

initiates computation process

asserts done signal when computation is completed asserts done signal when computation is completed

gcd outputs are valid

o stored in register r

Sample input and output inputs p = 0110, q = 1010

output gcd = 0010

Chapter 9

GCD Calculator

computes greatest common divisor (gcd) of a pair of 4-bit binary

signal when computation is completedsignal when computation is completed

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Algorithm and Moore ASM chartp = Pin;

q = Qin;

r = 0;

done = 0;

WHILE (p != q)

IF q > p THEN

p = q;p = q;

q = p;

ELSE

p = p – q;

END IF

END WHILE

r = p;

done = 1;

Chapter 9

GCD Calculator – cont.

Algorithm and Moore ASM chart

start

S0

0

S1

rst_b

0

1

1

p←Pinq←Qin

r←0done←0

start

S4

18

1

S2

S3

1

0

0

p=q

q>p

p←qq←p

p←p-q

r←pdone←1

S4



Algorithm and Mealy ASM chartp = Pin;

q = Qin;

r = 0;

done = 0;

WHILE (p != q)

IF q > p THEN

p = q;p = q;

q = p;

ELSE

p = p – q;

END IF

END WHILE

r = p;

done = 1;

Chapter 9


Algorithm and Mealy ASM chart

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Verilog code

Chapter 9


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Can you design an even better design?

Chapter 9


better design?

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MKEL 1173 Advanced Digital DesignAdvanced Digital Design Behavioural RTL Modelling In FSMD HDL...

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