IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. I, JULY 1986 955

Model for the Channel-Implanted Enhancement-Mode IGFET

Abstract-A simple dc four-terminal “channel-implanted model’’ is developed for the enhancement-mode IGFET. The model accurately predicts the dependence of transistor threshold voltage and current gain on substrate bias. Modeled and measured threshold voltages are ghown to agree to within 25 mV across a 15-V range of VsB. Modeled and measured transistor currents agree to within 5 percent across a LO-V range of Vss for medium- to long-channel length transistors (Ldrawn 2 2.5 pm). The channel impurity profile is approximated as a constant effective impurity concentration N,, extending from the semiconductor wrface through the implanted region to an effective implant depth X,, (‘‘box” profile approximation). At depths greater than X,,, the bulk substrate impurity Concentration is approximated as a constant, N A . ‘!?he model is composed of two threshold voltage equations, three drain :urrent equations, two saturation voltage equations, and two boundary :quatiom. All first-order model equations and all of their first deriv- Itives are continuous at all boundaries. The model’s continuity and its .kccuracy make it useful for circuit simulation. Extrapolation of chan- 11e1 concentration profile parameters N,,, X,,, and N , from measured I Iireshold voltages yields information on implant profile and on field- implant impurity encroachment into the transistor channel.

NOMENCLATURE

Distance from surface (insulator-semicon-

Distance along surface from source toward

Source-to-bulk voltage. Drain-to-source voltage. Gate-to-source voltage. Channel inversion layer-to-bulk voltage. Drain current. Elementary electronic charge. Relative dielectric constant of semiconduc-

Dielectric constant of free space. Gate-to-surface insulator capacitance (per

Effective channel width. Effective channel length. Effective channel mobility. Flat-band voltage. Gate-to-bulk threshold voltage. Gate-to-source threshold voltage.

ductor interface) into substrate.

drain.

tor.

unit area).

Sat Drain-to-source saturation voltage. Extrapolated gate-to-source threshold volt-

Effective implant impurity concentration

Effective implant depth into substrate. Effective substrate impurity concentration

Potential in the semiconductor. 4 is refer-

Surface-to-bulk potential at the onset of in-

Surface-to-bulk potential at the onset of in-

Volume charge density in the surface deple-

Surface depletion region width.

age with VsB = 0.

(per unit volume).

(per unit volume).

enced to the bulk potential.

version with VR(Y) = 0.

version ( 4 s I n v = ~ F T + VR(Y>>.

tion region.

XDMax Surface depletion region width at the onset -

of inversion.

(derived in Section 11-B and shown in

QB(Y) Charge density in the surface depletion re-

QBInv( Y ) QB( Y ) at the onset of inversion. QN( Y ) Charge density in the surface inversion layer

(per unit area). Qs(Y) Total charge density due to depletion and

inversion charges (per unit area).

vZB Boundary in channel-to-bulk bias potential,

(11)).

gion (per unit area).

A I. INTRODUCTION

LTHOUGH the channel-implanted enhancement- mode insulated gate field-effect transistor is used ex-

tensively in both analog and digital circuitry, its threshold voltage behavior and its current characteristics are not ad- equately predicted by the device model [l] most com- monly used in circuit simulation. Specifilcally, the clas- sical model ignores the second-order effects of the threshold voltage adjustment ion implant. Throughout the derivation of the classical model it is assumed that the impurity concentration from the surface through the bulk

Manuscript received January 7 , 1985; revised January 27, 1986. is constant. This assumption leads to a threshGld voltage :). M. Rogers and D. D. Rinerson are with the Non Volatile Memory dependence upon source-to-bulk voltag’e vsB, which is

94c 118. De>l-,lopment Group at Advanced Micro Devices, Inc., Sunnyvale, CA, p ropo~iona~ to (vsB + (bFT)1’2 . enhancement transis-

1. D. Hayden is with NCR Microelectronics, Colorado Springs, CO. tors~ the adjustment ion imp1ant 1 EEE Log Number 8608377. the threshold voltage dependence upon the source to bulk

0018-9383/86/0700-0955$01.00 O 1986 IEEE

956 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. I, JULY 1986

VSS (VOLTS)

1.8 0.0 0.8 2.25 4.1 6.45 9.3 12.7 16.5

1.6

8 1.4 3

:: 1.2

1 .o

0.8 - 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

\iG - b ’ G

Fig. 1. Threshold voltage behavior as a function of V,, for a 20 pm/4 pm n-channel enhancement transistor (4FT = 0.37 V). Solid points: mea- sured data. Broken line: best case fit of classical model. Solid line: best case fit of classical model increased 82 mV so that VT- Mode, = VT- Measured

at V,, = 1 V. Open circles: best case fit of channel-implanted rrodel reduced 12 mV so that VT-Model = VT-Measured at VsB = 1 V.

-SUPREM I1 SIMULATION

MODEL, (BOX) APPROXIMATION CHANNEL IMPLANTED

0.0 0.2 0.4 0.6 0.8 1.0

DEPTH X(pm) FROM SURFACE INTO SUBSTRATE

Fig. 2. The channel impurity profile predicted by the channel-implanted model for the 20 pm/4 pm transistor that was used in Fig. 1. The: tran- sistor’s SUPREMII simulation is also shown for comparison.

bias to deviate from the classical equation’s ( VsB + +FT)1’2

behavior (see Fig. 1). Consequently, the classical model incorrectly predicts threshold voltage and drain cwrent when used over a range of source-to-bulk biases. The problem becomes particularly apparent in circuit appli- cations where enhancement-mode transistors operate over a wide range of VsB, as in EPROM’s [ 2 ] , EEPROM’s, and analog and telecommunications circuits. Ignoring the variation in substrate impurity concentration can lead to errors in predicted threshold voltage of several hundred millivolts and errors in predicted drain current of more than 100 percent.

The purpose of this paper is to present a complete set of transistor model equations that takes into account the difference between the semiconductor surface anc. bulk impurity concentration levels. In this channel-implanted model, the concentration profile is approximated as a con- stant volume impurity concentration NAE that extend:$ from the semiconductor surface to a depth X,, (see Fig. 2 ) . NAE and X,, represent the channel implant volume concentra- tion and implant depth, respectively. At greater ldepths

than X,,, the bulk volume concentration is represented by NA. Dang and Iwai [3] referred to this arrangement as the “box” profile approximation.

The channel-implanted model consists of seven major equations and two minor equations. The major equations are two threshold voltage equations, three drain current equations, and two drain-to-source saturation voltage equations. The minor equations define boundaries in VsB, VDs, and VGs. Of the seven major equations, three are similar to the classical equations for threshold voltage, drain current, and saturation voltage [l]. The second threshold voltage equation and the second current equa- tion are presented in alternate forms elsewhere [4]-[8]. The third current equation is presented without derivation by Herr et al. in [8]. The second saturation voltage equa- tion and one of the boundary equations are published for the first time in this article. This is the first article in which the full set of equations needed for a simulation model based upon the “box” profile approximation has been published.

The basic channel-implanted model equations are de- rived in Section I1 of the paper. In Section 111 the accuracy of the model’s predictions and some of the model’s im- plications for device design and process development are discussed. The Appendix lists the particular second-or- der-effect equations that were used for both the classical model and for the channel-implanted model discussed in this paper.

11. MODEL DEVELOPMENT Throughout the derivation of the model’s equations, two

basic biasing cases occur. For small surface-to-bulk po- tentials, the surface depletion region resides only in the higher impurity-concentration implanted region (Case 1 : X , 5 X,,). For large surface-to-bulk potentials, the de- pletion region edge extends beyond the implant depth into the substrate (Case 2 : X , 1 X,,).

A . Maximum Depletion Region Width at the Onset of Inversion (XDMa.J

assumed and Poisson’s differential equation is solved. For both biasing cases, the depletion approximation is

d2+ P dx2 = --*

(1)

Potential in this derivation is referenced to the bulk (+[XDMax] = 0) . The surface or channel-to-bulk potential at inversion is approximated as

Ksfo

+SI”” = VR + +FT ( 2 ) where VR is the applied voltage from channel to bulk. +FT

is the energy band bending from bulk to surface at inver- sion when there is no applied bias VR.

Case I : (XDMax 5 X D E ) ; When the surface-to-bulk po- tential is sufficiently small that the depletion region width at the onset of inversion XDMax is less than the implant depth X,,, the equation for the depletion width is similar to the classical equation [ 11. The new equation for XDMax

ROGERS ef ai.: MODEL FOR CHANNEL-IMPLANTED IGFET 957

is the same as the classical equation except that the clas- sical equation’s substrate impurity concentration N A is re- placed by the implanted layer concentration N A E .

Case 2: (XDMax 2 &): When the maximum depletion region width at the onset of inversion exceeds the implant region depth, the calculation of the depletion region width parallels the calculation for Case 1 . But, the calculation must take into account the two regions of differing im- purity concentration. Poisson’s equation must be solved for values of X between X,, and X D M a x before it can be solved for values of X that are less than X,, (Case 2a: X,, I X 5 X D M a x , and Case 2b: X I X,, I X D M a x , respec- tively).

Case 2a: (XDE 5 X 5 XDMa.J: The potential in the part of the depletion region that resides in the bulk semicon- ductor is described by Poisson’s differential equation (see (1) ) . Assuming the depletion approximation

P -qNA (4) ,and integrating (1) from X = XDE to X = XDMax yields

where the constant of integration was found by noting that I,rl$/dX) = -E = 0 at the depletion region edge X = hDMax (E represents electric field). Integrating ( 5 ) from X ::= X,, to X = XDMax and noting that $(XDMax) = 0 results

11 I n

Case 2b: (X 5 X,, I XDMax): The potential in the de- pletion region between the surface and X,, is also de- scribed by Poisson’s equation. Assuming the depletion allproximation for this region results in

Inlegrating (1) from X = 0 to X = XDE yields

Th: constant of integration in (8) was determined by not- ini; that ( 5 ) and (8) must be equivalent at X = X D E .

!P second integration results in

In IS) the constant of integration is determined by noting thal (6) and (9) are equivalent at X = XDE. Setting X equal to x r o in (9) and setting + ( X ) equal to yields the

general relation for the depletion region width at inversion for Case 2 ( X D M a x 1 X D E ) .

B. Boundary In Channel To Bulk Bias Potential VzB The boundary in the channel-to-bulk potential between

Case 1 and Case 2 occurs at the potential that causes the depletion region width at inversion XDMax to be equal to the implant depth X D E . Setting X D M a x equal to X,, in either (3) or (10) and solving for VR yields [a]

C. Threshold Voltages The general form of the gate-to-bulk threshold voltage

is derived by summing the voltage drops from gate to bulk at the onset of inversion.

VTB = VFB + (PSInv(Y> - --. Q B ( U

CO (12)

Case 1 : (VsB I VzB, XDMax I X D E ) : The depletion re- gion charge at the onset of inversion for Case 1 is found from the depletion approximation and (3).

Q B I ~ ~ ) = -(2KSEOqNAE[VR(y) f (PFT1>1’2* (13) Substitution of (13) into (12) results in the Case 1 relation for gate-to-buik threshold voltage ( VR(0) = VsB).

(14) This equation is in the same form as the classical thresh- old voltage equation where the substrate impurity concen- tration N A is replaced by the implant region impurity con- centration N A E [l]. Subtracting VsB from (14) results in the gate-to-source threshold voltage VT. Furthermore, set- ting VsB equal to zero in the result yields VTH, the gate- to-source threshold voltage with zero source bias.

Subtracting VsB from (14) and eliminating VFB by substi- tuting (15) results in the Case 1 gate-to-source threshold voltage equation.

Vi“ = VTH + rl[(vSB + $FT)’’2 - ( ( P F T ) ’ ” ] (16) where

VFB is eliminated in (16) so that the more easily measured quantity VTH can be used instead.

Case 2: (VsB 1 VzB, X D M a x 2 X D E ) : The total charge in the depletion region at the onset of inversion for Case

2 is the sum of the charges contained in the implanted portion of the depletion region and in the bulk portion of the depletion region.

Equation (1 8) is substituted into (12) and the result is re- duced by VsB to yield the gate-to-source threshold voltage for Case 2. Equation (15) is also substituted to eliminate VFB .

where

Equation (19) was reported previously in different forms by several authors [4]-[6], [8]. It is important to note that (16) and (19) are continuous at their boundary, VsB = VzB. Their first derivatives are also continuous at that bound- ary. Equation continuity and derivative continuity are generally required features of any model that is used in a circuit-simulation environment.

D. Current Equations There are three current equations in the channel-im-

planted model. Each of the three is valid for a separate region of transistor operation. The first equation is valid when the surface depletion region width across the entire channel is less than the effective implant depth (see Fig. 3(a)). The source-to-bulk potential and the drain-to-bulk potential are both less than the boundary potential VzB (Region 1 : VsB 5 VDs + VsB 5; VzB). The second (:qua- tion is valid when the depletion region width at the slmrce is less than the effective implant depth and the depletion region width at the drain exceeds the effective implant depth (Region 2: V,, 5 VzB 5 VDs + V S B , Fig. 3(b)). The third equation is valid when the surface depletion re- gion width across the entire channel exceeds the efkctive implant depth (Region 3: VzB 5 VsB 5 VDs + VsB, Fig.

The development of the current equations proceeds in the normal manner [l]. The inversion layer charge is found by first writing the general equation for gate-tl3-bulk potential as a function of position ( Y ) between source and drain.

3 (c)).

958 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 7, JULY 1986

stant along the entire channel length. The inversion layer

\ //. LY SOURCE

N+ DEPLETION

c--------- DRAIN

N' (NAE) ., 1 k I X-XDE) (NA)

- 1 I \ 1- I / \ I

\

X t P- SUBSTRATE \

\ -. J ----

I / cy

SOURCE DRAIN

DEPLETION (N*) /-----

\

Fig. 3 . Transistor cross sections showing the positions of the depletion regions for the three regions of transistor bias used in the current equa- tion derivations. (a) Region l : vs, I VDs + VsB I VzB. (b) Region 2: v s ~ I vzs I VDS + v38. (C) Region 3: VZB I Vsa I VDS + V S B .

The total charge in the semiconductor at a given bias is

For all three regions of transistor bias, the current-volt- age relation for a differential of channel length dY be- tween the source and the drain is given by

In (24) the effective mobility UEFF is assumed to be con-

ROGERS et al.: MODEL FOR CHANNEL-IMPLANTED IGFET 959

thickness and the inversion layer charge are assumed to vary gradually from the source to the drain (gradual chan- nel approximation). Equation (24) is multiplied by QN ( Y ) and is integrated from source to drain.

VDS + VSB LEff S - QN(VR( Y ) ) * dVR(Y) = S dY. VSE wEff UEff 0

(25) The form of the equation for inversion charge Q, at a particular point Y in the channel depends upon the applied bias VR(Y) between the channel charge and the bulk.

Case 1: (VR(Y) 5 VzE, XDMax 5 XDE): The relation for inversion charge, when the channel-to-bulk potential VR(Y) is less than the boundary potential VzE, is found by substituting (1 3) into (23).

Q N - c ~ ~ ~ I = -CO(J“GB - VFE - ~ F T - Tr,(Y))

+ (2KSeOqNAE[VR(Y) + +FT1>”2. (26) Case 2: (VR(Y) 2 VzB, XDMax 2 XDE): The inversion

lhyer charge for the case when the channel-to-bulk poten- ial VR(U is greater than the boundary potential V,, is “ound by substituting (1 8) into (23).

! ‘ 1 ? ~ - ~ a s e 2 = - CO(VGE - VFB - ~ F T - VR(Y))

+ qNAEXDE

(27) Tn obtain the three current equations, the integration s?,,Dwn in (25) is performed separately for the three re- giIons of transistor bias.

Region 1: (VsE 5 VDS + VsE 5 V Z E ) : When the surface dcpletion region width XDMax is less than the effective im- pl ~ n t depth X,, along the entire length of the channel, the development of the current equation is analogous to the development of the classical current equation [ 11. Equa- tion (26) is substituted into (25) and the integration is per- fomed.

2

2 - - 3 Ti [(VDS + VSB + 4FT)3” - (VSB i- 8FT)3’21].

(28) VFB is defined by (15). Equation (28) is the same as the clasilical current equation except that NAE is substituted for . V A .

Region 2: (VsE I VzE 5 VDS + J‘SB): For this biasing situation, the depletion region at the source is contained within the implanted layer (X,,,, I XDE). The depletion region at the drain extends into the bulk ( X D M ~ ~ 2 XDE). At some point between the source and the drain, the chan- nel-to-bulk potential VR(Y) equals the boundary potential VzE. At that position, the surface depletion region width XDMax equals the effective implant depth XDE. The inte- gration shown in (25) is separated into two parts to ac- commodate the two bias-dependent equations for inver- sion layer charge (see (26) and (27)) .

VDS f VSB I D LEff - = S COIVGE - vFE

UEff VSB

- 4 F T - V R ( y ) l dVR(Y)

r VDS -t VSE

Performing the integrations results in the current equation for Region 2.

2

1

This equation is presented in alternate forms in [7] and

Region 3: (VzE 5 VsE < VDs + VSE): Equation (27) describes the inversion layer charge density when the sur- face depletion region extends into the bulk along the en- tire channel length (XDMax 1 X,,). The integration shown in (25) is performed and results in the Region 3 current equation.

[81*

960 IE.EE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 7 , JULY 1986

This equation is presented in an alternate form by Herr et al . , [8]. As was true with the two threshold voltage equa- tions, the three current equations and their first deriva- tives are continuous at their boundaries in V,, and VD, .

E. Drain-To-Source Saturation Voltages The saturation voltage analysis results in three model

equations. Two equations describe the saturation voltage relations for two separate biasing conditions. The third equation defines the boundary in gate-to-source voltage that separates the two saturation voltage biasing condi- tions.

The drain-to-source voltage reaches saturation when the drain-to-bulk potential becomes large enough to reduce the inversion layer charge in the channel at the drain to zero. If the drain-to-bulk potential is greater than or equal to the drain-to-bulk saturation potential (VDs - Sat + bIsB) ,

the potential at the drain end of the inversion layer is equal to the drain-to-bulk saturation potential. It is the pote ltial from the drain end of the inversion layer to the bulk that determines which equation for inversion layer charge: ap- plies for a particular biasing situation (see (26) or (:!7)). When the channel-to-bulk saturation potential is less than VzB, (26) is used. When the potential exceeds VzB, (27) is used.

Condition 1: {VDs- Sat I VzB, XDMax I X D E ) : A1 sat- uration, the inversion layer charge at the drain defined by (26) is equal to zero. V, in (26) is solved for in this con- dition and is equal to (V,, - Sat + VsB). V,, - Sat for Con- dition 1 is the same as the classical equation for saturation voltage except that NA is replaced by NAE [ 11.

vDs- Sat = vGs - vTH + T ~ ( ~ F T ) I ’ ~

(32)

Condition 2: (VDs - Sat 2 Vze, XDMax 2 X D E ) : t f the channel-to-bulk potential exceeds V, , at the drain and causes the surface depletion region to extend into the bulk, then (27) is the valid equation for inversion layer charge. At the onset of saturation, the inversion layer charge near the drain is equal to zero and V, is equal to (VDs .. Sat + V,,). Performing these substitutions in (27) and s3lving for the drain-to-source saturation voltage yields

(33)

To this point, the boundary (V,, - Sat + VsB = VzB) be- tween the two equations for saturation voltage has itself been expressed in terms of saturation voltage. The bound- ary equation is replaced by a boundary in gate-to-source voltage between Condition 1 and Condition 2. To solve for this boundary, the quantity (VzB - VsB) is substituted into (32) or (33) for the term VDs - Sat. Solving for VGS produces the boundary in VGs between the two saturation voltage bias conditions.

I/GSBound = VZB - VSB + ‘TH

+ rd(Vz, + 4 F T I 1 / * - ( 4 F T ) 1 1 2 1 . (34) If V G , is less than then (32) is used for the sat- uration voltage. If VGs is greater than VGSBound, then (33) is used. When the transistor is in saturation (VDs 2 V,, - Sat), the saturation voltage VDs - Sat is substituted for V,, in the appropriate current equation to obtain the tran- sistor current. Like the threshold voltage equations and the current equations, the two saturation voltage equa- tions and their first derivatives are continuous at their boundary.

In summary, there are seven major equations and two boundary equations in the channel-implanted model. There are two threshold voltage equations (( 16) and (19)), three current equations ((28), (30), and (31)), and two saturation voltage equations ((32) and (33)). One bound- ary equation in VsB (see (1 l)), is used in conjunction with the threshold voltage equations and the current equations. The other boundary equation in VGs (see (34)), is used in conjunction with she saturation voltage equations.

111. MODEL PREDICTIONS AND MODEL ACCURACY Model parameters VTH, NAE, X D E , and N A are deter-

mined empirically for a particular transistor by fitting the threshold voltage equations to measured threshold volt- ages. It is interesting to compare the actual transistor’s impurity concentration depth profile with the approximate profile predicted by the model through parameters NAE, X D E , and N A . Threshold voltage measurements were made on n-channel enhancement transistors that were fabricated on {loo} silicon substrates. The starting material had an acceptor impurity concentration of 7.5 X 1014 atoms/cm3. A threshold voltage adjustment ion implant was per- formed by implanting boron icns at a concentration of 8 X 10” ions/cm2 through 280 A of thermally grown SiO,. The implant energy was 32 keV. Fig. 2 shows an approx-

ROGERS e? ai.: MODEL FOR CHANNEL-IMPLANTED IGFET 96 1

imate acceptor impurity concentration profile that is based upon the extrapolated values of parameters NAE, X D E , and NA for a 20 pm/4 pm transistor. A SUPREM I1 simulation of the actual concentration profile is also shown for com- parison.

Measured threshold voltages as functions of source-to- bulk voltage are shown in Fig. 1 for the same 20 pm/4 pm transistor. Threshold voltage curves corresponding to the channel-implanted model and to the classical model are also shown. The best case fit threshold voltage func- tions for both models were raised or lowered so that the model thresholds matched the measured thresholds at VsB = 1 V. These adjustments were necessary for the accurate acquisition of mobility parameters and were accom- plished by modifying the flat-band voltage in each model.

The success of the mobility parameter extraction method that was used for these models depends upon hav- ,ng each model’s threshold voltage match the measured 1.1reshold voltage at the bias conditions that are used for ]nobility measurement (VsB = 1 .O V). Without the clas- :,ical model’s 82-mV threshold voltage increase, its drain ,:*urrent characteristics would be grossly inaccurate for gate

Atages near threshold voltage. The 12-mV threshold 7,oltage reduction in the channel-implanted model has a 1;c:gligible benefit for model accuracy because the reduc- t ~ o n is relatively small. However, the channel-implanted ruodel threshold voltage is reduced for the sake of consis- t;:ncy with the classical model procedure.

Fig. 1 highlights the threshold voltage accuracy advan- t;i;;es of the channel-implanted model. Prior to adjust- n.l:nt, the channel-implanted model threshold voltage fl ...?ction was within 12 mV of the measured threshold vloltages across a 0 to 15 V range of VsB. The 12-mV re- d liction in the channel-implanted model threshold voltage iraxeases the 12-mV error to a maximum error of 25 mV. In comparison, the classical model threshold voltage dis- pl,jys errors that are as large as 100 mV before adjust- m6:nt. After threshold voltage adjustment, the classical m’odel’s error is almost 200 mV. On some long- and nar- rowchannel transistor geometries, the classical model thitr>shold can be in error by more than 200 mV before ad] xstment . The classical threshold voltage equation’s de- viziiion from measured values occurs because the classical model’s derivation ignores the variations in impurity con- C ~ T , :ration that are caused by the channel implant.

I! (Ieasured current characteristics, channel-implanted mo;iel current characteristics, and classical model current characteristics, are compared over wide ranges of V , , and VG,s in Fig. 4(a)-(f) and in Fig. 5(a)-(f). The curves sho,vn in Fig. 4(a)-(f) come from the 20 pm/4 pm tran- sistl:r that was used for Figs. 1 and 2. Fig. 5(a)-(f) com- parts curves for a 20 pm/1.5 pm transistor. The channel- implanted model and the classical model both accurately precict the measured characteristics for large gate volt- age! (Fig. 4(a)-(c) and Fig. 5(a)-(c)).

The classical model’s drain current predictions deviate sign ~ficantly from the 20 pm/4 pm transistor’s measured char Ecteristics at low gate voltages (Fig. 4(d)-(f)). This

deviation occurs because the classical model cannot ac- curately predict threshold voltage dependence upon VsB. In contrast, the channel-implanted model’s drain current predictions are within 5 percent of the measured values for the same low gate voltage conditions. This drain cur- rent accuracy for gate voltages near threshold is made possible by the channel-implanted model’s threshold volt- age accuracy.

Low gate voltage characteristics for the 20 pmll.5 pm transistor are shown in Fig. 5(d)-(f). The classical mod- el’s predictions of drain currents in Fig. 5(d) and (f) again deviate from the actual currents because the classical model does not accurately predict threshold voltage de- pendence upon VsB, The channel-implanted model tracks the low gate voltage characteristics of the 20 pm/ 1.5 pm transistor through the transistor’s linear region of opera- tion (V,, s V,, - Sat). This linear-region tracking indi- cates that the channel-implanted model’s threshold volt- age equations (( 1 l ) , (16), and (19)) and current equations ((28), (30), and (31)) are reacting correctly to changes in source-to-substrate bias.

In the 20 pmll.5 pm transistor’s saturation region the channel-implanted model deviates from the actual transis- tor’s characteristics. This deviation appears to be caused by short-channel effects, and may indicate the need for a VsB-dependent drain-induced barrier-lowering relation. Possibly a channel-length modulation equation that more accurately takes into account VsB variation is also needed. The drain-induced barrier-lowering equations [9]-[ 111, [14] and the channel-length modulation equations [12]- [14] that were used in both models are shown in the Ap- pendix (see (A3) and (A$)).

In addition to drain-induced barrier lowering and chan- nel-length modulation, other second-order effects were also taken into account in both the classical model and in the channel-implanted model. These effects include mo- bility reduction due to gate-to-channel electric field [ 141- [16], carrier velocity saturation [14] , [17], and effective channel lengths and effective channel widths. Equations that describe these effects -are contained in the Appendix.

The channel-implanted model makes predictions that are significant to transistor design and process develop- ment. Threshold voltage sensitivity to changes in VsB is reduced by making the channel implant very shallow. In a typical MOS process, the threshold voltage as predicted by the Case 2 threshold voltage equation (see (19)), is much less sensitive to variations in VsB than is its Case 1 counterpart (see (16)). According to (1 1 ) 7 the boundary VzB in source-to-bulk bias between the two threshold volt- age equations (( 16) and (19)) can be negative if the chan- nel implant depth X,, is made small. Transistor threshold voltage is much less sensitive to changes in VsB if the channel implant depth X,, is made small causing the value of VzB to be less than VsB.

Extrapolated values of threshold voltage parameters VTH, NAE, XDE, and NA, are dependent upon transistor ge- ometry. As is shown in Table I, the values of NAE and NA tend to increase as transistor width becomes small. This

962 IEI?E TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 7, JULY 1986

0 1 2 3 4 5 6

VDS (VOLTS)

(a)

160

120

t2Orm/4am VSB = 0.0 VOLTS A

40

I I I I I 0 1 2 3 4 5 6

VDS (VOLTS)

(d)

8 1 20pm14pm VSI! = Vzs = 1.11 VOLTS I

0 1 2 3 4 5 6

VDS(VOLTS)

(b)

20

0

1 20rm14pm VSB = 10.0 VOLTS 1

j Z o [ -2Ojm/4$m Vss = 10.OVOLTS I 100

08 I I 1 0 1 2 3 4 5 6

VDS(VOLTS)

( f )

Fig. 4. 20 pm/4 p n transistor drain currents are plotted as functions of applied drain-to-source, gate-to-source, and source-to-substrate volt- ages. Open circles: measured values. Solid lines: channel-implanted model. Broken lines: classical model. Where not shown, the classical model is coincident with the channel-implanted model.

effect is at least partially caused by field implant impuri- ties that have diffused into and beneath the transistor channel from the transistor sides. This field implant im- purity encroachment dominates the threshold voltage characteristics of long narrow-channel devices. Yamagu- chi and Morimoto [6] confirm this view. Extrapolation of parameters NAE and NA can act as an aid in monitoring and controlling field impurity encroachment.

IV. CONCLUSIONS A complete set of insulated gate field-effect trans)istor

model equations was presented. The derivation O F the equations takes into account the effects caused by the threshold voltage adjustment ion implant. The channel- implanted model is suitable for use in circuit simulation. It can be accurately matched to actual transistor threshold voltage characteristics over a wide range of source-to-bulk bias. It can accurately predict drain current characteristics over a wide range of source-to-bulk bias. All of the first- order model equations and all of their first derivativ'zs are continuous across all boundaries. Extrapolated values of the model parameters that govern threshold voltage de- pendence on source-to-bulk voltage (NAE, X,,, and NA) were shown to agree reasonably well with actual device process parameters. It was also demonstrated that the channel-implanted model can be used as an aid in device development and process characterization.

APPENDIX MODEL SECOND-ORDER EFFECTS

The classical model and the channel-implanted model that were shown in Figs. 4 and 5 included various second- order effects. The equations that embody the effects are fairly standard and are shown here merely for the sake of completeness.

A . Second-Order Effects Symbols

WMASK AW

LMASK AL

FDS ESAT

VDSA UO F1 F2 x MCL

Channel width defined by mask. Channel width reduction due to field implant

impurity encroachment and due to field ox- ide thickness encroachment (LOCOS pro- cess).

Gate electrode length defined by mask. Channel length reduction due to lateral diffu-

sion of source and drain implant impurities beneath gate.

Drain-induced barrier-lowering factor. Critical electric field. Applied drain-to-source voltage. Low field mobility. Mobility reduction factor, Mobility reduction exponent. Channel length modulation factor. Channel length modulation exponent.

ROGERS er a i . : MODEL FOR CHANNEL-IMPLANTED IGFET 963

0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6

400 360 360

300 270 270

a 3 200 ,s 5 180 J 180 -

100 90 90

0 0 . o 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6

Vos(V0LTS) Vos(V0LTS) Vcls (VOLTS)

( 4 (e) (f)

Fig. 5 . 20 p d 1 . 5 p n transistor drain currents are plotted as functions of applied drain-to-source, gate-to-source, and source-to-substrate volt- ages. Open circles: measured values. Solid lines: channel-implanted model. Broken lines: classical model. Where not shown, the classical model is coincident with the channel-implanted model.

TABLE I IPARAMETER VALUES EXTRACTED FROM MEASURED THRESHOLD VOLTAGES

($FT = 0.37 V)

WDRAWN Gun) LDRAWNG~)

20/20 10120 6/20 3/20 2019 2014 20/3

20/1.5 3/2.5

(VOLTS) VTn

0.837 0.877 0.896 0.906 0.825 0.808 0.802 0.779 0.826

1.46 x 10l6

1 . 6 6 ~ 1 0 ' ~ 1 . 9 7 ~ 1 0 " 1.45 x 1.37 x IOi6 1.31 x 10l6 1 . 1 5 ~ 1 0 "

1.63 x 10l6

1.68x1016

XDE

0.355 0.336 0.303 0.321 0.353 0.374 0.370 0.345 0.300

Gm)

8" Effective Geometries

= wMASK - Aw (All

L ~ f f = LMASK - u. (A21 C. Drain-Induced Barrier Lowering [9]-[1 I ] , [I 41.

equal to IyTH in the first-order equations is reduced by an amount

D. Velocity Saturation and Effective Drain-to-Source Voltage in Saturation [14,7, [I 71

The drain-to-source voltage VDs in the first-order equa- tions is replaced by the effective value of drain-to-source voltage shown below. Replacing VDs by VDs - SAT for the transistor operating in saturation is actually part of the first-order equations (and was mentioned in Section 1 1 4 ) .

E. Mobility Reduction with Gate-to-Channel Electric Field [I 4]-[14]

F. Channel Length Modulation- Transistor In Saturation [12]-[14].

When the transistor is in saturation (VDsAIFp 2 VDs - Sat), the value of L E r in the current equations (see (28), (30), and (31)) is replaced by

LEff = LEff - Fp2McLX[(VDSA - F@vDS- Sat

+ 4F*)1'2 - (4FT)1'21. (A@

964 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 7, .IlJLY 1986

MODEL PARAMETER EXTRACTION METHOD Extraction of model parameters for the channel-im-

planted model and for the classical model was performed in steps. Threshold voltages were measured at various values of VsB and VDs. Threshold voltage parameters werr: calculated from measured threshold voltages ( VTH, N A E ,

N A , XDE, and FDs for the channel-implanted model; VTh, body factor y and FDs for the classical model). Parameters AL and AWwere calculated from measured value of trans- conductance. Drain currents were measured under various biasing conditions and values for the mobility parameters were calculated, (Uo, F , , and F2). Drain currents wel’e measured with the transistor in saturation and values were calculated for channel length modulation parameters X ard MCL. All other model variables were constant.

ACKNOWLEDGMENT The authors wish to thank L. Razouk and M. Radwin

for valuable discussions on this and related topics. We wish to thank S. Longcor and A. Kobrin for the SUPRElVl I1 simulations. We wish to thank J. Stanczak and Non

[15] E. Demoulin, J. A. Greenfield, R. W. Dutton, P. K. Chatterjee, and A. F. Tasch, 3r., “Process statistics of submicron MOSFET’s,” in IEDM Tech. Dig., pp. 34-37, 1919.

[16] M. H. White, F. Van De Wiele, and J . P. Lambot, “High-accuracy MOS models for computer-aided design,” ZEEE Trans. Electron De- vices, vol. ED-27, no. 5 , pp. 899-906, May 1980.

[17] Y . El-Mansy, “MOS device and technology constraints in VLSI,” ZEEE Trans. Electron Devices, vol. ED-29, no. 4, pp. 561-573, Apr. 1982.

*

David M. Rogers (”81) was born in Salem, OR, on January 19, 1956. He received the B.S.E.E. and M.S.E.E. degrees from the University of Cal- ifornia at Santa Barbara in 1978 and 1980, re- spectively.

In 1980, he joined the MOS Dynamic RAM de- sign group at Advanced Micro Devices, Inc. He joined AMD’s MOS Non Volatile Memory De- velopment Group in 1981. Since 1980, he has been engaged in the development of several DRAM, EPROM, and EEPROM memory products. His

interests are in the areas of VLSI technolow develoDment. MOSFET de- Volatile Memory process development and process per- vice physics and modeling, and in the development bf devices for circuit

-. sonnel for providing the test devices. We‘ also wish to r e d ~ ~ a ~ ~ ~ ~ ~ ~ f ~ ~ ~ ~ ; f Eta Kappa Nu. thank E. Fong for assistance in preparing the text.

REFERENCES A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967, pp. 263-355. D. Rinerson, M. Ahrens, J. Lien, B. Venkatesh, T. Lin, P. Song, S. Longcor, L. Shen, D. Rogers, and M. Briner, “512K EPROM’s,’’ in ISSCC Dig. Tech. Papers, vol. 27, pp. 136-137, 327, Feb. 1984. L. M. Dang and H. Iwai, “Modeling the impurity profile in an ion- implanted layer of an IGFET for the calculation of threshold volt- ages,” IEEE Trans. Electron Devices, vol. ED-28, no. 1, pp. 116- 117, Jan. 1981. M . Kamoshida, “Electrical characteristics of boron-implanted

626, 1974. n-channel MOS transistors,” Solid-state Electron., vol. 17, pp. 621-

V. L. Rideout, F. H. Gaensslen, and A. LeBlanc, “Device design considerations for ion implanted n-channel MOSFET’s,” IBM J . Res. Develop., vol. 19, pp. 50-59, Jan. 1975. T. Yamaguchi and S . Morimoto, “Analytical model and charat:ter- ization of small geometry MOSFET’s,” IEEE Trans. Electron De- vices, vol. ED-30, no. 6, pp. 559-566, June 1983. P. P. Wang, “Double boron implant short-channel MOSFET,” IEEE

James D. Hayden (”83) received the B.S. de- gree in engineering physics from the University of Colorado in 1980 and the M.S. degree in electri- cal engineering from the University of Arizona in 1983.

He was employed as an RF test engineer at the U.S. Army Electronic Proving Grounds’ Electro- magnetic Environmental Test Facility from 1981 to 1983. From 1983 to 1985, he was a member of Advanced Micro Devices’ MOS Non Volatile Memory Development Group where he was in-

volved in device modeling for the development of EPROM and EEPROM products. In 1985, he joined an MOS process development group at NCR Microelectronics in Colorado Springs, CO.

Mr. Hayden is a member of Tau Beta Pi and Sigma Pi Sigma.

Trans. Electron Devices, vol. ED-24, no. 3 , pp. 196-204, Mar. 1977. N. Herr, B. Garbs, and J . Barnes, “A statistical modeling appr3ach for simulation of MOS VLSI circuit designs,” in IEDM Tech. Dig.,

L. M. Dang, “Drain-voltage dependence of IGFET turn-on volt- age,” Solid-State Electron., vol. 20, pp. 825-830, 1917. H. Masuda, M. Nakai, and M. Kubo, “Characteristics and limitation of scaled-down MOSFET’s due to two-dimensional field effwt,” Darrell D. Rinerson (”76) received the B.S. IEEE Trans. Electron Devices, vol. ED-26, no. 6, pp. 980-986, June 1979.

degree in physics in 1969 and the M.S. degree in electrical engineering in 1977 from the University

T. Grotjohn and B. Hoefflinger, “A parametric short-channel MOS of Minnesota, Minneapolis. transistor model for subthreshold and strong inversion current,” IEEE From 1969 to 1977, he was with Sperry Cor- Trans. Electron Devices, vol. ED-31, no. 2, pp. 234-246, Feb. 1984. poration in Roseville, MN, engaged in the design H. C. Poon, L. D. Yau, R. L. Johnston, and D. Beecham, “dc model and development of large computer memory sys- for short-channel IGFET’s,” in ZEDM Tech. Dig., pp. 156-159, 1973. tems. From 1977 to 1981, he was with Mostek R. M. Warner and B. L. Grung, Transistors, Fundamentals j3r the Corporation in Carrollton, TX, engaged in the de- Integrated-Circuit Engineer. New York: Wiley, 1983 pp. 807-808. velopment of MOS dynamic RAMS. Since 1981, L. Razouk, G. Marr, U. Ahmed, C. Tung, and M. Radwin, “Ad- he has been with Advanced Micro Devices, in vanced modeling,” Advanced Micro Devices internal commrmica- Sunnyvale, CA, and currently is the manager of the MOS Non Volatile tion. Memory Development Group.

pp. 290-293, 1982. *