Modeling of top and bottom contact structure organic field effect transistorsBrijesh Kumar, Brajesh Kumar Kaushik, and Yuvraj Singh Negi Citation: Journal of Vacuum Science & Technology B 31, 012401 (2013); doi: 10.1116/1.4773054 View online: http://dx.doi.org/10.1116/1.4773054 View Table of Contents: http://scitation.aip.org/content/avs/journal/jvstb/31/1?ver=pdfcov Published by the AVS: Science & Technology of Materials, Interfaces, and Processing

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Modeling of top and bottom contact structure organic field effect transistors

Brijesh Kumara)

Departments of Polymer and Process Engineering and Electronics and Computer Engineering, Indian Instituteof Technology, Roorkee 247667, India

Brajesh Kumar Kaushikb)

Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India

Yuvraj Singh Negic)

Department of Polymer and Process Engineering, Indian Institute of Technology, Roorkee 247667, India

(Received 30 August 2012; accepted 4 December 2012; published 26 December 2012)

This research paper proposes analytical models for top and bottom contact organic field effect

transistors by considering the overlapping of source-drain (S/D) contacts on to the organic

semiconductor layer and effective channel between the contacts. The contact effect is investigated

in the proposed models and further verified through two-dimensional (2-D) numerical device

simulation. The electrical characteristics are obtained from the linear to saturation regime and

analytical outcomes are compared with the simulation and experimental results, which shows good

agreement and thus validate the models. The extracted mobilities for top and bottom contact

structure include 0.129 and 0.0019 cm2/Vs, and the device resistance as 2.25 and 450MX and the

contact resistance as 2.25 and 450 MX lm2, respectively. The performance difference between top

and bottom contact is attributed to the structural difference and morphological disorders of

pentacene film around the contacts in bottom contact device which results in higher contact

resistance and lower mobility as compared to the top contact device. VC 2013 American VacuumSociety. [http://dx.doi.org/10.1116/1.4773054]

I. INTRODUCTION

Over the past several years, organic field effect transistor

(OFET) is under continuous development and extensively in

use for low cost display applications and flexible circuitry

owing to its compatibility with flexible substrates. Therefore,

its popularity has been enhanced due to its unique properties

such as ease of processing, lower temperature fabrication

process, lower production cost, and large area applications.1

It is well known that the performance of OFET does not

solely depend on the mobility of the semiconductor; how-

ever, the series (parasitic) resistance also plays an important

role. Ideally, it requires an Ohmic source and drain contact

for proper operation, whereas, in many practical situations,

the injection of charge carriers from metal to the semicon-

ductor is non-Ohmic, i.e., externally applied voltages partly

drop among the channel and the contact regions. The non-

Ohmic contacts affect the carrier movement and result in the

degraded performance.2 This non-Ohmic property can be

modeled by adding the contact resistances in series to the

source and drain terminals.

An OFET device constitutes three electrodes, i.e., source

(S), drain (D), and gate (G), a semiconductor, and a dielec-

tric layer.3 The relative position of the electrodes with

respect to the semiconductor and insulator confers two well

known bottom gate top contact (BGTC) and bottom gate bot-

tom contact (BGBC) structures. In top contact, the S/D con-

tacts are deposited above the organic semiconductor (OS)

layer through shadow masking, whereas microlithography

technique is used to place the contacts below the OS layer in

bottom contact devices. The inhomogeneities created in the

morphology of the OS due to deposition of the OS layer on

to the prepatterned contacts and higher contact resistance are

the major cause for the inferior performance of bottom con-

tact devices as compared to top contact.4,5

Various strategies have been extensively investigated in

the literature to deal with the effect of contact resistance

such as a transmission line method,6,7 Kelvin probe micros-

copy,8 and four-probe system.9,10 Recently, to extract the

contact resistance of experimental device, Nakao et al.11

proposed the method of probing the optical second har-

monic generation (SHG) signals, which enhance the carrier

injection mechanism around the injection electrodes, and

by applying different gate voltages, the SHG decay can be

observed in terms of the relaxation time (s)11 and further

the Maxwell-Wagner model is used to extract the contact

resistance (Rc), which can be represented by s¼RcCi,

where Ci is the dielectric capacitance. Further, Weis et al.12

highlighted the contact resistance behavior in terms of

thermionic emission model, and internal electric field

dependency on semiconductor thickness was analyzed in

the terms of carrier injection barrier and thus it has been

shown that the contact resistance gets affected by the gate

voltage.12

This paper investigates the analytical model for top and

bottom contact devices incorporating the effect of the series

and contact resistances which are the functions of gate volt-

age. Further, a two-dimensional device simulator ATLAS is

used for numerical simulation that predicts the electrical

characteristics associated with each device structure. Finally,

a reasonable match is shown among the analytical, numeri-

cal simulation, and experimental results that validate the

existence of the derived model.

a)Electronic mail: bkiitr@gmail.comb)Electronic mail: bkk23fec@iitr.ernet.inc)Electronic mail: ynegifpt@ iitr.ernet.in

012401-1 J. Vac. Sci. Technol. B 31(1), Jan/Feb 2013 2166-2746/2013/31(1)/012401/7/$30.00 VC 2013 American Vacuum Society 012401-1

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II. CONTACT EFFECTS IN OFET STRUCTURES

In OFET, the charge carriers travel across three segments,

as traversing from the source to drain electrode through the

channel of OS thin film. First of all, they are injected from

source contact into OS channel, then transported across the

length of the conducting channel, and finally extracted by

the drain. This movement of the carriers can be modeled as

three separate resistors in series arrangement as shown in

Fig. 1. The resistances linked with carrier injection and col-

lection steps are grouped into contact resistance, Rc, means

Rc¼RsþRd, while the resistance associated with the chan-

nel is termed as the channel resistance, Rch. For Ohmic con-

tacts, contact resistance must be small as compared to the

channel resistance, i.e., Rc<Rch, and therefore, the S/D con-

tacts perform the proper operation under the given bias con-

ditions but generally contacts are non-Ohmic in the nature.10

A. Contact resistance effect in top contact devices

Top contact structures usually have lower contact resist-

ance because of large effective area for injecting the charge

carriers in the OS channel at metal contact and OS thin film

interface13 as shown by the arrows indicating injection and

extraction of charge carriers in Fig. 2(a). However, the main

component that contributes the non-Ohmic contacts in the

top contact configuration is the access resistance.

Figure 3 shows the bumpy organic semiconductor thin film

near the accumulation layer and ovals represent the penetration

of top contacts deep into the OS thin film. The origin of the

access resistance arises from the path that the charge carriers

need to travel from the source contact to top of the OS thin film,

then down to accumulation layer at OS and dielectric interface,

and finally extracted from the drain contact through the top of

the OS film.10 The access resistance can be minimized by reduc-

ing the thickness of OS film. However, less impact of the access

resistance has been proposed in the literature for the top contact,

owing to large peak-to-valley roughness of OS film or type of

process used for metal deposition, and due to this fact, contact

metal penetrates the OS film down to accumulation layer and

provides easy flow to charge carriers.

B. Contact resistance effect in bottom contact devices

In this structure, access resistance plays no significant

role as the metal contacts and the conducting channel lie in

the same plane but contains large contact resistance due to

the very small effective area for charge injection into the

conducting channel as shown in Fig. 2(b). Moreover, in this

structure, OS layer is deposited on two different materials,

i.e., gate dielectric and S/D metal contacts simultaneously,

which causes differences in the surface energy and thus

surface roughness exists between the metal electrodes and

insulator layer. This surface energy difference forces the OS

film to adapt different microstructures in two regions and

causes the disorders in organic thin film near the S/D

contacts5 which results in larger S/D contact barriers and

contact resistance.

III. ANALYTICAL MODELING FOR ORGANICTRANSISTORS

The organic electronic material based devices are extensively

used for flexible displays and low-cost identification tags, which

FIG. 1. (Color online) Schematic of OFET showing equivalent resistances

corresponding to source, drain contact resistance, and channel resistance.

FIG. 2. (Color Online) Schematics of OFET devices: (a) top contact structure

(BGTC) and (b) bottom contact Structure (BGBC), in which arrows repre-

sent flow of current.

FIG. 3. (Color online) Top contact OFET schematic with access resistance

representation shown at metal contact and OS interface in accumulation

regime.

012401-2 Kumar, Kaushik, and Negi: Modeling of top and bottom contact structure OFET 012401-2

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is quite difficult to achieve with silicon technologies.6 To extend

the applicability of OFETs, it is necessary to establish a physi-

cally meaningful device model for both the structures. Both

the structures have same working principle but are different in

terms of their configuration14 and current–voltage characteris-

tics, owing to different contact/series resistance.15,16 In this

work, the current–voltage analytical model has been presented

for top contact OFET structure by using the concept of vari-

able series resistance near the source and drain contacts and

further extended for bottom contact structure by using the

contact effects analysis.

A. Analytical modeling for top contact OFET structure

Analytical model has been derived by considering cross

section of the top contact structure as shown in Fig. 4. Here,

drain current flows from source to drain electrode through

source resistance Rs, the channel resistance Rch, and drain re-

sistance Rd. Prior to driving the current voltage (I–V) model

of top contact structure, few assumptions is made; First, the

accumulation layer is induced not only in the channel but

also at the bottom of the overlap region. Second, sheet resist-

ance Rsh (X/sq) of accumulation layer is considered to be

uniform.17 Third, the drain current in the channel is assumed

to accumulate only through the accumulation layer, and the

net current in bulk semiconductor is zero and finally it is

assumed that the intrinsic S and D voltages, V0s and V0d, are

different from applied voltages Vs and Vd, respectively, due

to contact resistance Rs and Rd.17–19

To derive the current–voltage model under these assump-

tions, channel and overlap region is analyzed separately as

shown in Fig. 4. In the channel region, it is assumed that the

drain current flows only through accumulation layer and thus

the derived model is analogous to the MOSFET except the

effect of series resistance is also accounted. The drain cur-

rent in OFET can be defined by simple expressions20

Ids ¼W

LlCi ðVg � VtÞVds �

1

2V2

ds

� �: (1)

For linear regime, Vds� (Vg � Vt) and then

Ids ¼W

LlCiðVg � VtÞVds: (2)

For saturation regime, Vds> (Vg � Vt) and then

Ids ¼W

2LlCiðVg � VtÞ2: (3)

Due to contact effects, source Vs and drain Vd voltages are

replaced by V0s and V0d, respectively. Then drain current in

linear can be rewritten as

Ids ¼ lCiW

LðVg � VtÞ ðV0d � V0sÞ; (4)

where W, L, l, Ci, and Vt represent device width, channel

length, mobility, dielectric capacitance, and threshold volt-

age, respectively. Though all the device parameters such as

mobility and threshold voltage are known, but to obtain

drain current, first V0s and V0d voltages must find out.17 There-

fore, to obtain the voltage drop across a series resistance,

overlap region is considered as shown in Fig. 5, where V(x)

and Ix(x) represents the variable potential and current,

respectively, which changes with the position x. Jy(x) is the

current density that represents drain current flow only in

y-direction in the unit area. The apparent y-direction resistance

per unit area is denoted by a Ry which includes both the contact

and bulk semiconductor resistances, i.e., Ry¼RcontactþRbulk.

Since the accumulation layer is considered to be uniform, sheet

resistance of accumulation layer is same as Rsh in the channel.

Further by using these electrical quantities, few equations

have been derived for overlap region. The relation between

resistance and sheet resistance can be given by

R ¼ RshL

W: (5)

For Ix(x) and V(x), voltage change in small differential length

dx can be expressed as

Vðxþ dxÞ ¼ VðxÞ � IxðxÞRshdx

W: (6)

FIG. 4. (Color online) Schematic of top contact OFET device in linear region

with an intrinsic source (V0s) and drain voltage (V0d) in the channel region.

FIG. 5. (Color online) Schematic of source overlap region with conducting

channel in top contact structure.

012401-3 Kumar, Kaushik, and Negi: Modeling of top and bottom contact structure OFET 012401-3

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Further, as traversing from source contact to accumulation

layer, the change in potential across the contact and bulk

resistance that means along the y-direction resistance Ry is

determined as

0��

JyðxÞWdx� Ry

Wdx¼ VðxÞ: (7)

Since, Jy(x) contributes the current across the accumulation

layer, Ix(x) can be obtained by integrating y-direction current

density and is given by

IxðxÞ ¼ W

ðx

�L0JyðxÞ dx: (8)

In order to obtain expressions of Jy(x), Ix(x), and V(x), L is

assumed to be infinite. On eliminating Ix(x) and V(x) from

Eqs. (6) and (7), the differential equation can be obtained as

d2JyðxÞdx2

¼ Rsh

RyJyðxÞ: (9)

And further the solution of differential equation can be

expressed as21

JyðxÞ ¼ Jyc expx

Lc

� �; (10)

where Jyc is an integration constant and Lc, which termed as

characteristic length, is also a constant and can be obtained

as

Lc ¼ffiffiffiffiffiffiffiRy

Rsh

r: (11)

It is known that the sheet resistance(Rsh) and apparent

y-direction resistance Ry depend on the gate voltage (Vg),

therefore characteristic length Lc is also a function of Vg.

Further, the voltage V(x) and the drain current Ix(x) along the

accumulation layer can be obtained by amending the Jy(x)

in Eqs. (7) and (8) respectively and the expressions can be

written as;

IxðxÞ ¼ WJycLcexpx

Lc

� �(12)

and

VðxÞ ¼ �RyJycexpx

Lc

� �: (13)

Since S and D contact resistance act in the similar manner

for OFETs, the equations derived from source overlap

region are applicable for drain overlap region and thus the

total series resistance Rsd can be defined as the twice of

source resistance Rs.10 Though the maximum current flows

through the boundary (x¼ 0) of overlap region, Rsd can be

expressed as

Rsd ¼ 2Rs ¼ �2Vðx ¼ 0ÞIxðx ¼ 0Þ ¼

2Ry

WLc: (14)

It is observed from above equation that Rsd is inversely pro-

portional to Lc. Since Lc is a function of Vg; therefore, Rsd

also becomes Vg dependent, and at higher Vg, series resist-

ance decreases due to increment in Lc. Further, by applying

Kirchoff law along the source overlap region, V0s and V0d can

be obtained as

V0s ¼ 0� Vðx ¼ 0Þ ¼ RyJyc; (15)

V0d ¼ Vd � RyJyc: (16)

B. Drain current in the linear region

Drain current in the linear region can be obtained by sub-

stituting the values of V0s and V0d and Jyc in Eq. (4) and can be

simplified as

Idlin ¼ Ids ¼lCi

WL ðVg � VtÞVds

1þ lCi2Ry

LLcðVg � VtÞ

h i : (17)

C. Drain current in the saturation region

The accumulation charge at the drain end of the channel

(x¼L) can be expressed as

QL ¼ �CiðVg � Vt � VdsÞ: (18)

In the saturation regime, as the drain voltage reaches its satu-

ration value, i.e., Vds¼Vds(sat)¼ (Vg � Vt), the charge at the

drain end becomes nearly zero and the condition is called

“pinch-off” at x¼ L point and beyond the saturation value,

the drain voltage causes pinched-off the larger portion of the

channel. The portion of the channel, which is pinched-off,

reduces the length of the effective channel (Leff) and the

remaining channel can be defined as22

Leff ¼ L� DL; (19)

where DL is the segment of the channel with Q¼ 0 for

Leff< x<L and the voltage at point x¼ Leff becomes equal to

Vds(sat). The current equation for the saturation region with

replacement of L by Leff can be understood as the shortening

of the channel and represented as the “channel length modu-

lation” and an effective channel length becomes the function

of drain voltage. The current expression for saturation re-

gime can be modified in terms of Leff (Ref. 22)

Ids ¼ lCiW

2ðL� DLÞ ðVg � VtÞ2: (20)

Since Leff is less than the L, the drain current obtained from

Eq. (20) will be higher than the considering L. Though the

pinch-off segment depends upon the drain voltage, the em-

pirical relation can be expressed between DL and the drain

voltage as

012401-4 Kumar, Kaushik, and Negi: Modeling of top and bottom contact structure OFET 012401-4

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L

L� DL� 1þ kVds; (21)

where k is called the “channel length modulation coefficient”

and expression for drain current can be modified as

Ids ¼ lCiW

2Lð1þ kVdsÞðVg � VtÞ2: (22)

Due to contact effects, Vds can be rewritten as

Vds ¼ V0d � V0s: (23)

Further, Eq. (22) can be modified in the terms of intrinsic

drain voltage as

Ids ¼ lCiW

2L

�1þ kðV0d � V0sÞ

�ðVg � VtÞ2: (24)

On substituting the values of V0s, V0d , and Jyc, the expression

can be arranged as

Ids ¼ lCiW

2L1þ k Vds � 2Ry

Ids

WLc

� �� �ðVg � VtÞ2: (25)

Further the expression of drain current for saturation region

can be simplified as

Idsat ¼lCi

W2L ð1þ kVdsÞðVg � VtÞ2

1þ lCikRy

LLcðVg � VtÞ2

� � : (26)

To determine the drain current, all the parameters must be

known. Device parameters like mobility and capacitance are

already known, but other parameters like Rsh, Ry, and Lc are

unknown. Since it has been assumed that the accumulation

layer is almost uniform, sheet resistance Rsh along the accu-

mulation layer can be considered as constant. Sheet resist-

ance can be roughly obtained by using current–voltage

characteristics of OFET. Furthermore, to evaluate the series

resistance Ry various models have been proposed in Refs. 17

and 22–26 and those are based on total resistance versus

channel length plot,5,14 which is analogous to the channel re-

sistance method for MOSFETs.

The device total resistance Rtot is the ratio of total voltage

to the current and based upon the expression solved for the

drain current in the linear region; it can be expressed as

Rtot ¼Vds

Ids¼ L

lCiWðVg � VtÞþ 2Ry

WLc; (27)

Rtot ¼ RshL

Wþ 2Ry

WLc; (28)

Rtot ¼Rsh

W½Lþ 2Lc�: (29)

Further, the relationship between Rtot and L is plotted,

which is obtained as the straight line with the slope of Rsh/Wand y-intercept is as the series resistance as shown in Fig. 6.

Further, by relating Eqs. (27)–(29) with the Fig. 6, the

x-intercept, y-intercept, and triangular area can be expressed

in terms of W, Rsh, Lc, and Ry (Ref. 23) as shown in Table I.

Finally, by relating the Rtot versus L plot with Table I, pa-

rameters such as, Rsh, Lc, and Ry can be extracted. Though

the characteristic length Lc is the function of Ry and Rsh, it

can be calculated after determining Ry and Rsh.

D. Analytical modeling of bottom contact OFETstructure

It has been observed that the top and bottom contact

structure with the gate at the bottom can be differentiated on

FIG. 6. (Color online) Schematic of total contact resistance Rtot vs channel

length (L), in which x-intercept, slope, and triangular area are used for

parameter extraction.

TABLE I. Parameters extracted from Rtot vs L plot.

Name of parameters Parameters

Slope Rsh/W

x-intercept �2Lc

y-intercept 2Ry/WLc

Triangular area 2Ry/W

FIG. 7. (Color online) OFET device structures: (a) top contact structure and

(b) bottom contact structure.

012401-5 Kumar, Kaushik, and Negi: Modeling of top and bottom contact structure OFET 012401-5

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the basis of the series resistance due to their architecture.24

This contact resistance difference is discussed in Ref. 5,

where it has been calculated from plot of series resistance

(Rtot¼Vds/Ids) at different Vg and estimated for several chan-

nel lengths, and it is verified that the bottom contact exhibits

higher contact resistance as compared to the top contact

device.2,6,25–29 Therefore, the derived analytical model of

current–voltage characteristics of top contact structure can

also be applicable for bottom contact structure except the

higher values of Ry.27,28

IV. RESULTS AND DISCUSSION

This section analyzed the analytical, device simulation,

and experimental results5 for top and bottom contact struc-

tures as per shown in Fig. 7. To carry out the current–voltage

characteristics by using proposed analytical model equa-

tions, the values for channel length and width is considered

as 30 and 1000 lm, respectively. The characteristic length Lc

(lm) and channel length modulation coefficient k (V�1) are

taken as 2.79 and 0.035 for top contact and 0.20 and 0.05 for

bottom contact structure, respectively. The gold S/D and alu-

minum gate electrode are considered with the thickness of

20 nm, respectively. Further, silicon dioxide (SiO2) is taken

as the gate dielectric with the thickness (tox) of 200 nm and

dielectric constant of 3.9. Channel capacitance (Ci) of gate

dielectric is calculated as 1.65� 10�8 F/cm2.

The material properties5 such as band gap, electron affin-

ity, dielectric constant, and the density of both conduction

and valance band states in organic semiconductor, penta-

cene, is taken as 2.2 eV, 2.8 eV, and 4 and 2� 1021 cm�3,

TABLE II. Extracted performance parameters for top and bottom contact structures.

Top contact structure Bottom contact structure

Performance parameters Experiment (Ref. 5) Simulation Analytical Experiment (Ref. 5) Simulation Analytical

llin (cm2/Vs) 0.085 0.088 0.060 0.0014 0.0015 0.0012

lsat (cm2/Vs) 0.125 0.129 0.120 0.0017 0.0019 0.0014

Vt (V) �3.2 �3.5 �3.3 �8.5 �9.4 �9.1

Ids (lA) at Vds¼�25 V, Vgs¼�20 V �12 �11.9 �11.7 �0.210 �0.280 �0.290

Rtot (MX) at Vg¼�10 V 2.2 2.1 2.25 450 455 450

FIG. 8. (Color online) Comparison among the analytical, simulation, and ex-

perimental (Ref. 5) results of OFET output characteristics of (a) top contact

and (b) bottom contact structures.

FIG. 9. (Color online) OFET transfer characteristics comparison between the

analytical, simulation, and experimental (Ref. 5) results of (a) top contact

and (b) bottom contact structures.

012401-6 Kumar, Kaushik, and Negi: Modeling of top and bottom contact structure OFET 012401-6

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respectively. To perform the analytical calculations and de-

vice simulation, the parameter values are taken from the

experimental data5 as an initial. The structural parameters

for both the devices are kept same, for the appropriate com-

parison between them. The drain and gate voltages have

been chosen in such a way that could be able to make a com-

parison with the experimental result.5

The proposed analytical model has been validated using

their current–voltage characteristics of linear to the satura-

tion regime of both the structures. Subsequently, both the

structures are simulated in organic FET display module for

verification and validation of the analytical results with nu-

merical simulation and experiment. Further device perform-

ance parameters such as mobility (l), threshold voltage (Vt),

drive current (Ids), and resistance (Rtot) are extracted from

the Ids–Vds and Ids–Vgs characteristic plots27 and some of pa-

rameters are adjusted manually to get better fit24 as shown in

Table II.

The resulting output and transfer characteristic plots for

device simulation, analytical, and experimental results for

both the devices are shown in Figs. 8 and 9, and it can be

observed that the figures explore a fairly good match among

all the characteristic curves for top and bottom contact devi-

ces and thus produces validation of the analytical model.

V. CONCLUSION

The top and bottom contact devices exhibit difference in

drive current and characteristic performance parameters

such as threshold voltage, field effect mobility, and contact

resistance. The reason of the difference cannot be solely

attributed to the device structures; it also depends upon fab-

rication process, way of modeling, and material properties.

In bottom contact, the organic semiconductor film near

source/drain contact exhibits poor morphology as compared

to the film far away, which results in higher contact resist-

ance as compared to the top contact devices. The average

drive current between analytical and numerical device sim-

ulations for top and bottom contact devices are analyzed

which represents a good agreement of matching among

numerical device simulation, analytical, and experiment

results and hence validate the derived current–voltage

model for both the structures.

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012401-7 Kumar, Kaushik, and Negi: Modeling of top and bottom contact structure OFET 012401-7

JVST B - Microelectronics and Nanometer Structures

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