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Modeling Undeposited CNTs for

High Performance Design and the Evaluation of

Reliable CNTFET Circuits

A Dissertation Presented

by

Geunho Cho

to

The Department of Electrical and Computer Engineering

in partial fulfillment of the requirements

for the degree of

Doctor of Philosophy

in

Electrical Engineering

Northeastern University

Boston, Massachusetts

June 2012

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© Copyright 2012 by Geunho Cho

All Rights Reserved

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NORTHEASTERN UNIVERSITY Graduate School of Engineering

Dissertation Title: Modeling Undeposited CNTs for High Performance Design

and the Evaluation of Reliable CNTFET Circuits.

Author: Geunho Cho.

Department: Electrical and Computer Engineering.

Approved for Dissertation Requirements of the Doctor of Philosophy Degree

_______________________________________ _________________

Dissertation Advisor: Prof. Fabrizio Lombardi Date

_______________________________________ _________________

Dissertation Reader: Prof. Nian X. Sun Date

_______________________________________ _________________

Dissertation Reader: Prof. Marvin Onabajo Date

_______________________________________ _________________

Department Chair: Prof. Ali Abur Date

Director of the Graduate School:

_______________________________________ _________________

Dean: Prof. Sara Wadia-Fascetti Date

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Abstract

The Carbon NanoTube Field Effect Transistor (CNTFET) is one of the most

promising emerging technologies to extend and complement silicon MOSFET; this

is due to its excellent performance characteristics and similarity in operational

principles and device structure. During manufacturing, CNTs are usually grown or

transferred to a substrate with a fixed pitch prior to defining the gates and the

contacts. One of the likely defects occurs during the deposition of the CNTs, i.e. only

some of the required CNTs are deposited. These defects significantly affect the

performance of the CNTFET, because the number of CNTs present in the channel is

reduced and the distances between CNTs become uneven, thus causing changes of

current and capacitance.

This dissertation first suggests CNTFET circuit design methods to fairly compare

the performance between MOSFET and CNTFET by considering PDP, leakage, and

PVT variations. A detailed simulation-based assessment of the circuit performance

of CNTFETs is presented and compared to conventional MOSFETs. Then, to

evaluate the effect of the number and the position of undeposited CNTs, a

MATLAB-based model for a CNTFET is proposed. Initially, a comprehensive

characterization is pursued and new equations are found for the capacitance and the

drain current when undeposited CNTs are encountered following CNTFET

fabrication. With this proposed model, it is found that that the delay in a CNTFET

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significantly increases with the number of undeposited CNTs and the deviation in

delay depends on the position of the undeposited CNTs. To mitigate the effect of the

undeposited CNTs, two corrective processes are also proposed; these approaches are

based on adjusting the gate width of the CNTFET by lithography (and removing

CNTs) as part of the fabrication process. These two methods reduce the average

delay and its deviation, respectively. Generally, to evaluate the effects of

undeposited CNTs (such as uneven spacing between CNTs in a CNTFET) in a

CNTFET, different pitches (as distance between CNTs) must be simulated. However

in the current CNTFET HSPICE model, only a single pitch can be utilized. Therefore,

a new methodology using linear programming is proposed to find the parameters

(such as number, pitch, doping level, and chirality of CNTs) that can be used in a

CNTFET HSPICE model to represent the effect of uneven spacing. Finally, using the

proposed CNTFET circuit design and evaluation method, a methodology to design a

novel ternary CNTFET SRAM cell is proposed and its performance is evaluated

compared to a binary MOSFET and CNTFET-based SRAM cells with undeposited

CNTs.

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Acknowledgments

I would never have finished the doctorate program successfully without the

assistance and sacrifice of the following people.

First, I express my deepest gratitude to my advisor, Prof. Fabrizio Lombardi, who

has guided me not only with his vast knowledge and excellent insights but also with

his decent personality. I also heartily appreciate his support for my research in terms

of equipments and finances. I am also thankful to my other committee professors,

Prof. Nian-xiang Sun and Prof. Marvin Onabajo for their careful reading and

comments.

I would like to thank many Korean students at Northeastern University and my

friends in Korea for their help and encouragement. Discussions on diverse topics

with my officemates were also very beneficial to my research.

My parents have spent a large portion of their life in supporting my study. I

cannot dare to find words that express my appreciation for their sacrifice and love.

Whenever I felt exhausted and like giving up my study, there were my wife,

daughter, and son who have never allowed me to do so.

Finally, at this moment, it is a great grief to me that my advisor at Sogang

University, Jinwoo Choe, could not see this small academic achievement of mine. I

vividly recall the moment when I first met him. He inspired and motivated me to

pursue academic research by showing his doctoral dissertation very proudly. Without

his guidance and teaching, I could not start and cannot finish the doctoral program.

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Table of Contents

Abstract ...................................................................................................................... iv

Acknowledgments ...................................................................................................... vi

Table of Contents ..................................................................................................... vii

List of Tables .............................................................................................................. ix

List of Figures ............................................................................................................ xi

1 Introduction ............................................................................................................ 1

1.1 Structure and Manufacturing Process ............................................................................. 3

1.2 CNTFET Device Sizing.................................................................................................. 5

1.3 Performance .................................................................................................................... 8

1.3.1 Power Delay Product ............................................................................................... 8

1.3.2 Leakage .................................................................................................................. 12

1.3.3 PVT Variation ....................................................................................................... 16

1.4 Dissertation Outline ...................................................................................................... 23

2 A Model for Undeposited CNTs in CNTFET Operation .................................. 26

2.1 CNTFET Model ............................................................................................................ 28

2.1.1 Gate Capacitance Model ........................................................................................ 28

2.1.2 Current Model ....................................................................................................... 30

2.2 Proposed Model ............................................................................................................ 32

2.2.1 Proposed Gate Capacitance Model ........................................................................ 33

2.2.2 Proposed Drain Current Model .............................................................................. 36

2.2.3 Simulation Results ................................................................................................. 37

2.3 Delay Analysis .............................................................................................................. 41

2.4 Probabilistic Analysis ................................................................................................... 47

2.5 Conclusion .................................................................................................................... 51

3 Delay Analysis of a CNTFET with Undeposited CNTs by Gate Width Adjustment ................................................................................................................ 52

3.1 Gate Width Adjustment ................................................................................................ 53

3.2 Adjustment for Reduced Delay Deviation .................................................................... 60

viii

3.3 Conclusion .................................................................................................................... 66

4 A Linear Programming Method for HSPICE Simulation of CNTFETs with Uneven Defective CNTs ........................................................................................... 68

4.1 A Model for Uneven Defective CNTFET .................................................................... 70

4.2. Linear Programming .................................................................................................... 74

4.3 The Adjustment of Variables (STEP3) ......................................................................... 79

4.3.1 Chirality ................................................................................................................. 79

4.3.2 Doping Level ......................................................................................................... 86

4.3.3 Pitch ....................................................................................................................... 89

4.4. HSPICE Simulation ..................................................................................................... 92

4.5 Simulation Time and Memory ...................................................................................... 95

4.6. Conclusion ................................................................................................................. 101

5 Design and Comparative Analysis of a CNTFET-based Ternary SRAM ....... 103

5.1 Ternary Inverter .......................................................................................................... 107

5.2 Ternary CNTFET SRAM ........................................................................................... 108

5.2.1 First Proposed Ternary CNTFET SRAM ............................................................ 109

5.2.2 Second Proposed Ternary CNTFET SRAM ........................................................ 127

5.3 Process Variation ........................................................................................................ 132

5.3.1 Density ................................................................................................................. 133

5.3.2 Lithography ......................................................................................................... 135

5.3.3 The number of CNTs ........................................................................................... 139

5.4 Summary ..................................................................................................................... 146

5.4 Conclusion .................................................................................................................. 147

5.5 Appendix .................................................................................................................... 150

6 Summary and Future Work .............................................................................. 153

6.1 Summary of Contributions ......................................................................................... 153

6.2 Future Works .............................................................................................................. 156

ix

List of Tables

1.1: FO4 delay, power, and power delay product for 32nm MOSFET and 32nm

CNTFET benchmark circuits ............................................................................. 11

2.1: Two intervals of CNTs for largest delay (VGS=0.9V, (19,0), N=9) .................... 46

2.2: Two intervals of CNTs for least delay (VGS=0.9V, (19,0), N=9) ........................ 46

2.3: Configuration probability for largest and least delays (VGS=0.9V, (19,0), N=9) 50

3.1: Summary of results of proposed methods by adjusting WG ................................ 65

4.1: Linear programming ............................................................................................ 78

4.2: Variables (Isemi_middle, Isemi_edge, Cgc_middle, and Cgc_edge) and semiconducting sub-

bands (E1,0, E2,0, and E3,0) vs. chirality ((n1’,n2’)) .............................................. 81

4.3: The position of CNT defects (PCD), the required number of CNTs (N’), gate

width (Wg’), errors between two models (Ei, and Ec) when the number of CNT

defects (NCD) is 1, chirality ((n1’, n2’)) is (19,0), pitch (s’) is 3.812nm, and gate

width (Wg) is 32nm .............................................................................................. 81

4.4: Parameters ((n1’,n2’), s’, Ef’, N’) for linear programming, errors (Ei and Ec), and

ratio of simulation iteration (RSI) depending on chirality ((n1, n2)) when the

number of CNT defects (NCD) is changed from 3 to 9 ....................................... 89

4.5: Diameter(d’), twice diameter (2×d’), and possible pitch (s’) depending on

chirality ((n1’,n2’)) .............................................................................................. 91

4.6: Delay, energy, and ratios in five stage fan-out of four inverter chain depending

on chirality ((n1, n2)) and the number of CNT Defects (NCD) ............................ 96

4.7: Parameters ((n1’, n2’), s’, Ef’, N’, Wg’, Ei, and Ec ) for linear programming

depending on chirality ((n1, n2)) when the number of CNT defects (NCD) is 1 or

3 (8% or 32%) .................................................................................................... 97

4.8: The required time and memory for MATLAB simulation when chirality ((n1,n2))

is (19,0) and the number of CNT defects (NCD) is 1 or 3 (8% or 32%) ............. 98

x

4.9: The required step, time, and memory for MATLAB simulation depending on

various chirality ((n1,n2)) when the number of CNT defects (NCD) is 1 or 3 (8%

or 32%) ............................................................................................................... 99

4.10: Time and memory for HSPICE simulation depending on chirality ((n1, n2))

when the number of CNT defects (NCD) is 1 or 3 (8% or 32%) ....................... 100

5.1: Truth table of STI, PTI, and NTI ...................................................................... 107

5.2: Transistor ratio and gate width .......................................................................... 116

5.3: Transistor ratio and performance ...................................................................... 124

5.4: Read and write delay of Lin’s TC SRAM cell .................................................. 124

5.5: The performance of the second proposed TC SRAM ....................................... 129

5.6: Density and performance .................................................................................. 134

5.7: The rank of performance ................................................................................... 148

5.8: The rank of standard deviation to the process variation in lithography ............ 149

5.9: The rank of standard deviation to the process variation in the number of CNTs

.......................................................................................................................... 149

5.10: The process variation in lithography ............................................................... 150

5.11: The process variation in the number of CNTs ................................................ 151

5.12: SNM vs. process variation .............................................................................. 152

xi

List of Figures

1.1: CNTFET structure ................................................................................................. 3

1.2: CNTFET manufacturing process .......................................................................... 4

1.3: Voltage transfer characteristic for 32nm MOSFET and 32nm CNTFET at 0.9V

power supply voltage. .......................................................................................... 6

1.4: Voltage transfer characteristic for 32nm CNTFET and 32nm MOSFET as

function of power supply voltage. ....................................................................... 7

1.5: Power delay product for 32nm MOSFET and 32nm CNTFET at 0.9V power

supply voltage ...................................................................................................... 9

1.6: Power delay product for 32nm MOSFET and 32nm CNTFET at 0.9V power

supply voltage .................................................................................................... 10

1.7: Average leakage power for 32nm MOSFET and 32nm CNTFET at 0.9V power

supply voltage. ................................................................................................... 13

1.8: Average leakage power for 32nm MOSFET and 32nm CNTFET vs. supply

voltage. ............................................................................................................... 14

1.9: Average leakage power for 32nm MOSFET and 32nm CNTFET vs. temperature.

............................................................................................................................ 15

1.10: Drain current vs. gate voltage curve with ±10% change of gate length and

width for 32nm MOSFET and 32nm CNTFET. ................................................ 17

1.11: Power delay product for 32nm CNTFET logic gates vs. the diameter (chirality)

of carbon nanotube ............................................................................................. 17

1.12: Maximum leakage power for 32nm CNTFET logic gates vs. the diameter

(chirality) of CNT. .............................................................................................. 18

1.13: Power delay product for 32nm MOSFET and 32nm CNTFET logic gates vs.

supply voltage. ................................................................................................... 19

1.14: Maximum leakage power for 32nm MOSFET logic gates and 32nm CNTFET

logic gates vs. supply voltage. ............................................................................ 20

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1.15: Power delay product for 32nm MOSFET and 32nm CNTFET logic gates vs.

temperature. ........................................................................................................ 21

1.16: Maximum leakage power for 32nm MOSFET and 32nm CNTFET logic gates

vs. temperature. .................................................................................................. 22

2.1: Gate to channel capacitance model for a CNTFET ............................................ 32

2.2: Planar view of CNTFET with undeposited CNTs showing intervals ................. 34

2.3: Proposed gate to channel capacitance model for a CNTFET with defects ......... 37

2.4: Cgc_e ,Cgc_m_symmetric, and Cgc_m_asymmetry vs. interval values for CNTFET with

defects ................................................................................................................. 38

2.5: Drain current vs. the number of CNT Defects (NCD) (VGS=0.9V, (19,0), N=9,

Wg=32nm); average, largest and least values are plotted for drain current. ....... 39

2.6: Gate capacitance vs. the number of CNT defects (NCD) (VGS=0.9V, (19,0), N=9,

Wg=32nm); average, largest and least capacitance values are plotted for gate

capacitance. ........................................................................................................ 40

2.7: Delay vs. the number of CNT defects (NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm);

average, largest and least values are plotted for delay. ...................................... 40

2.8: Configuration (and its definition) of a CNTFET (planar view) with undeposited

CNTs and intervals. ............................................................................................ 42

2.9: Relative standard deviation and the number of combinations for CNT defects

(NCCD) vs. the number of CNT defects (NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm)

for drain current, gate capacitance and delay ..................................................... 45

2.10: Configuration (PCD) for largest delay ((a)) and configurations (PCD ) for least

delay ((b), (c), and (d)) (VGS=0.9V, (19,0), N=9, NCD=6, Wg=32nm); planar

views ................................................................................................................... 47

3.1: Reducing Wg (WRg = 1 CNT and WRg = 2 CNTs) ................................................ 56

3.2: Proposed method for Wg adjustment ................................................................... 57

3.3: Delay vs. NCD when adjusting Wg (VGS=0.9V, (19,0), N=9, Wg=32nm) ............. 59

3.4: Delay and deviation vs. the number of CNT defects (NCD) when adjusting Wg at

different chiralities (VGS=0.9V, (19,0), N=9, Wg=32nm) ................................... 59

xiii

3.5: Delay vs. the number of CNT defects (NCD) when adjusting Wg for reducing

deviation (VGS=0.9V, (19,0), N=9, Wg=32nm) ................................................... 61

3.6: Delay vs. the number of CNT defects (NCD) when adjusting Wg for reducing

deviation at different chirality values (VGS=0.9V, (19,0), N=9, Wg=32nm ........ 61

3.7: Reduction in average delay (%) and average deviation between average delay

and least delay (%) vs. chirality (VGS=0.9V, N=9, Wg=32nm) ........................... 62

3.8: Reduction in average delay vs. chirality at standard deviation values of 0.01 and

0.1(VGS=0.9V, N=9, Wg=32nm) ......................................................................... 63

3.9: Reduction in average deviation vs. chirality at standard deviation values of 0.01

and 0.1 (VGS=0.9V, N=9, Wg=32nm) .................................................................. 64

4.1: A model for uneven defective CNTFET ............................................................. 71

4.2: The positions of CNT defects (PCD) when CNTs are evenly positioned. ........... 72

4.3: The positions of CNT defects (PCD) when CNTs are unevenly positioned. ....... 73

4.4: A model for uneven defective CNTFET (a) and a model for even defective

CNTFET (b) ....................................................................................................... 75

4.5: Flow chart ............................................................................................................ 78

4.6: Average, largest, and least values for the required number of CNTs (N’) vs.

chirality ((n1’, n2’)) and the number of CNT defects (NCD) ............................... 82

4.7: Average values for the required number of CNTs (N’) vs. chirality ((n1’, n2’))

and the number of CNT defects (NCD) ............................................................... 82

4.8: Average, largest, and least values for the required gate width (Wg’) vs. chirality

((n1’, n2’)) and the number of CNT defects (NCD) .............................................. 83

4.9: Average, largest, and least values for the error between IT and IT’ (EI) vs.


4.10: Average, largest, and least values for the error between CT and CT’ (EC) vs.


4.11: Average, largest, and least values for the error between IT and IT’ (EI) and

between CT and CT’ (EC) vs. chiralityi n1’ .......................................................... 84

xiv

4.12: Variables for linear programming (Isemi_middle, Isemi_edge, Cgc_middle, and Cgc_edge) vs.

chirality((n1’, n2’)) and doping level (Ef’) .......................................................... 88

4.13: Average, largest, and least values for the error between IT and IT’ (EI) and

between CT and CT’ (EC) vs. doping level (Ef’) when chirality ((n1’, n2’)) is

(16,0) .................................................................................................................. 89

4.14.: Variables for linear programming (Isemi_middle, Isemi_edge, Cgc_middle, and Cgc_edge)

vs. chirality ((n1’, n2’)) and pitch (s’) ................................................................. 91

4.15:. Average, largest, and least values for the error between IT and IT’ (EI) and

between CT and CT’ (EC) vs. pitch (s’) when (n1’, n2’) = (16,0) and (n1’, n2’) =

(10,0) .................................................................................................................. 93

4.16: Five stage FO4 inverter chain .......................................................................... 94

5.1: STI inverter ....................................................................................................... 108

5.2: 6T SRAM cell ................................................................................................... 109

5.3: Grouping CNTFETs for sizing in TC SRAM cell ............................................ 110

5.4: Lin’s TC SRAM cell ......................................................................................... 111

5.5: The first proposed TC SRAM cell .................................................................... 112

5.6: Sense amplifiers for TC SRAM ........................................................................ 112

5.7: MN4/MN2 ratio versus voltage rise at nq for SRAM cell ................................ 114

5.8: MP5/MN1 ratio versus voltage rise at q for SRAM cell ................................... 114

5.9: Voltage transfer characteristic of BM SRAM cell and BC SRAM cell for SNM

.......................................................................................................................... 117

5.10: Voltage transfer characteristic of STI inverter and modified STI inverter ..... 117

5.11 Voltage transfer characteristic of TC SRAM cell and modified TC SRAM cell

.......................................................................................................................... 118

5.12: Average delay and power delay product when chirality vectors in MN33,

MN43, MP53, and MP63 are changed ............................................................. 120

5.13: Write operation of the first proposed TC SRAM cell ..................................... 121

5.14: Read operation of the first proposed TC SRAM cell ...................................... 122

xv

5.15: Largest, average, and least write delay and power delay product when chiralitiy

in write circuits (MN1 and MN2) is changed in the first proposed TC SRAM

.......................................................................................................................... 126

5.16: Largest, average, and least read delay when chirality in read circuit (MN9,

MN10, MN11, and MN12) is changed in the first proposed TC SRAM ......... 126

5.17: The second proposed TC SRAM .................................................................... 127

5.18: Write operation of the second proposed TC SRAM ....................................... 128

5.19: Largest, average, and least write delay and power delay product when chiralitiy

in write circuits (MN1, MN2, MN7 and MN8) is changed in the second

proposed TC SRAM ......................................................................................... 130

5.20: Largest, average, and least read delay when chirality in read circuit (MN9,

MN10, MN11, and MN12) is changed in the second proposed TC SRAM .... 131

5.21: Delay of 0 -> 1 (or 2 -> 1) when chiralitiy in write circuits (MN1, MN2, MN7

and MN8) is changed in the second proposed TC SRAM ............................... 131

5.22: Standard deviation of average write delay with Gaussian distribution (±5%

distribution at the ±3 sigma level) in 32nm gate width and length. ................. 135

5.23: Standard deviation of average write power with Gaussian distribution (±5%


5.24: Standard deviation of average write power delay product with Gaussian

distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and

length. ............................................................................................................... 136

5.25: Standard deviation of average read delay with Gaussian distribution (±5%


5.26: Standard deviation of average read power with Gaussian distribution (±5%


5.27: Standard deviation of average read power delay product with Gaussian

distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and

length. ............................................................................................................... 138

xvi

5.28: Standard deviation of average SNM with Gaussian distribution (±5%


5.29: Standard deviation of average write delay with random limit distribution (±1

absolute distribution) in the number of CNTs. ................................................. 142

5.30: Standard deviation of average write power with random limit distribution (±1


5.31: Standard deviation of average write power delay product with random limit

distribution (±1 absolute distribution) in the number of CNTs. ....................... 143

5.32: Standard deviation of average read delay with random limit distribution (±1


5.33: Standard deviation of average read power with random limit distribution (±1


5.34: Standard deviation of average read power delay product with random limit

distribution (±1 absolute distribution) in the number of CNTs. ....................... 145

5.35: Standard deviation of average SNM with random limit distribution (±1


1

Chapter 1 Introduction

As per Moore’s law, the number of transistors of an integrated circuit is

increasing exponentially by almost doubling every two years. Technology scaling

has been pursued aggressively to meet the density and sustain the IC predicted by

Moore’s law. Since 2006, the gate length of a MOSFET device has entered the deep

submicron/nano region at the 65 nm feature size. Today, 45 nm technology is reality,

and 32 nm has been predicted as feature size in the near future. As the physical gate

length is reduced to below 65 nm, many device-level effects (such as large

parametric variations and exponential increase in leakage current) have substantially

affected the I-V characteristics of traditional MOSFETs, thus resulting in major

concerns for scaling down the feature size of these devices. A possible approach to

2

meet the challenges of nano scale CMOS consists of utilizing new circuit techniques

together with alternative technologies to replace conventional silicon and the current

MOSFET-based technology. Recently, there have been tremendous advances in

carbon nanotube (CNT) technology for nano-electronics applications [1][2][3].

Carbon NanoTube Field Effect Transistor (CNTFET) has been advocated as one

of the possible alternatives to replace the conventional MOSFET due to its excellent

performance characteristics (13 times CV/I improvement over a bulk n-type

MOSFET at a 32 nm feature size). Moreover, its operational principles and device

structure are similar to those of a MOSFET device, thus showing excellent

compatibility with CMOS manufacturing processes. In CNTFETs, ballistic or near-

ballistic transport phenomena have been observed under low voltage, and the

existing design infrastructure and fabrication process of CMOS-based MOSFETs can

be also used for CNTFETs [1][2][4]. The I-V characteristics and gate capacitance of

a CNTFET are different from those of the MOSFET because in addition to the

dependency on well known parameters (node voltages, threshold voltage, and gate

width) for a MOSFET, the three device characteristics (pitch, number, and position

of CNTs) must also be established. Due to the so-called screening effect [1][2], the

current of a CNTFET changes depending on the spacing (pitch) and the position of

the CNTs; so, the current of a CNTFET cannot be increased linearly by just

increasing the number of CNTs. When considering the capacitance, the potential

profile in the gate region is affected by a screening/imaging effect from the parallel

conducting channels (i.e. the CNTs) [5].

3

1.1 Structure and Manufacturing Process

Figure 1.1: CNTFET structure

CNTs are sheets of graphene rolled into tubes. The single-walled CNT can be

either metallic or semiconducting depending on the chirality (i.e., the direction in

which the graphene sheet is rolled). The diameter of CNT is also determined by the

chirality. Semiconducting nanotubes have attracted the widespread attention of

device/circuit designers as an alternative channel implementation for high-

performance transistors. In this paper, we focus on only single-walled

semiconducting CNTs. A typical structure of a MOSFET-like CNTFET device is

illustrated in Figure 1. For its fabrication, CNTs are grown or transferred (deposited)

to a substrate using a fixed spacing (pitch) prior to defining CNTFET-based gates

and contacts. The CNT channel region under the gate is undoped while the other

regions are heavily p+ or n+ doped [1][2].

4

The common steps for manufacturing a CNTFET are shown in Figure 1.2

[8][9][10]. Figure 1.2 (a) shows that CNTs are deposited to a substrate. Then, the

region of logic cells is defined using lithography and the CNTs outside this region

are etched away (Figure 1.2 (b)). One of the likely defects that occur during the

deposition of the CNTs is that only some of the required CNTs are deposited. In this

paper, it is assumed that in the presence of undeposited CNTs (as identified by empty

spacing), the remaining (deposited) CNTs are semiconducting and aligned. Figure

1.2 (c) shows the gate and contact regions as defined by lithography in the presence

of undeposited CNTs. The last manufacturing step (Figure 1.2 (d)) is then

implemented and the CNT regions corresponding to the PFET (NFET) transistors are

doped accordingly.

Figure 1.2: CNTFET manufacturing process

5

To evaluate the performance of a CNTFET, various simulation models have been

proposed [12][13][14]. The CNTFET HSPICE model of [12] is widely used in

circuit design. For a CNTFET in addition to the dependency on node voltages (the

gate to source voltage VGS and the drain to source voltage VDS), threshold voltage

(Vth), and gate width/length such as in a MOSFET, the three features of pitch,

number, and position of CNTs determine the gate capacitance and current, as

presented in more detail next.

1.2 CNTFET Device Sizing

The inverter is the fundamental logic gate for digital circuit design. Many of the

basic principles employed in the design and analysis of an inverter can be also

applied to complex logic gates/circuits such as NOR, NAND, XOR, and FA. To

compare the performance of the MOSFET and CNTFET, the P-transistor/N-

transistor ratio of the MOSFET and CNTFET inverters should be established. In

general for Si CMOS, a PMOS/NMOS ratio of 2 or 3 is used because the NMOS

mobility is about 2 or 3 times higher than for the PMOS transistor. A 3:1

(PMOS:NMOS) ratio is used in this simulation because at this value, the voltage

transfer characteristic (VTC) of the MOSFET inverter shows a more symmetrical

shape for the 32nm technology (as shown in Fig. 1.3). However for CNTFETs, a

PCNTFET /NCNTFET ratio of 1 is used because the NCNTFET and PCNTFET

have the same current driving capabilities with same transistor geometry [1][2]. In

6

CMOS design, the width of the MOSFET is adjusted to change the PMOS/NMOS

ratio. However in a CNTFET, the number of tubes is the design parameter (such as

the W/L ratio in conventional design) for changing the current and resistance.

Therefore, in this paper, when the width of the CNTFET is increased, the number of

tubes is increased.

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90

Vout(V)

Vin(V)

MOSFET

CNFET

Figure 1.3: Voltage transfer characteristic for 32nm MOSFET and 32nm CNTFET at 0.9V power supply voltage.

The Voltage Transfer Characteristic (VTC) curves of the 32nm MOSFET and

32nm CNTFET are shown in Fig. 1.3, for minimum size MOSFET and CNTFET

inverters’ functionality. The curve is symmetric and the logic threshold voltage

(Vi

cur

CN

tha

(NM

vol

Figfun

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NTFET can

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8

1.3 Performance

1.3.1 Power Delay Product

Due to the increased demand for high-speed computation and complex

functionality in high density mobile circuits, reductions in delay and power

consumption are very challenging. The propagation delay is mostly determined by

the speed at which the energy can be stored on the gate capacitors of the transistors

of an IC. A faster energy transfer requires a higher power consumption, thus

operating at a faster speed. For a technology and gate topology, the product of the

power consumption and the propagation delay is generally constant [25]. The

performance of the MOSFET and the CNTFET can be compared using the Power

Delay Product (PDP) as metric.

Figure.1.5 shows the Power Delay Product (PDP) of the 32nm MOSFET and

CNTFET based logic gates; the PDP of the 32nm MOSFET is about 100 times

higher than for the 32nm CNTFET. The difference becomes more pronounced (about

1000 time) for the FA. In general, if the fan-out is increased, the delay of the driving

gate and the power consumption are also increased to drive the increased capacitive

load, thus resulting in an increase of the PDP as shown in Fig.1.6. Even though the

PDP of a CNTFET based gate is also increased as the fan-out increases, the load

dependent slope is almost the same as for the corresponding MOSFET gate.

9

Therefore, the overall PDPs of the CNTFET gates are much lower than for the

MOSFET gates.

Inverter NAND2 NAND3 NOR2 NOR30.00E+000

1.00E-018

2.00E-018

3.00E-018

4.00E-018

5.00E-018

5.00E-017

1.00E-016

1.50E-016

2.00E-016

2.50E-016

PD

P(J)

MOSFET CNFET

Full Adder0.00E+0005.00E-0181.00E-0171.50E-0172.00E-0172.50E-0173.00E-0173.50E-017

4.00E-014

5.00E-014

PDP(

J)

Figure 1.5: Power delay product for 32nm MOSFET and 32nm CNTFET at 0.9V power supply voltage

10

1 2 3 4

1E-16

1E-15

1E-14

CMOS FA CNFET FA

PDP

(J)

Logr

ithm

ic S

cale

FanOut

1 2 3 41E-19

1E-18

1E-17

1E-16

1E-15

PDP

(J)

Logr

ithm

ic S

cale

CNFET Inverter CNFET NAND2 CNFET NAND3 CNFET NOR2 CNFET NOR3

MOSFET Inverter MOSFET NAND2 MOSFET NAND3 MOSFET NOR2 MOSFET NOR3

Figure 1.6: Power delay product for 32nm MOSFET and 32nm CNTFET at 0.9V power supply voltage

11

Few combinational circuits have also been evaluated. Table 1.1 shows the

simulation results of circuits designed with 32nm CNTFET and 32nm CMOS

technologies. As shown in Table 2, the average delay and power consumption of the

32nm MOSFET circuits is about 10 times and 100 times higher than for the 32nm

CNTFET circuits respectively; these results confirm the findings found previously

for the CNTFET and MOSFET logic gates. Moreover, it shows that indeed

CNTFET-based designs offer significant improvements over MOSFET-based

designs.

Table 1.1: FO4 delay, power, and power delay product for 32nm MOSFET and 32nm CNTFET benchmark circuits

Delay(s) Power(w) PDP(joule)

M O S F E T

Inverter Chain 2.886e-11 9.601e-07 2.771e-17 2 : 4 Decoder 3.013e-11 7.811e-06 2.354e-16 4 : 16 Decoder 5.504e-11 1.028e-05 5.655e-16

C17 3.811e-11 6.969e-06 2.656e-16 1-bit Full Adder 5.187e-11 9.459e-06 4.906e-16

3-bit Ripple Carry Adder 8.526e-11 2.530e-05 2.157e-15 74182 6.401e-11 9.219e-06 5.901e-16

C N T F E T

Inverter Chain 4.337e-12 8.164e-08 3.541e-19 2 : 4 Decoder 4.966e-12 7.298e-07 3.624e-18 4 : 16 Decoder 9.648e-12 1.215e-06 1.173e-17

C17 6.847e-12 6.712e-07 4.596e-18 1-bit Full Adder 8.097e-12 9.087e-07 7.357e-18

3-bit Ripple Carry Adder 1.213e-11 1.299e-06 1.577e-17 74182 7.668e-12 6.198e-07 4.753e-18

12

1.3.2 Leakage

Power consumption can be classified into three types, i.e. short circuit current,

static power consumption and dynamic power consumption. The short circuit current

can be reduced using appropriate circuit techniques; however, as process dimensions

shrink further into the nanometer ranges, traditional methods for dynamic power

reduction are becoming less effective due to the increased impact of static power. In

nanometer MOSFET circuits, the main components of static power are sub-threshold,

gate tunneling, and reverse-biased junction band to band tunneling leakage current

[26][27][28][29][30]. For a CNTFET, the main leakage component is the band to

band tunneling leakage because the leakage current is controlled by the full band gap

of the CNTs and band to band tunneling. The other leakage currents are relatively

small and can be reduced by new techniques such as utilizing high-k dielectric

materials [31][32][33]. Figure 1.7 shows the average leakage power for 32nm

MOSFET and CNTFET gates and FA. For logic gates, the average leakage power of

the MOSFET is 150 times larger than the CNTFET based gates; especially for the

FA, the leakage power of the MOSFET becomes 250 times bigger than for the

CNTFET.

Another advantage of a CNTFET based gate is the low power supply operation.

When the supply voltage is reduced to 0.5V, the MOSFET based FA does not

operate any more, while the CNTFET based FA still operates till the supply voltage

is reduced to 0.3V. Figure 1.8 shows the average leakage power of the MOSFET and

13

CNTFET gates when the supply voltage is reduced until the FA fails. It shows that

even though the average leakage power of the MOSFET gates is reduced as the

supply voltage decreases, the overall leakage power is greater than for the CNTFET

FA. This leakage power advantage of the CNTFET technology is also retained at

high temperature operation as shown in Fig. 1.9. As temperature is increased, the

average leakage power of the CNTFET FA increases too. However, the total leakage

power is significantly smaller that the leakage power of the MOSFET gates.

Inverter NAND2 NAND3 NOR2 NOR30.00E+000

5.00E-010

1.00E-009

1.50E-009

2.00E-009

2.50E-009

1.00E-007

1.20E-007

1.40E-007

1.60E-007

1.80E-007

Aver

age

Leak

age

Pow

er(W

)Lo

grith

mic

Sca

le

Full Adder0.0

5.0x10-9

1.0x10-8

1.5x10-8

2.0x10-8

2.5x10-8

2.0x10-6

2.5x10-6

MOSFET CNFET

Aver

age

Leak

age

Pow

er(W

)Lo

grith

mic

Sca

le

Figure 1.7: Average leakage power for 32nm MOSFET and 32nm CNTFET at 0.9V power supply voltage.

14

0.9 0.8 0.7 0.6 0.5 0.4 0.310-10

10-9

10-8

10-7

10-6

0.9 0.8 0.7 0.6 0.5 0.4 0.3

10-8

10-7

10-6 MOSFET FA CNFET FA

Ave

rage

Lea

kage

Pow

er(W

)Lo

grith

mic

Sca

le

Vdd(V)

Aver

age

Leak

age

Pow

er(W

)Lo

grith

mic

Sca

le



Figure 1.8: Average leakage power for 32nm MOSFET and 32nm CNTFET vs. supply voltage.

15

0 20 40 60 80 100

10-8

10-7

10-6 MOSFET FA CNFET FA

Ave

rage

Lea

kage

Pow

er(W

)Lo

grith

mic

Sca

le

Temperature( OC)

0 20 40 60 80 10010-10

10-9

10-8

10-7

10-6



Aver

age

Leak

age

Pow

er(W

)Lo

grith

mic

Sca

le

Figure 1.9: Average leakage power for 32nm MOSFET and 32nm CNTFET vs. temperature.

16

1.3.3 PVT Variation

With technology scaling, the effects of systematic and random variations in

process, supply voltage, and temperature (PVT) have led to inconsistent delay and

leakage in low power circuits, thus becoming a major obstacle for device scaling.

Therefore, the possible performance degradation due to PVT variations has become a

major criterion in assessing the performance of a new technology.

When investigating physical process variations, channel length and width are

usually considered for a MOSFET transistor in MOSFET. However, MOSFET and

CNTFET have different characteristics, as evidenced in Figure 1.10. The current

change in a MOSFET is about ±30% (±13%) for a ±10% change in length (width) at

a gate voltage of 0.9V while the current change in a CNTFET is below ±0.5%.

However when the diameter of the CNTFET is changed by ±10%, the current change

in a CNTFET is about ±17%. Therefore for a CNTFET, the diameter variation is

more important because a CNTFET is more sensitive to diameter variation than

length and width variations. Based on this observation, the PDP and leakage of a

CNTFET are computed and plotted in Figure 1.11 and Figure 1.12, respectively.

When the diameter of a CNTFET is changed, this causes a change in PDP. Figure

1.12 shows that the maximum leakage power increases when the diameter is

increased. Moreover, the threshold voltage and diameter of a CNTFET are

determined based on the chirality of the CNTs used in this device.

17

0.0 0.2 0.4 0.6 0.8 1.00.0

5.0x10-6

1.0x10-5

1.5x10-5

2.0x10-5

2.5x10-5

3.0x10-5

3.5x10-5

4.0x10-5

4.5x10-5

5.0x10-5

M : MOSFETC : CNFET

M

C

M : MOSFETC : CNFET

Gate Voltage (VGS)

M

C 0.0 0.2 0.4 0.6 0.8 1.0

0.0

5.0x10-6

1.0x10-5

1.5x10-5

2.0x10-5

2.5x10-5

3.0x10-5

3.5x10-5

4.0x10-5

Dra

in C

urre

nt (I

D)

Gate Voltage (VGS)

Figure 1.10: Drain current vs. gate voltage curve with ±10% change of gate length and width for 32nm MOSFET and 32nm CNTFET.

17_4 17_6 17_7 17_9 17_10 14_7 15_7 17_7 18_7 20_7 --

1.0x10-19

1.5x10-19

2.0x10-19

2.5x10-19

3.0x10-19

3.5x10-19

4.0x10-19

4.5x10-19

5.0x10-19

5.5x10-19

6.0x10-19

6.5x10-19

CNTFET Inverter CNTFET NAND2 CNTFET NAND3 CNTFET NOR2 CNTFET NOR3

PD

P (J

)

Chirality

Figure 1.11: Power delay product for 32nm CNTFET logic gates vs. the diameter (chirality) of carbon nanotube

18

17_4 17_6 17_7 17_9 17_100.0

1.0x10-10

2.0x10-10

3.0x10-10

4.0x10-10

5.0x10-10

6.0x10-10

7.0x10-10

8.0x10-10

9.0x10-10

1.0x10-9

Chirality

14_7 15_7 17_7 18_7 20_70.0

1.0x10-10

2.0x10-10

3.0x10-10

4.0x10-10

5.0x10-10

6.0x10-10

7.0x10-10

8.0x10-10

9.0x10-10

1.0x10-9

1.1x10-9

1.2x10-9

1.3x10-9

Max

imum

Lea

kage

Pow

er (W

)M

axim

um L

eaka

ge P

ower

(W) CNTFET Inverter

CNTFET NAND2 CNTFET NAND3 CNTFET NOR2 CNTFET NOR3

Figure 1.12: Maximum leakage power for 32nm CNTFET logic gates vs. the diameter (chirality) of CNT.

Figures 1.13 and 1.14 show the Power Delay Product (PDP) and maximum

leakage power for 32nm MOSFET and 32nm CNTFET logic gates, respectively

when the supply voltage is decreased until the gate stops functioning correctly. Even

though PDP is changed depending on the supply voltage, the change of PDP in a

CNTFET is less than a MOSFET because a CNTFET has a lower gate capacitance

and a higher mobility than a MOSFET [1][2]. The maximum leakage power of the

CNTFET (MOSFET) gates decreases linearly (exponentially) as shown on Figure

19

1.14, however the overall leakage power of the MOSFET gates is greater than for the

CNTFET gates.

Figures 1.15 shows that the PDP of the MOSFET gates increases with temperature;

however, the PDP of the CNTFET logic gates is constant due to the high thermal

stability of CNTFETs [34]. Moreover, the maximum leakage power of the MOSFET

gates increases linearly with temperature, while for the CNTFET-based gates this

increase is exponential (as shown in Figures 1.16).

0.9 0.8 0.7 0.6 0.5

1E-19

1E-18

1E-17

1E-16



PD

P (J

) (Lo

g Sc

ale)

Supply Voltage (V)

Figure 1.13: Power delay product for 32nm MOSFET and 32nm CNTFET logic gates vs. supply voltage.

20

0.8 0.6 0.4 0.2 0.00.0

5.0x10-11

1.0x10-10

1.5x10-10

2.0x10-10

2.5x10-10

3.0x10-10

3.5x10-10

4.0x10-10

4.5x10-10

5.0x10-10


Supply Voltage (V)0.8 0.6 0.4 0.2 0.0

0.0

4.0x10-9

8.0x10-9

1.2x10-8

1.6x10-8

2.0x10-8

2.4x10-8

2.8x10-8

3.2x10-8

3.6x10-8 MOSFET Inverter MOSFET NAND2 MOSFET NAND3 MOSFET NOR2 MOSFET NOR3

Max

imum

Lea

kage

Pow

er (w

)

Supply Voltage (V)

Figure 1.14: Maximum leakage power for 32nm MOSFET logic gates and 32nm CNTFET logic gates vs. supply voltage.

21

0 20 40 60 80 100

10-18

10-17

10-16

10-15


PD

P (J

)

Temperature (OC)


Figure 1.15: Power delay product for 32nm MOSFET and 32nm CNTFET logic gates vs. temperature.

22

0 20 40 60 80 1000.0

1.0x10-8

2.0x10-8

3.0x10-8

4.0x10-8

5.0x10-8

6.0x10-8

7.0x10-8


Max

imum

Lea

kage

Pow

er (w

)

Temperature (OC)

0 20 40 60 80 1000.0

4.0x10-10

8.0x10-10

1.2x10-9

1.6x10-9

2.0x10-9

2.4x10-9

2.8x10-9


Temperature (OC)

Figure 1.16: Maximum leakage power for 32nm MOSFET and 32nm CNTFET logic gates vs. temperature.

23

1.4 Dissertation Outline


promising emerging technologies to extend and complement silicon MOSFET; this

is due to its excellent performance characteristics (13 times CV/I improvement over

a bulk n-type MOSFET at a 32 nm feature size) and similarity in operational

principles and device structure. Simulation results have shown that the PDP and the

leakage power of the CNTFET based gates are 100 and 75 times lower than for the

MOSFET gates, respectively. It is also demonstrated that the advantages offered by

CNTFET gates under different operational conditions such as very low power supply

voltage and high temperature.

However, one of the likely defects occurs during the deposition of the CNTs, i.e.

only some of the required CNTs are deposited. These defects change radically the

performance of the fabricated CNTFET because for example, the delay can vary

significantly due to the smaller number of CNTs present in the channel and the

uneven spacing between them. To evaluate the effect of uneven spacing between

CNTs, various simulation models have been proposed [12][13][14]. The CNTFET

HSPICE model of [12] is widely used in circuit design. However, in [12], the

screening effect is assumed to be symmetric, i.e. it is assumed that the distances at

both sides of a CNT with respect to adjacent CNTs are always the same; hence a new

analytical framework is required for modeling a CNTFET following the deposition

of not all CNTs on the substrate.

24

In Chapter 2, a new MATLAB-based model for characterizing the delay

performance of a CNTFET when undeposited CNTs occur as defects in the

deposition/growth process for fabrication. Initially, a comprehensive characterization

is pursued and new equations are found for the capacitance and drain current when

undeposited CNTs are encountered following CNTFET fabrication. An extensive

analysis and simulation-based evaluation of the undeposited CNTs are pursued on

deterministic and probabilistic basis. The simulation results show that the delay in a

CNTFET significantly increases with the number of undeposited CNTs and the

deviation in delay depends on the position of the undeposited CNTs.

To reduce the effect of undposited CNTs, in Chapter 3, a new corrective action to

the fabrication process is suggested. Based on the capabilities of today’s lithography,

two methods are proposed for reducing the delay and the deviation with adjusting the

gate width of the CNTFET. By reducing gate width considering the number and

position of undeposited CNTs, the gate capacitance of the CNTFET can be decreased.

To verify these two approaches, extensive simulation are performed deterministically

and probabilistically under various chirality, number and position of undeposited

CNTs.

With the proposed MATLAB-based model in Chapter 2 and Chapter 3, the effect

of undeposited CNTs and the performance of corrective process can be evaluated.

However, the MATAB-based model requires highly iterative simulation to evaluate

the undeposited CNTs and it cannot perform circuit level simulation. To evaluate the

25

effect of variations (the chirality, the number, and the position of CNTs) in circuit

level performance, in Chapter 4, first, the complicatedly defective CNT composition

in a CNTFET (CNTs are randomly deposited or undeposited in a CNTFET) is

modeled based on the MATLAB-based Model. Then, by using linear programming,

proper parameters (number, pitch, doping level, and chirality of CNTs) which can be

used in HSPICE and represent the complicatedly defective CNT composition will be

achieved.

In Chapter 5, using the proposed CNTFET circuit design and evaluation method,

a new methodology to design a novel ternary CNTFET SRAM cell is proposed. First,

the methodology to utilize the traditional transistor sizing methods is proposed. Then,

chirality in each CNTFET is optimized to achieve four even SNM and to reduce

power. It will be also shown that the proposed ternary CNTFET SRAM cell can be

operated without 0.45V power supply by adding two transistors.

Finally, Chapter 6 summarizes the major achievements and contributions of this

dissertation.

26

Chapter 2 A Model for Undeposited CNTs in CNTFET Operation

In previous chapter, it is discussed that the Carbon NanoTube Field Effect

Transistor (CNTFET) has been advocated as one of the possible alternatives to

replace the conventional MOSFET due to its better performance, lower leakage, and

higher robustness to PVT variation. However, in a CNTFET, The I-V characteristics

and gate capacitance of a CNTFET are different from those of the MOSFET because

in addition to the dependency on well known parameters (node voltages, threshold

voltage, and gate width) for a MOSFET, the three device characteristics (pitch,

number, and position of CNTs) must also be established [1][2]. Moreover, for

CNTFET manufacturing, CNTs are usually grown or deposited on a substrate at a

fixed pitch prior to defining the gates and the contacts. If the pitch is decreased, the

processes for correctly aligning and positioning CNTs at the desired locations

become difficult [6][7][62][63]. Moreover, following manufacturing, 10% to 70% of

27

the CNTs are usually metallic and have to be discarded; only semiconducting CNTs

must be utilized for a CNTFET [7]. For current technology, corrective processes can

be employed when manufacturing CNTFETs; for example by using electrical

burning and selective etching, defective CNTs (such as misaligned CNTs) can be

removed [8][9]. Techniques for detection and correction have been proposed [7].

One of the likely defects occurs during the deposition of the CNTs, i.e. only some of

the required CNTs are deposited. These defects change radically the performance of

the fabricated CNTFET because for example, the delay can vary significantly due to

the smaller number of CNTs present in the channel and the uneven spacing between

them. Statistical approaches have been reported in the technical literature [10][11]

using the HSPICE model of [1][2][12] to identify the impact of defects. However in

[1][2], the spacing between CNTs of a CNTFET is constant and therefore, it cannot

take into consideration the impact of undeposited CNTs. Furthermore, in [1] the

screening effect is assumed to be symmetric, i.e. it is assumed that the distances at

both sides of a deposited CNT with respect to adjacent CNTs are always the same;

hence, a new analytical framework is required for modeling a CNTFET following

the deposition of not all CNTs on the substrate.

In this paper, a MATLAB-based model for a CNTFET with undeposited CNTs as

defects is proposed. Initially, a comprehensive characterization is pursued and new

equations are found for the capacitance and drain current when undeposited CNTs

are encountered following CNTFET fabrication. It is shown that CNTFET

performance (and in particular the delay) depends on the number of defects as well

as their position in the CNTFET, i.e. the so-called configuration of the defective

CNTFET. An extensive analysis and simulation-based evaluation of the CNTFET

configurations that yield the least and largest delays are pursued on deterministic and

probabilistic basis.

28

2.1 CNTFET Model

2.1.1 Gate Capacitance Model

The equation for the gate capacitance of a CNTFET (Cgg,CNTFET) is given in (2.1);

the gate outer fringe capacitance to doped source/drain regions are ignored because

the gate outer fringe capacitance is significantly smaller than other components when

gate height is 64nm and source/drain length is 32nm which are used in this paper and

technical literature [1][2][5][15]. Moreover, the values are not changed depending on

the position and the number of CNTs. The gate capacitance is function of the gate to

channel capacitance (Cgc), the gate length (Lg), the Miller factor (fmiller), the gate to

gate capacitance (Cgtg), and the gate width (Wg). Cgc is given in (1.2) and consists of

three terms, as related to the unit capacitances of the gate to the cylinders (CNTs) at

the two ends (Cgc_e), in the middle (Cgc_m), and the number of CNTs (N). As given in

(2.2), this model is based on placing first the CNTs at the edges and then the

remaining N-2 CNTs from the middle across the gate of a CNTFET.

ggtgmillerggcCNTFETgg WCfLCC ××+×≈, (2.1)

mgcegcgc CNCNC __ )0,2max()2,min( ×−+×= (2.2)

When considering Cgc (Figure 2.1 (a)), in the channel conduction is accomplished by

identical objects (i.e. the CNTs) in parallel (in this case, 7 objects with the same

pitch), and the gate electrode (the planar object #0); note also that the possible

29

number of CNTs in a CNTFET is a function of the gate width, the diameter of CNTs,

and the placement accuracy/resolution of the employed fabrication technology. To

calculate the coupling capacitance (C01) between object #0 and the object #1, the

total effect of the other 6 objects around object #1 can be lumped and approximated

by considering only the two nearest objects, i.e. objects #2 and #3 in Figure 2.1 (b).

This assumption is valid, because objects located at a far distance from object #1

have a rather weak influence on the electric field distribution between electrode #0

and object #1. This is a commonly found assumption in the technical literature [5],

thus effectively making the gate to channel capacitance independent of the number

of cylinders in the model. Therefore, when calculating the screening/imaging effect

of a CNT (Figure 2.1 (a)), only the two neighboring CNTs are considered for an

internal (non boundary) CNT (Figure 2.1 (b)). For a boundary CNT (i.e. located at

the edge), only one neighbor must be considered (Figure 2.1 (c)).

When a voltage V1 is applied between objects #1, #2, #3, and the electrode #0, the

charges Q1, η1Q1, and η2Q1 are found on these three objects due to the different

coupling capacitance C01, C02, and C03. η1 and η2 are defined as the ratios of C02 to

C01 and C03 to C01, respectively, i.e.

(2.3)

From [5], C01 is given by

01

032

01

021 C

CCC

== ηη

30

(2.4)

Csr_1 and Csr_2 are the capacitances due to the screening effects of objects #2 and #3,

respectively; so, Csr_1 (Csr_2) changes depending on the spacing between object #1

and object #2 (#3). Cinf is the capacitance between electrode #0 and object #1 with no

screening from all other objects. When Cinf and Csr are replaced by Cinf and Csr for

calculating the gate to channel capacitance (Cgc_inf and Cgc_sr) of [5], C01 in (4)

becomes the gate to channel capacitance (Cgc) of each CNT in a CNTFET. η1 and η2

are function of the geometry and the number/position of the objects in the model.

Using [5], the following cases can be distinguished using (2.4): (A) when Cgc_e is

found, η1=1 and η2=0 because the screening objects are located only on one side

(Figure 2.1 (c)); (B) when Cgc_m is found, η1= η2= Cgc_e/Cgc_m and Cgc_sr_1=Cgc_sr_2

because objects #2 and #3 are positioned at a same pitch on both sides of object #1

(Figure 2.1 (b)). Therefore, Cgc_e and Cgc_m can be written as (2.5) and (2.6)

respectively (where Cgc_m_symmetric is the capacitance for the case in which the pitch

between the CNTs is constant; this feature will be discussed in more detail in a later

section).

2.1.2 Current Model

In [1][2], the current equations for a semiconducting CNT are given by (7) and (8)

(the fitting parameters for the sub-threshold slope and the measured short channel

2_2

1_1

inf

01 1111

srsr CCC

C⋅+⋅+

=ηη

31

effects are not relevant in this analysis and are ignored). M and L are the number of

sub-bands and the number of sub-states, respectively. In this paper, it is assumed that

M=2 and L=9 because only the first 2 or 3 sub-bands and the first 10-15 sub-states

have a significant impact on the current [1][2]. TLR and TRL are the transmission

probabilities of the carriers flowing from the drain to the source (+k branch) and

from the source to the drain (-k branch) respectively. Jm,l is the current of the sub-

state (m,l). ΔΦB is the channel surface potential that can be achieved by solving (8).

Cgc_p is found based on the position of the CNTs and is given by (9). Csub is the

capacitance between the channel and substrate. Em,l is the carrier energy at the (m,l)

sub-state.

srgcgc

srgcgcegc CC

CCC

_inf_

_inf__ +

×= (2.5)

symmetricmgcgcegcmgc CCCC __inf___ 2 =−= (2.6)

]|),(|),0([2

),(

1 0,,,

,,

kB

M

m

L

lDSchlmRLkBlmLR

GSchDSchsemi

VJTJT

VVI

−= =

+ ΦΔ−ΔΦ= ∑∑ (2.7)

( )

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎥⎦⎤

⎢⎣⎡

++

+−⋅×

+⋅=ΔΦ

∑∑= =

+ΔΦ−ΔΦ−

M

m

L

lkTeVEkTE

gGSchpgc

subpgcB

DSchBlmBlm eeLeVC

CCe

1 0/)(/)(,_

_

,,, 11

114

( (2.8)

32

⎩⎨⎧

=edgetheatpositionedisCNTwhenC

middletheinpositionedisCNTwhenCC

egc

mgcpgc

_

__ (2.9)

Electrode #0

CNTs in the middle

Electrode #0

#2 #1 #3

Electrode #0

#1 #2

a CNT at Edge a CNT at Edge

Figure 2.1: Gate to channel capacitance model for a CNTFET

2.2 Proposed Model

During fabrication, CNTs are usually grown or transferred (deposited) to a

substrate at a fixed pitch prior to defining the CNTFET gates and the contacts

(Figure 1.1) [6][7]. Among the grown (deposited) CNTs, only semiconducting CNTs

are considered; metallic CNTs increase leakage and reduce the noise margin [11].

Other types of defect are mispositioned and misaligned CNTs and cause shorts and

33

incorrect logic functionality [7]. Corrective and design techniques to remove CNT

defects have been proposed [7][8][9]. It is likely that some CNTs will not be grown

on the substrate, hence this type of defects (referred to as undeposited CNT) will

result in a CNTFET in which the distance between deposited CNTs is not constant

(Figure 2.2). In these cases, the model of [1][2] cannot be used due to the assumed

even spacing between CNTs. Figure 2.2 shows that when three CNTs are

undeposited, three different intervals (inta, intb, and intc) exist, i.e. uneven spacing.

Hereafter, the correct spacing between CNTs is defined by the pitch (s); in the

presence of undeposited CNTs (as defects), the spacing between each pair of

deposited CNTs is referred to as an interval (int) (Figure 2.2). Each int in a

CNTFET is a multiple of the pitch (i.e. s); for example, in Figure 2.2, inta=2s,

intb=3s, and intc=1s. Next, new models for the gate capacitance and drain current are

proposed under the CNTFET scenario of undeposited CNTs.

2.2.1 Proposed Gate Capacitance Model

Let NCD denote number of CNT defects (i.e. undeposited CNTs); hence, the

number of deposited CNTs is given by N-NCD and intervals are present between

some pairs of tubes. Initially, (2.2) is changed to (2.10) by taking into account the

reduced number of deposited CNTs for calculating Cgc.

mgcCDegcCDgc CNNCNNC __ )0,2max()2,min( ×−−+×−= (2.10)

34

When Cgc_m is calculated from (2.4), in the defect free scenario (2.6) is obtained

as CNTs are separated by the same spacing (i.e. even or constant pitch), as shown in

Figure 2.1. However, when defects due to undeposited CNTs occur (Figure 2.2), the

intervals between CNTs are uneven as dependent on the number and position of the

defects. Therefore, (2.6) cannot be used and a new equation for Cgc_m must be found

from (2.4). Prior to finding the new equation for Cgc_m, let the Cgc_m for two intervals

of equal values be denoted as Cgc_m_symmetric and the Cgc_m for two different intervals

be denoted as Cgc_m_asymmetirc. So, Cgc_m is function of the intervals (as in (2.11)) and

Cgc_m_symmetric is added to (2.6).

Figure 2.2: Planar view of CNTFET with undeposited CNTs showing intervals

⎭⎬⎫

⎩⎨⎧

≠=

=21asymmetricmgc

21symmetricmgcmgc intintC

intintCC

__

___ (2.11)

35

Two cases can be distinguished: (A) If Cgc_m_asymmetirc is found from (2.4), then

new values for η1 and η2 in (2.3) should be found. (B) If Cgc_m_symmetric is found from

(2.4), then η1= η2= Cgc_e / Cgc_m and Cgc_sr_1=Cgc_sr_2 because int1=int2 [5]. For

Cgc_m_asymmetirc, int1≠int2 (Figure 2.3), two values for Cgc_e (denoted by Cgc_e_int1 and

Cgc_e_int2), two values for Cgc_m_asymmetric (denoted by Cgc_m_asymmetric_int1 and

Cgc_m_asymmetric_int2), and two values of Cgc_sr (denoted by Cgc_sr_int1 and Cgc_sr_int2) must

be found as related to the two intervals (int1 and int2). In this model (as consistent

with the existing technical literature), it is assumed that CNTs that are spaced further

apart from the two intervals considered, have a negligible effect, i.e. when

calculating Cgc_m of CNT #1, only the two intervals (int1 and int2) to two adjacent

deposited CNTs (#2 and #3) are considered. This is also assumed in the defect-free

case when Cgc_e and Cgc_m_symmetric are found from (2.4) as function of the pitch in a

previous section [5]. As int is a multiple of the pitch (s), then this model is consistent

and correct. By considering all components of Cgc, (2.3) and (2.4) can be modified as

(2.12) and (2.13) (Cinf is changed to Cgc_inf because it is independent of the pitch or

the interval).

For comparing Cgc_m_asymmetric with Cgc_e and Cgc_m_symmetric, its value is plotted

versus a single interval (int1) in Figure 2.4 (the second interval int2 for Cgc_m_asymmetric

is denoted by Cgc_m_asymmetric_int2). For example, in Figure 2.4, Cgc_m_asymmetirc_2s

denotes Cgc_m_asymmetric when int1 is changed from 1s to 7s and int2 is 2s. As

mentioned previously, intervals are multiples of s (and in this paper, the pitch is

s=3.812 nm). The values of Cgc_e and Cgc_m_symmetric as function of the interval (i.e.

36

(2.5) and (2.6)) [1][2] are also plotted in Figure 2.4. As shown in Figure 2.4, when

the two intervals are the same, Cgc_m_asymmetric is the same as Cgc_m_symmetric,; however,

when only one interval is changed for Cgc_m_asymmetric, the trend of Cgc_m_asymmetric is

similar to Cgc_e. Therefore, Figure 2.4 shows that the value of Cgc_m_asymmetric found by

the proposed model in the absence of defects (undeposited CNTs) is the same as the

values of Cgc_e and Cgc_m_symmetric in the original model of [1]. However, the proposed

model can also capture the impact of defects on the gate capacitance if not all CNTs

are deposited/grown as considered in this paper.

(2.12)

(2.13)

2.2.2 Proposed Drain Current Model

(2.7) and (2.8) require many parameters; however, Cgc_p mostly changes as

function of the pitch (intervals). From (2.9) and (2.11), Cgc_p can be defined

depending on the intervals (as given below in (2.14)). Once Cgc_p is found and the

2int___

2int__

__

_2

1int___

1int__

__

_1

symmetricmgc

egc

symmetricmgc

egc

symmetricmgc

egc

symmetricmgc

egc

CC

CC

CC

CC

⇒=

⇒=

η

η

2int__2int___

2int__

1int__1int___

1int__

inf_2_2

1_1

inf

__

1

1

11

1111

srgcasymmetricmgc

egc

srgcasymmetricmgc

egc

gcsrsr

asymmetricmgc

CCC

B

CCC

A

BACCCC

C

⋅=

⋅=

++=

⋅+⋅+=

ηη

37

gate voltage (VGS) is specified, then ΔΦB can be calculated from (2.8); using ΔΦB and

the drain voltage (VDS), the drain current of the CNTFET can be calculated from

(2.7).

Figure 2.3: Proposed gate to channel capacitance model for a CNTFET with defects

(2.14)

2.2.3 Simulation Results

In this section, the drain current, capacitance, and delay in a CNTFET are

calculated by using MATLAB as function of NCD for VGS=0.9v, (19,0) as chirality

vector, N=9, and Wg=32nm. The drain current is found over the range of VDS (from

0v to 0.9v). (19,0) and N=9 are selected for consistency with the technical literature

[1][2]; moreover under these parameter values, the CNTFET has better performance

⎪⎩

⎪⎨

⎧

≠=

===

21asymmetricmgc

21symmetricmgc

21egc

pgc

intintCintintC

0intor0intCC

__

__

_

_

38

(delay and energy) than silicon CMOS when the pitch is 4nm [15]. The chirality

vector of (19,0) corresponds to a CNT diameter (d) of 1.507 nm [1]. The pitch of a

CNTFET is calculated in (2.15) using Wg, d, and N with the largest possible pitch, i.e.

the pitch is given by 3.812 nm when Wg =32nm and N=9 or in general,

)1/()( −−= NdWs g (2.15)

1s 2s 3s 4s 5s 6s 7s

140

160

180

200

220

240

260

280

300

320 Cgc_e Cgc_m_symmetric Cgc_m_asymmetric_1s Cgc_m_asymmetric_2s Cgc_m_asymmetric_3s Cgc_m_asymmetric_4s Cgc_m_asymmetric_5s Cgc_m_asymmetric_6s Cgc_m_asymmetric_7s

Cap

acita

nce

(aF/

um)

Interval (nm)

Figure 2.4: Cgc_e ,Cgc_m_symmetric, and Cgc_m_asymmetry vs. interval values for CNTFET with defects

To evaluate the effect of the intervals (as uneven spacing between CNTs) as

caused by the number and position of the defects, intervals are randomly generated

by considering NCD, Wg, and s; the effect of uneven interval will be discussed in

detail in the next section. Figure 2.5 shows the plot of the drain current versus NCD;

the drain current is reduced almost linearly when NCD increases because the CNTs

are used in the conducting channel between source and drain of a CNTFET. At a

39

fixed value of NCD, the drain current of a CNTFET changes because different

intervals may exist; this may also change Cgc (Figure 2.4) to determine the drain

current (and gate capacitance) as discussed before. The largest and least drain

currents at a fixed value of NCD are also depicted in Figure 2.5; under these

conditions, the gate capacitance and the delay are also calculated and plotted in

Figure 2.6 and Figure 2.7 respectively. Figure 2.6 shows that the total gate

capacitance decreases almost linearly by increasing NCD because by (2.1), the gate

capacitance consists of the sum of the capacitances of all deposited CNTs. Having

found the drain current and gate capacitance, the delay is calculated by using the

CV/I equation [15] (Figure 2.7); this shows that the delay increases exponentially

with NCD and, when NCD is fixed, the delay changes too depending on the intervals.

Figure 2.5: Drain current vs. the number of CNT Defects (NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm); average, largest and least values are plotted for drain current.

0 1 2 3 4 5 6 7

20

30

40

50

60

70

80

90

100

Dra

in C

urre

nt (u

A)

Number of CNT Defects (NCD)

Average Largest Least

40

Figure 2.6: Gate capacitance vs. the number of CNT defects (NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm); average, largest and least capacitance values are plotted for gate capacitance.

Figure 2.7: Delay vs. the number of CNT defects (NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm); average, largest and least values are plotted for delay.

0 1 2 3 4 5 6 7

0.02

0.03

0.04

0.05

0.06

Gat

e C

apac

itanc

e (fF

)



0 1 2 3 4 5 6 72.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Del

ay (p

s)



41

2.3 Delay Analysis

In this paper, the CNTFET is modeled following CNT deposition in the

fabrication process; Figure 2.8 shows a CNTFET in which only 4 of the required 7

CNTs have been deposited. Its performance depends on the number of undeposited

CNTs as defects (given by NCD=3 in Figure 2.8) as well as their position; these two

features characterize the intervals. A CNTFET with N CNTs is represented by a N

binary string in which the ith bit of the binary string is 0 (1) if the ith CNT is

undeposited (deposited). This string (also referred to as configuration) denotes the

state of the CNTFET with respect to the defects and is denoted by PCD. The

substrings of 0’s are also referred to as intervals. Figure 2.8 shows also the

corresponding PCD, i.e. PCD is given by {1 0 1 0 0 1 1} when N=7, NCD =3 and three

intervals exist. Let the number of combinations of NCD defects be denoted by NCCD

and

(2.16)

An algorithm for deterministically calculating the delay of a CNTFET with

undeposited CNTs is proposed in this section using the previous presented model for

the capacitance and current. This algorithm (referred to as Algorithm 2.1) utilizes a

combinatorial routine (i.e. nchoosek in MATLAB) for finding all possible PCD’s

combination (NCCD); every ith combination in the CNTFET is considered. Then, in

each PCD, both intervals of deposited CNT (N-NCD) are established; every jth CNT’s

)!(!!

CDCDCDCDC NNN

NNN

N−×

=⎟⎟⎠

⎞⎜⎜⎝

⎛=

42

both intervals are described as int1(j) and int2(j). Based on the values of the intervals,

Cgc_p is determined using (2.5),(2.6),(2.13), and (2.14). Having found Cgc_p, the gate

capacitance of the CNTFET is calculated by (2.1) (the current of each individual

CNT can be calculated using Cgc_p by (2.7) and (2.8)). By adding the currents of all

CNTs, the current of the CNTFET is found. Finally, the delay is calculated using the

well known CV/I equation.

Figure 2.8: Configuration (and its definition) of a CNTFET (planar view) with undeposited CNTs and intervals.

To assess the deviation of the largest and least values with the average value in

drain current, gate capacitance, and delay, the Relative Standard Deviation (RSD) is

calculated; the results are plotted in Figure 2.9. Figure 2.9 shows that the RSDs for

the rate of change in drain current and capacitance have different values. As both

drain current and gate capacitance vary as function of Cgc (as related to the intervals

43

int1 and int2 of each CNT), the rate of change for the gate capacitance is larger than

for the drain current. Moreover, the maximum deviation point for the gate

capacitance is different from the current, because the gate capacitance is affected not

only by Cgc, but also by Cgtg and Wg (as in (2.1)). Therefore, the RSD for the delay is

affected mostly by the gate capacitance. (2.16) is also plotted in Figure 2.10; NCCD

has maximum value when NCD is 4 and 5, however the maximum deviation point for

the delay does not occur at maximum NCCD, therefore the deviation in delay cannot

be simply expected from the number of combinations.

Algorithm Delay begin do algorithm for choosing NCD from N for i to NCCD for j to N-NCD if int1(j)=0 or int2(j)=0 Cgc_p(j)=Cgc_e (int1(j), int2(j)) else if int1(j)==int2(j) Cgc_p(j)=Cgc_m_symmetric(int1(j)) else Cgc_p(j)=Cgc_m_assymetric(int1(j), int2(j)) end Cgc(i) {Cgc_p(j)} Total_I(i) Isemi(VGS, VDS, Cgc_p(j)) end Cgg,CNTFET(i)(Wg, Lg, Cgc(i)) Delay gg,CNTFET(i)=(4·Cgg,CNTFET(i)·V)/ Total_I(i) end end

Algorithm 2.1: Delay Calculation for a CNTFET with Undeposited CNTs

U

U

44

For analyzing the effect of the configurations (i.e. PCD ) that result in the largest

and least delays, let the PCD for the largest delay and the PCD for the least delay be

denoted as PCD_Largest and PCD_Least respectively. Depending on PCD, when the two

intervals (int1 and int2) of each deposited CNT change due to defects, variations in

current, capacitance, and delay (at a fixed NCD) occur in the operation of the

CNTFET. Tables 2.1 and 2.2 show the two intervals of CNTs for largest and least

delays respectively. For example, when NCD=6 in Tables 2.1 and 2.2 (this value is

chosen because the RSD for the delay is maximum when NCD=6 as reported

previously in Figure 2.9), there are 3 deposited CNTs in a CNTFET and two

different combinations of intervals. In Table 2.1, the two CNT intervals are ∞s and

4s nm, and all single CNT intervals are 4s nm. ‘∞’ means that the CNT has only one

adjacent CNT on one side (i.e. the CNT is positioned at the edge of the CNTFET).

As mentioned previously, s denotes the pitch (in this case 3.812 nm). These CNT

configurations are shown in Figure 2.10 (a). In Table 2.2, the two CNT intervals are

∞s nm and 1s nm, and all single CNT intervals are 1s nm. These CNTs are also

shown in Figures 2.10 (b), (c), and (d) depending on PCD . This is not a unique CNT

configuration; in this case, there are four additional configurations that would result

in the least delay under the same conditions (these CNT configurations are not

shown). As shown in Tables 2.1 and 2.2 as well as Figure 2.10, when CNTs are not

positioned between correctly deposited CNTs, all intervals between CNTs have the

smallest values, thus the delay has the least value. When non-defective CNTs have

the largest intervals, the delay becomes the largest. In general, when the intervals

45

decrease, the drain current decreases due to the screening effect [1][2] and the gate

capacitance also decreases due to the decrease of Cgc (Figure 2.6 and (1)). However,

Tables 2.1 and 2.2 show that the delay decreases as the delay is mostly affected by

the gate capacitance in the CV/I equation. These results are consistent with the

results of the RSDs in Figure 2.9.

0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16 RSD for Drain Current RSD for Gate Capacitance RSD for Delay NCCD


Rel

ativ

e S

tand

ard

Dev

iatio

n (R

SD

) (%

)

0

50

100

150 Num

ber of Com

binations for CN

T Defects (N

CC

D )

Figure 2.9: Relative standard deviation and the number of combinations for CNT defects (NCCD) vs. the number of CNT defects (NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm) for drain current, gate capacitance and delay

46

Table 2.1: Two intervals of CNTs for largest delay (VGS=0.9V, (19,0), N=9)

NCD int1 (nm) int2 (nm) Number of CNT

1

∞s 1s 1 ∞s 2s 1 1s 1s 5 1s 2s 1

2 ∞s 2s 2 1s 2s 2 1s 1s 3

3

∞s 2s 2 1s 1s 1 1s 2s 2 2s 2s 1

4 ∞s 2s 2 2s 2s 3

5

∞s 2s 1 ∞s 3s 1 2s 3s 1 3s 3s 1

6 ∞s 4s 2 4s 4s 1

7 ∞s 8s 2

Table 2.2: Two intervals of CNTs for least delay (VGS=0.9V, (19,0), N=9)

NCD int1 (nm) int2 (nm) Number of CNT

1 ∞s 1s 2 1s 1s 6

2 ∞s 1s 2 1s 1s 5

3 ∞s 1s 2 1s 1s 4

4 ∞s 1s 2 1s 1s 3

5 ∞s 1s 2 1s 1s 2

6 ∞s 1s 2 1s 1s 1

7 ∞s 1s 2

47

Figure 2.10: Configuration (PCD) for largest delay ((a)) and configurations (PCD ) for least delay ((b), (c), and (d)) (VGS=0.9V, (19,0), N=9, NCD=6, Wg=32nm); planar views

2.4 Probabilistic Analysis

In practice, PCD and NCD are affected by manufacturing; so, a probabilistic process

is also proposed to calculate the probability of a given PCD to occur (this is denoted

as PROBPCD). Let the random variable for the number of CNT defects be denoted as

XCD with range S={0,1,…,N}; XCD is assumed to be independently distributed and

the probability of CNT defects is given by pCD (0≤ pCD≤ 1). Then, PROBPCD can be

written as

48

100)1(][ )( ×−××⎟⎟⎠

⎞⎜⎜⎝

⎛== − CDCD NN

CDN

CDCD

CDCDPCD ppNN

NXPROB (2.17)

Using the previously defined NCCD in (2.16), (2.17) can be written as

100)1(][ )( ×−××== − CDCD NNCD

NCDCCDCDCDPCD ppNNXPROB (2.18)

For current technology, CNT synthesis techniques yield ~33% metallic CNTs;

however, [16] has reported 4% metallic CNTs. Other CNT defects (due to

misposition and mis-alignment) can occur [5]; 99.5% of all CNTs can be correctly

aligned when the average density of the CNTs is 5-10 CNTs/μm. However, 250

CNTs/μm is required to ensure better performance (delay and energy) than silicon-

CMOS [15]. This higher CNT density is used in this paper to measure the

performance degradation with respect to an ideal CNTFET performance. Compared

with [5] at least a 10% decrease in probability of correct alignment can be expected

for more than two orders of magnitude increase in density [17,18], i.e. it is assumed

that 90% of all CNTs are aligned when the CNT density is 250 CNTs/μm. As no

relation has been established between the presence of metallic CNT and

mispostioned (and misaliged) CNTs, pCD can be calculated probabilistically as below

in (2.19).

232.0

2.004.02.004.0____

=×−+=

×−+= −− positionedMisCDMetallicCDpositionedMisCDMetallicCDCD ppppp

(2.19)

49

Based on (2.19), PROBPCD can be calculated as function of NCD using (2.18); the

results are plotted in Figure 2.11. The average delay increase (in % from Figure 2.7)

and RSD (in % from Figure 2.10) are also depicted in Figure 2.11. Figure 2.11 shows

that PROBPCD decreases as NCD increases; also, the average delay increases

exponentially, while RSD has non-ignorable value.

Previously, it has been shown that the delay is not strictly related to NCD and there

exist many configurations (PCD) for which the intervals are the same (as shown in

Figures 2.10 (b), (c), and (d)). The number of configurations (in this case denoted as

NPCD) with same interval(s), is dependent on the interval values, NCD, and N. So, the

corresponding PROBPCD that results in the largest (PROBPCD_Largest) or least delay

(PROBPCD_Least), depends on NCD and N . They can be calculated using (2.18), as

PCDCCDLeastPCDLeastPCD

PCDCCDeLPCDeLPCD

PROBNNPROB

PROBNNPROB

×=

×=

)/(

)/(

__

arg_arg_ (2.20)

NPCD_Largest and NPCD_Least can be found by selecting the largest and least values of

the configurations with the largest and least delays for Cgg,CNTFET in Algorithm 2.1

(when NCD and N are given as inputs). PROBPCD_Largest, PROBPCD_Least, NPCD_Largest,

NPCD_Least, and NCCD are reported as function of NCD for N=9 in Table 2.3. When

comparing PROBPCD_Largest with PROBPCD_Least, the values of PROBPCD_Largest are

smaller than for PROBPCD_Least because, in general, PCD_Largest requires configurations

with large intervals and the number of such configurations is very small (PCD_Least is

found in configurations with small intervals, such that most CNTs are deposited and

50

NPCD_Least increases linearly as NCD is increased). However, PROBPCD_Least does not

simply increase as NCD is increased because NCCD changes differently; for example,

when NCD is 4 and 5, NCCD has the largest value, and NCCD decreases when NCD

increases or decreases from 4 or 5. As the values of NCCD are larger than those of

NPCD, then the probability for least delay is affected more by NCCD than NPCD.

1 2 3 4 5 6 7

0

5

10

15

20

25

30

35

40

45

50

55

60

Perc

enta

ge (%

)


PROB_PCD Average Delay Increase RSD

Figure 2.11: PROBPCD, Delay Increase, and RSD vs. Number of CNT Defects

(NCD) (VGS=0.9V, (19,0), N=9, Wg=32nm) in a CNTFET

Table 2.3: Configuration probability for largest and least delays (VGS=0.9V, (19,0), N=9)

Probability NCD1 2 3 4 5 6 7

PROBPCD_Largest (%) (NPCD Largest,,NCCD)

5.616 (2,9)

0.848 (1,36)

0.513(2,84)

0.077(1,126)

0.047(2,126)

0.007 (1,84)

0.002(1,36)

PROBPCD_Least (%) (NPCD Least, NCCD)

5.616(2,9)

2.545(3,36)

1.025(4,84)

0.387 (5,126)

0.140(6,126)

0.049 (7,84)

0.017(8,36)

51

2.5 Conclusion

This chapter has presented a new analytical model for characterizing the delay

performance of a CNTFET when undeposited CNTs occur as defects in the

deposition/growth process for fabrication. One of the defect types that can occur

when fabricating a CNTFET, is the absence of some CNTs following the

deposition/growth step. It has been shown that this type of defect will change the

operational characteristics of a CNTFET because drain current, gate capacitance, and

delay are affected due to the lower number of CNTs present in the channel of the

transistor. Hence, a new model by which the drain current, the gate capacitance and

the delay are found when not all CNTs are deposited has been proposed. The uneven

CNT spacing in the channel results in new equations that are still applicable for both

defective and defect-free CNTFETs. The proposed model has been implemented in

MATLAB and has been extensively simulated to show that defects due to

undeposited CNTs have a significant impact on the operation of a CNTFET. Delay

as degradation in performance is shown to be related to both the number and position

of the defects; an extensive delay analysis on both deterministic and probabilistic

basis has been presented.

52

Chapter 3 Delay Analysis of a CNTFET with Undeposited CNTs by Gate Width Adjustment


promising emerging technologies to extend and complement the silicon MOSFET

due to its excellent performance, however, the defects related to the number and

position of CNTs (undeposited CNTs) in a CNTFET, the CNTFET’s superior

performance can be degraded severely [1][2][53][54][55][56]. To assess the effect of

undeposited CNTs, in previous chapter, a MATLAB-based model for a CNTFET

with undeposited CNTs as defects is proposed and an extensive simulation are

performed [35]. The analysis shows that the delay in a CNTFET significantly

53

increases with the number of undeposited CNTs and the deviation in delay depends

on the position of the undeposited CNTs. While the proposed model offers

significant advantages in terms of electrical characteristics (such as current and gate

capacitance), the analysis of a CNTFET in the presence of undeposited CNTs

remains elusive and its overall performance is still unpredictable in the presence of

these defects.

To mitigate the change of in delay, in this chapter, a new corrective action to the

fabrication process is suggested; based on the capabilities of today’s lithography, two

methods are proposed for reducing the delay and the deviation by adjusting the gate

width (and removing CNTs) of the CNTFET. Using the first method for adjusting

the gate width, the average delay can be decreased, but the deviation is increased

more. To decrease this deviation, a second method has been proposed; this method

decreases the gate width only when the decreased value is above the least delay. To

evaluate these methods, a probabilistic delay analysis is then presented. The

performance of the proposed two adjustment methods is evaluated by considering

CNT features (such as chirality and defect distribution) deterministically and

probabilistically.

3.1 Gate Width Adjustment

As shown previously, the delay in a CNTFET significantly changes as function of

PCD, NCD, and the diameter (chirality). Consider the fabrication process of a

54

CNTFET. When the regions of logic cells and contacts are defined (as shown in

Figures 2 (b) and (c) respectively), predefined layouts are usually used. However,

current imaging and process technologies [11] make possible to assess NCD, PCD, and

the intervals prior to defining the logic cells and the contacts. In [11], the CNT

spacing distribution is extracted using a Scanning Electron Microscope (SEM);

moreover, a partial etching step is possible for the adjustment of this area [7].

Therefore, the process of gate width adjustment can be performed by considering

NCD and PCD and using current fabrication/manufacturing technology.

When the gate and contact regions are defined, the drain current and gate

capacitance of a CNTFET can be decreased by reducing the gate width as shown in

Figure 3.1. However, the changes in drain current and gate capacitance depend on

NCD, PCD, and diameter. Therefore, the process of adjusting the gate width is utilized

by considering those parameters (NCD, PCD, and diameter). In this paper, the

reduction of Wg is measured in units of CNTs (WRg in Figure 3.1); Figure 3.1 (a)

shows that a CNTFET contains two deposited CNTs (solid lines) and three

undeposited CNTs (dotted lines). So, WRg = 1 CNT and WRg = 2 CNTs in Figures 3.1

(b) and (c) respectively. Figure 3.1 (a) shows the pitch (s), the distance between two

CNTs (s’), and the diameter of the CNT (d) in the CNTFET. The relationship among

these parameters in Figure 3.1 is given in (3.1). (3.1) shows that the reduction in Wg

with units of number of CNTs is the same as reducing Wg with the unit of ‘s’, i.e.

WRg = 1 CNT and WRg = 2 CNTs in Figure 3.1 are equivalent and consistent with WRg

= 1s nm and WRg = 2s nm.

55

The proposed method for adjusting Wg is depicted in Figure 3.2. In Figure 3.2 (a),

there is an undeposited CNT at the leftmost position, so Wg is reduced until a

deposited CNT is found (at a new width Wg’); so in this step, PCD is also changed to

PCD’. An ‘X’ in PCD means that the (deposited or undeposited) CNT is not included

in the adjusted gate width. When a deposited CNT is found on the leftmost position,

the proposed method checks whether there is at least a undeposited CNT to the right

of the deposited CNT. If undeposited CNT(s) exist(s), the undeposited CNT(s) is

(are) discarded (denoted by PCD’’) and the delay for PCD’ and PCD’’ are compared

(Figure 3.2 (b)). If the delay for PCD’’ is smaller than for PCD’, Wg’ is reduced to Wg’’

(Figure 3.2 (c)). These steps for the discarding process are repeated until the delay

cannot be decreased any longer. Figure 3.2 (d) shows the process when the same

method is applied from right to left (Wg’’ is reduced to Wg’’’). When NCD is known,

various PCDs can then exist (NCCD) (as found previously in (1)). The proposed

method for adjusting Wg is applied to these PCDs. This algorithm is referred to as

Algorithm 3.1.

sW

ddsW

dsW

WWW

g

g

g

Rggg

−=

−×−−=

−−=

−=

)2

2(

'

'

(3.1)

56

Figure 3.1: Reducing Wg (WRg = 1 CNT and WRg = 2 CNTs)

By applying Algorithm 3.1, the delay can be reduced (Figure 3.3); the plots with

white symbols in Figure 3.3 represent the original delay values and the plots with

black symbols represent the delay values as reduced by using Algorithm 3.1. The

delay is reduced on average by 6.98%, 1.183%, and 8.92% for the average, largest,

and the least delay values respectively (at a CNT chirality of (19,0)). When

Algorithm 3.1 is applied to various CNT diameters, nearly the same trend is

established (Figure 3.4).

57

’

= {0 1 0 1 1 1 1 0 1}

= {X 1 0 1 1 1 1 0 1}

’

Applying Adjusting Method

= {X 1 0 1 1 1 1 0 1}

= {X X X 1 1 1 1 0 1}

= {X X X 1 1 1 1 0 1}

= {X X X 1 1 1 1 X X}

Applying Adjusting Method

= {X 1 0 1 1 1 1 0 1}

= {X X X 1 1 1 1 0 1}

Delay for ’

Delay for ’’>

’’

’’

’’’

Comparing Delays

is reduced to ’

Figure 3.2: Proposed method for Wg adjustment

58

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Algorithm Adjusting Wg for PCD

begin for i to NCCD

if 0 exists on the leftmost position in PCD(i) Wg is reduced until 1 is found and stored in WRg(i) Delay gg,CNTFET(i)=Delay(PCD(i), WRg(i)) end stop=0 while (stop=0) if 0 exists on the right of leftmost 1 Delay gg,CNTFET(i)= Delay(PCD(i), Wg(i)) the leftmost 1 is changed to 0 and stored in PRCD Wg is reduced until 1 is found and stored in WRg Delay Rgg,CNTFET=Delay(PRCD, WRg) if Delay Rgg,CNTFET < Delay gg,CNTFET(i) Delay gg,CNTFET(i)= Delay Rgg,CNTFET

else stop=1

end end end end for i to NCCD

if 0 exists on the rightmost position in PCD(i) Wg is reduced until 1 is found and stored in WRg(i) Delay gg,CNTFET(i)=Delay(PCD(i), WRg(i)) end stop=0 while (stop=0) if 0 exists on the left of rightmost 1 Delay gg,CNTFET(i)= Delay(PCD(i), Wg(i)) the rightmost 1 is changed to 0 and stored in PRCD Wg is reduced until 1 is found and stored in WRg Delay Rgg,CNTFET=Delay(PRCD, WRg) if Delay Rgg,CNTFET < Delay gg,CNTFET(i) Delay gg,CNTFET(i)= Delay Rgg,CNTFET

else stop=1

end end end end

end

Algorithm 3.1: Algorithm for Wg adjustment

59

-1 0 1 2 3 4 5 6 7 82.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

Del

ay (p

s)


Avg Least Avg_Adjusting_Wg Least_Adjusting_Wg

Figure 3.3: Delay vs. NCD when adjusting Wg (VGS=0.9V, (19,0), N=9, Wg=32nm)

(16,0) (17,0) (19,0) (20,0) (22,0)0.0

0.1

0.2

Aver

age

Dev

iatio

n (p

s)

(b)

(16,0) (17,0) (19,0) (20,0) (22,0)2.0

2.5

3.0

3.5

Before Adjusting Wg Adjusting Wg for Reducing Delay

Ave

rage

Del

ay (p

s)

(a)

Figure 3.4: Delay and deviation vs. the number of CNT defects (NCD) when adjusting Wg at different chiralities (VGS=0.9V, (19,0), N=9, Wg=32nm)

60

3.2 Adjustment for Reduced Delay Deviation

As discussed previous chapter, even though Algorithm 3.1 reduces the delay but

the delay deviation may increase after adjusting Wg. In Algorithm 3.1, by comparing

the reduced delay (Delay Rgg,CNTFET) with Delayleast and Delay gg,CNTFET(i) (lines 15

and 35 in Algorithm 3.1, respectively), the delay is reduced only when Delay

Rgg,CNTFET is larger than Delayleast and less than Delay gg,CNTFET(i). So an additional

‘for loop’ is required to determine the least delay as dependent on NCD. This method

is therefore a modification to Algorithm 3.2; the algorithm for Wg adjustment for

reducing the delay deviation is hereafter referred to as Algorithm 3.2. The simulation

results of Algorithm 3.2 are depicted in Figure 3.5. Compared to the original values,

Algorithm 3.2 reduces the deviation by 44.444% with a 2.141% delay reduction.

When the original Algorithm 3.1 is applied, the delay is reduced by 6.968% but the

deviation is increased by 30.952%. Therefore, an improvement of 75.397% in

deviation is achieved at the expense of a 4.827% delay degradation (Figure 3.7) by

utilizing Algorithm 3. Algorithm 3 has also been applied to CNTFETs with different

chirality vectors (Figures 3.6 and 3.7). In these cases, the delay is decreased on

average by 6.968% while the average deviation increases by 32.444%. When

Algorithm 2.3 is applied, the average deviation is decreased by 44.195% on average,

while the average delay reduction is 2.166%. So, Algorithm 2.3 achieves a 76.603%

improvement at the expense of a 4.801% degradation in delay.

61

0 1 2 3 4 5 6 72.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

Del

ay (p

s)


19_0 Avg 19_0_Least 19_0 Avg 19_0_Least

Figure 3.5: Delay vs. the number of CNT defects (NCD) when adjusting Wg for reducing deviation (VGS=0.9V, (19,0), N=9, Wg=32nm)

(16,0) (17,0) (19,0) (20,0) (22,0)0.0

0.1

0.2

Ave

rage

Dev

iatio

n (p

s)

(b)

(16,0) (17,0) (19,0) (20,0) (22,0)2.0

2.5

3.0

3.5

Before Adjusting Wg Adjusting Wg for Reducing Deviation

Aver

age

Del

ay (p

s)

(a)

Figure 3.6: Delay vs. the number of CNT defects (NCD) when adjusting Wg for reducing deviation at different chirality values (VGS=0.9V, (19,0), N=9, Wg=32nm

62

(16,0) (17,0) (19,0) (20,0) (22,0)-60

-40

-20

0

20

40

60

73.387%73.984%75.397%

Red

uced

Ave

rage

Dev

iatio

n (%

)

(b)

3.968%4.484%4.827%5.191%5.537%

77.778%82.468%

(16,0) (17,0) (19,0) (20,0) (22,0)0

5

10 Adjusting Wg for Reducing DelayAdjusting Wg for Reducing Deviation

Red

uced

A

vera

ge D

elay

(%)

(a)

Figure 3.7: Reduction in average delay (%) and average deviation between average delay and least delay (%) vs. chirality (VGS=0.9V, N=9, Wg=32nm)

Figures 3.8 and 3.9 show both the reduction in average delay and deviation when

the proposed methods are probabilistically applied to the delay values at various

chirality and standard deviation values. Figure 3.8 shows that the reduced average

delay values by using Algorithm 3.1 (white symbols) are larger than the reduced

average delay values by Algorithm 3.2. When the standard deviation is increased

(Figure 3.8), the reduction in average delay increases (the triangular symbols have

larger values than the rectangular symbols) because, when the standard deviation is

increased, larger delay values are possible and they can be reduced by the proposed

two algorithms. In this case the least delay values are reduced too. Therefore, when

the standard deviation is increased, the difference between the two proposed gate

adjustment methods reduces.

63

As shown in Figure 3.3 for Algorithm 3.1, the deviation between the average and

least values is increased (in Figures 3.7 (b) and 3.9 this is indicated by negative

values). Figure 3.9 shows that the delay deviation decreases for an increase of the

standard deviation as the least delay values also reduce. Therefore, at an increased

standard deviation, the difference between the two proposed gate adjustment

methods is not significant; moreover as the chirality is increased (Figures 3.8 and

3.9), the current in each CNT is increased and the delay is less sensitive to the

undeposited CNTs.

(16,0) (17,0) (19,0) (20,0) (22,0)2

3

4

5

6

7

8

9

10

3.517%

1.831%

4.487%

2.329%

4.056%

2.417%

4.844%

2.520%2.868%

Adjusting Wg for Reducing Delay 0.01 Adjusting Wg for Reducing Delay 0.1 Adjusting Wg for Reducing Deviation 0.01 Adjusting Wg for Reducing Deviation 0.1

Red

uced

Av

erag

e D

elay

(%)

Chirality

5.178%

Figure 3.8: Reduction in average delay vs. chirality at standard deviation values of 0.01 and 0.1(VGS=0.9V, N=9, Wg=32nm)

64

(16,0) (17,0) (19,0) (20,0) (22,0)-20

-10

0

10

20

30

40

50

60

70

58.543%

20.705%

57.957%

18.510%

55.730%

18.653%

57.606%

19.158%

59.027%

16.495%

Adjusting Wg for Reducing Delay 0.01 Adjusting Wg for Reducing Delay 0.1 Adjusting Wg for Reducing Deviation 0.01 Adjusting Wg for Reducing Deviation 0.1

Red

uced

A

vera

ge D

evia

tion

(%)

Chirality

Figure 3.9: Reduction in average deviation vs. chirality at standard deviation values of 0.01 and 0.1 (VGS=0.9V, N=9, Wg=32nm)

The summary of the results for the proposed methods under the deterministic and

probabilistic analysis (DA and PA) is provided in Table 3.1. Table 3.1 shows that the

simulation results between DA and PA are similar except for the reduction in

average deviation values (and the difference values) when adjusting Wg for delay

reduction (Algorithm 3.1). In DA Algorithm 3.1 reduces the delay by 6.968%, but

the deviation is increased by 32.444%. Algorithm 3.2 reduces the deviation by

44.159% with a 2.166% delay reduction. In PA, the adjustment of Wg for reducing

the delay by Algorithm 3.1 reduces the delay and deviation by 7.811% and 9.788%

respectively. The adjustment of Wg for reducing the delay deviation by Algorithm

3.2 reduces the deviation by 47.476% with a 4.409% delay reduction.

65

Table 3.1: Summary of results of proposed methods by adjusting WG

Analysis Method

Reduction in average delay (%)

Reduction in averagedeviation (%)

Difference (%)

Chi- rality σ

Wg

adjustment for

reducingdelay

Wg adjustment

for reducingdeviation

Wg adjustment

for reducing

delay

Wg adjustment


Wg adjustment

for reducing

delay

Wg adjustment


DA

(16,0)

N/A

7.264 1.727 -41.558 40.909 5.537 82.468 (17,0) 7.195 2.004 -34.641 43.137 5.191 77.778 (19,0) 6.968 2.141 -30.952 44.444 4.827 75.397 (20,0) 6.873 2.389 -28.455 45.528 4.484 73.984 (22,0) 6.537 2.570 -26.613 46.774 3.968 73.387

PA

(16,0) 0.01 7.468 2.291 -16.102 42.925 5.178 59.027 0.05 8.326 4.277 10.684 47.617 4.048 36.933 0.1 8.615 5.746 33.842 50.337 2.868 16.495

(17,0) 0.01 7.418 2.574 -12.830 44.776 4.844 57.606 0.05 8.236 4.521 10.876 48.036 3.715 37.159 0.1 8.523 6.003 32.180 51.338 2.520 19.158

(19,0) 0.01 7.216 2.729 -10.420 45.310 4.487 55.730 0.05 7.978 4.622 11.103 47.630 3.356 36.527 0.1 8.260 5.843 30.768 49.421 2.417 18.653

(20,0) 0.01 7.101 3.045 -9.541 48.416 4.056 57.957 0.05 7.846 4.692 10.972 46.866 3.153 35.893 0.1 8.122 5.793 29.498 48.008 2.329 18.510

(22,0) 0.01 6.769 3.252 -10.328 48.215 3.517 58.543 0.05 7.518 4.808 9.452 45.882 2.710 36.431 0.1 7.777 5.946 26.660 47.365 1.831 20.705

66

3.3 Conclusion

This chapter has presented a detailed analysis (inclusive of related algorithms)

and extensive simulation results to assess the effect of undeposited CNTs in a

CNTFET. The analysis considers the number and position of the undeposited CNTs

using the model of [35]. The presented analysis has shown that the delay drastically

increases as the number of undeposited CNTs is increased and a significant deviation

is present as related to the position of the undeposited CNTs. When the undeposited

CNTs are grouped together (the deposited CNTs are separated by small intervals),

the delay has the least value. However when the deposited CNTs are separated by the

largest intervals, then the delay is also the largest. A probabilistic analysis also has

been presented to assess the impact of the number and position of the undeposited

CNTs.

Next, based on the capabilities of current lithographic technology, two methods

for adjusting the gate width have been proposed; these methods adjust and remove

CNTs at the gate. Using these methods, the delay and deviation can be reduced .

Using the first method for adjusting the gate width, the average delay can be

decreased by 6.968%. However, the deviation is increased by 32.444%. To decrease

this deviation, a second method has been proposed; this method decreases the gate

width only when the decreased value is above the least delay. To verify these two

approaches, a probabilistic analysis has also been performed by utilizing normal and

uniform distributions. The analysis has shown that the simulation results from the

67

deterministic analysis and the simulation results based on a probabilistic analysis are

almost similar. In the deterministic analysis, the first gate adjustment method shows

that the average delay can be reduced by 7.014%, but the deviation is increased by

32.941%. The second gate adjustment method reduces the deviation by 43.971%

with 2.111% delay reduction. In the probabilistic analysis, the first method reduces

the delay and the deviation by 7.811% and 9.788% respectively. The second method

reduces the deviation by 47.476% with 4.409% delay reduction.

68

Chapter 4 A Linear Programming Method for HSPICE Simulation of CNTFETs with Uneven Defective CNTs

Some of the likely defects that may occur when fabricating CNTFETs are the

change of chirality and the absence of some CNTs (undeposited CNTs) with uneven

spacing between CNTs. As a result of this type of defect, a CNTFET will show a

change in operational characteristics severely because the current and the gate

capacitance could be changed. To evaluate the performance of CNTFET, various

CNTFET model has been proposed [12][35][64][65][66][67][68] and, in Chapter 2

and Chapter 3, the MATLAB-based CNTFET model [35] is suggested and utilized.

However, the MATAB-based model requires highly iterative simulation to evaluate

69

the undeposited CNTs and it cannot perform circuit level simulation. The HSPICE-

based model of [12] is widely used in CNTFET circuit design. However, in [12], the

spacing between CNTs (pitch) of a CNTFET is assumed to be constant; so, the effect

of uneven spacing caused by undeposited CNTs cannot be evaluated. Statistical

approaches have been reported in the technical literature [1][2][10][11] using the

HSPICE model of [12] to assess the impact of those defects. However, this approach

requires assumption; whole CNTs are evenly spaced. Therefore, this approach

cannot evaluate the change of delay deterministically depending on the number and

the position of CNTs. To evaluate the uneven spacing between CNTs, [35] has

suggested a MATLAB-based model for a CNTFET. With this model, [35] has

reported that overall delay values rapidly increase depending on the number of

undeposited CNTs and the deviation of delay (between largest and least values) is

caused by the position of undeposited CNTs. However, with [35], circuit level delay

analysis cannot be performed because [35] is MATLAB-based model. Moreover, the

number of combination for the position of CNTs in a CNTFET is increased rapidly

as the number of deposited (or undeposited) CNT is increased. This can require

highly iterative simulation to evaluate the effect of unevenly positioned CNTs in

CNTFET HSPICE simulation.

To evaluate the effect of mentioned variations (the chirality, the number, and the

position of CNTs) in CNTFET HSPICE simulation, in this paper, a linear

programming methodology to find parameters (number, pitch, doping level, and

chirality of CNTs) which can be used in HSPICE simulation and represent the effect

70

of uneven space between CNTs is proposed. First, the current and gate capacitance

of CNTFET which has unevenly positioned CNTs are calculated using existing

MATLAB-based HSPICE Model [35]. Then, by using linear programming, proper

parameters (number, pitch, doping level, and chirality of CNTs) which can be used

in HSPICE simulation and represent the calculated current and gate capacitance are

obtained. The achieved parameters can cover the change in current and gate

capacitance caused by various number and position of undeposited CNTs with small

number of simulation; so, the number of simulation iteration can be reduced

eventually. In previous works [1][2][15], to evaluate the effect of undeposited CNTs

in HSPICE simulation, performance (delay, energy, and PDP) is measured in five

stages fan-out of four inverter chain under various process variations (i.e. 8% or 32%

undeposited CNTs and 1.5±0.3 nm diameter variation). However, in the simulation,

it is assumed that deposited (or undeposited) CNTs are evenly spaced. To assess the

effect of unevenly positioned CNTs, in this paper, the performance of five stages

fan-out of four inverter chain is measured considering the process variations. When

these simulations are performed, the simulation time and memory usage are also

measured in detail to make sure that the proposed method is computationally feasible

for common usage.

4.1 A Model for Uneven Defective CNTFET

To discuss the number and the position of CNTs, in this paper, the previously

proposed MATLAB-based CNTFET model [35] is utilized first (Figure 4.1). In the

71

model it is assumed that the deposited or undeposited CNTs are separated by the

same pitch (s) (s= 3.812 nm); the deposited CNTs are aligned with different intervals

(denoted as ‘int1’ and ‘int2’) and each int in a CNTFET is a multiple of the pitch (i.e.

s). For example, inta=2s and intb=1s. The positions of CNT Defects (PCD) are

represented by the Boolean vector; the ith bit of the binary string is 0 (1) if the ith

CNT is undeposited (deposited). This string (also referred to as configuration)

denotes the state of the CNTFET with respect to the CNT defects. Figure 4.1 shows a

PCD = {1 0 1 1} when the Number of CNT Defects (denoted by NCD) is 1.

Figure 4.1: A model for uneven defective CNTFET [10]

72

The existing HSPICE model of [12] is widely used in CNTFET circuit design.

However, [12] can only deal with a CNTFET with evenly spaced CNTs as shown in

Figure 4.2; a deposited (undeposited) CNT is depicted by a solid (dotted) line.

However, as mentioned before, in real CNTFET manufacturing process, the

positions of deposited (undeposited) CNTs are randomly changed; so the space

between CNTs can be uneven as shown in Figure 4.3. Moreover, unevenly

positioned CNTs increase the Number of Configurations for CNT Defects (NCCD)

severely comparing to evenly positioned CNTs as the total number of deposited and

undeposited CNTs in a CNTFET (denoted by N) and NCD is increased. For example,

when N is 9 and NCD is changed from 0 to 6, NCCD is 30 (is 465) when CNTs are

evenly (unevenly) positioned [35].

Figure 4.2: The positions of CNT defects (PCD) when CNTs are evenly positioned.

73

Figure 4.3: The positions of CNT defects (PCD) when CNTs are unevenly positioned. To evaluate the effect of unevenly positioned CNTs, [35] suggests MATLAB-

based CNTFET model and measures performance (considering whole NCCD, 465) in

a CNTFET. It reports that overall delay values increase exponentially depending on

NCD and the deviation (between largest and least value) of delay is changed by PCD

when NCD is fixed. Moreover, when chirality is changed at the same time, delay is

changed more severely [36]. From these simulation results, it can be expected that,

when CNTFET circuit is consist of CNTFETs which has unevenly positioned CNTs,

the performance of CNTFET circuit also can be degraded severely depending on PCD,

NCD, and chirality. However, with the MATLAB-based model, circuit level delay

analysis cannot be performed because the model is MATLAB-based and highly

iterative simulation is also required for the delay analysis because 465 times

74

simulation is necessary to measure the delay of each CNTFET in CNTFET circuit.

Therefore, new methodology to measure the effect of unevenly positioned CNTs in

HSPICE simulation is necessary and the required number of simulation runs should

be reduced.

4.2. Linear Programming

To assess the effect of unevenly positioned CNTs in CNTFET HSPICE

simulation, in this paper, a linear programming methodology to find parameters

(number, pitch, doping level, and chirality of CNTs) which can be used in HSPICE

simulation and represent the effect of uneven space between CNTs is proposed. First,

when a CNTFET which has unevenly positioned CNTs is given as shown in Figure

4.4 (a), the current (IT) and the gate capacitance (CT) of the CNTFET are calculated

using previously proposed MATLAB-based model [35]. Equations for IT and CT are

written in (4.1) and (4.2) respectively. (4.1) and (4.2) show that the total current and

gate capacitance in a CNTFET is calculated by summing each CNT’s current and

gate to channel capacitance (Cgc). (In this paper, the each CNT’s current and Cgc is

called by ‘variables’). The current of each CNT and Cgc also can be changed by

various factors and, in theory, every factors can be considered and solved in the

proposed methodology, but, in this paper, two parameters (interval (int) and diameter

(d)) which are related to uneven space between CNTs and the diameter of CNTs

(CNT count variations), are discussed. In Figure 4.4 (a), there are 3 CNTs. One CNT

is on the middle and Two CNTs are at the edge; so, in (4.1), the currents for the CNT

75

in the middle and at the edge are denoted by two variables (Isemi_middle and Isemi_edge)

and the variables are represented by a function of two parameters (int and d). In (4.2),

Cgc is is also a function of int and d, Lg is the gate length, fmiller is the Miller factor,

Cgtg is the gate to gate capacitance, and Wpitch is the device pitch in the width

direction. It is assumed that Wpitch is the same as the gate width (Wg) (Wpitch is also

defined as the width of the lithographically defined gate). The outer fringe

capacitance (Cof) is not considered because it is not a major component of the total

gate capacitance [5].

Figure 4.4: A model for uneven defective CNTFET (a) and a model for even defective CNTFET (b)

76

Tedgesemi

middlesemiedgesemi

IdI

dIdI

=+

+

),0,(int

),int,(int),0,(int

22__

211__11__ (4.1)

Tpitchgtgmillergsemigc

semigcsemigc

CWCfLdC

dCdC

=⋅⋅⋅+⋅+

+

2)},0,(int

),int,(int),0,(int{

23__

212__11__ (4.2)

As mentioned previously, HSPICE-based CNTFET model (Figure 4.4 (b)) cannot

support uneven space between CNTs; so, MATLAB -based CNTFET model is used

when calculating IT and CT. Figure 4.4 (b) represent a CNTFET which has evenly

positioned CNTs (It is assumed that the number of CNTs is N’); so, it has only one

kind pitch (s’). The current and gate capacitance for Figure 4.4 (b) (IT’ and CT’) can

be calculated as written in (4.3) and (4.4) respectively.

')',0,'(2)',','()2'( __ Tedgesemimiddlesemi IdsIdssIN =⋅+⋅− (4.3)

''2)}',0,'(2

)',','()2'{(

__

__

Tggtgmillergedgesemigc

middlesemigc

CWCfLdsC

dssCN

=⋅⋅⋅+⋅⋅+

⋅− (4.4)

Generally, when CNTs are deposited in a CNTFET, HSPICE-based CNTFET

model assumes that the first two CNTs are placed at the edge in a CNTFET and

other CNTs are placed between them with fixed pitch [12]. Therefore, in the

HSPICE-based CNTFET model, when pitch (s’) (and diameter (d’)) is fixed and N’

is bigger than 2, the current and the gate capacitance (IT’ and CT’) can increase

linearly depending on N’ because, in (4.3) and (4.4), variables (Isemi_middle, Isemi_edge,

Cgc_semi_middle, and Cgc_semi_edge) are constant when s’ and d’ are fixed. Other

77

parameters such as Lg, fmiller, and Cgtg, are also constant because they are not a

function of s’ and d’. Gate width of Figure 4.4 (b), W’ also can be increased linearly

depending on N’ when s’ and d’ are fixed as written in (4.5); so, (4.4) can be written

as in (4.6).

'')1'(' dsNWg +⋅−= (4.5)

'}')1'{(2

)}',0,'(2)',','()2'{( ____

Tgtgmillerg

edgesemigcmiddlesemigc

CdsNCfL

dsCdssCN

=+⋅−⋅⋅⋅+⋅

⋅+⋅− (4.6)

In conclusion, when uneven defective CNTFET is given, its IT and CT can be

calculated by using MATLAB-based model. Then, IT’ and CT’ are increased linearly

by increasing N’ until IT’ and CT’ become almost same as IT and CT. As written in

Table 1, this process can be represented in Linear Programming (LP) equation and

proper N’ can be found by Linear Programming. In the Linear Programming, the

increment of IT’ and CT’ are determined by the variables (Isemi_middle, Isemi_edge,

Cgc_semi_middle, and Cgc_semi_edge); so, parameters (such as int’ and d’), which decides

the amount of Isemi_middle and Cgc_semi_middle, have to be adjusted carefully to reduce the

error between IT (CT) and IT’ (CT’) respectively. In this paper, the error between IT

(CT) and IT’ (CT’) are denoted as EI (EC). Detailed steps for this process are shown in

Figure 4.5.

78

Table 4.1: Linear programming

Objective Function Maximize N’

Constraints

(a) (N’-2)· Isemi middle ≤ IT -2·Isemi edge (b) (N’-2) ·Cgc_semi_middle·Lg ≤ CT –[fmiller·2·Cgtg·{(N’-1) ·s’+d’)}]-(2·Cgc semi edge·Lg)

(c) N’ ≥ 3 (d) s’ > 2×d’

Figure 4.5: Flow chart

79

4.3 The Adjustment of Variables (STEP3)

For the execution of LP in Table1, the variables (Isemi_middle, Isemi_edge, Cgc_semi_middle,

and Cgc_semi_edge) must be determined first. To determined those values properly, in

this paper, three parameters (the diameter of CNTs (d’), the source/drain doping

level, and pitch (s’)) are considered (d’ is determined by chirality ((n1’, n2’)) as

mentioned before). By optimizing the parameters, in this chapter, EI and EC will be

decreased as much as possible.

4.3.1 Chirality

As mentioned previously, the value of variables (Isemi_middle, Isemi_edge, Cgc_semi_middle,

and Cgc_semi_edge) are changed at the same time depending on (n1’, n2’); so, it is worth

to decrease (n1’, n2’) to decrease the variables; so, IT’ and CT’ can be increased with

small step in LP. However, when (n1’, n2’) is changed, the half band gap of the mth

subband (Em,0) in CNT is also changed [1][2][5]. In [1][2][5], doping level in a CNT

is represented by Fermi level (Ef) and it is assumed that Ef is above the first

semiconducting subband but does not exceed the third semiconducting subband such

as E1,0 < Ef < E2,0 or E2,0 < Ef < E3,0. When the doping level is 0.8% (as default value

in [1][2][5]), Ef is 0.6 eV . Table 2 shows the value of E1,0, E2,0, and E3,0 depending

on (n1’,n2’). From these values, it can be found that when (n1’,n2’) is less than (10,0),

Ef cannot be between E1,0 and E2,0 or E2,0 and E3,0. Therefore, in this paper, it is

assumed that the least chirality is (10,0). Table 2 also shows the value of Isemi_middle,

80

Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge when chirality is changed from (19,0) to (10,0)

(It is assumed that Ef’=0.6eV, and s’=3.812nm). Note that throughout this

manuscript, when chirality is changed, only n1 is changed and n2 is fixed to 0

(chirality is changed in the simplest way) to evaluate the relation between the

performance and chiarality. When n1 is changed, n1 cannot be changed with fixed

step (linearly) because, in (n1,n2), CNT is metallic if n1 = n2 or n1 - n2 = 3i where i is

integer and only semiconducting CNT is considered in this paper.

When a CNTFET is unevenly defective (Figure 4.4 (a)) with N=9 and NCD=1,

NCCD is 9 and whole PCD is written in Table 4.3 (In this case, it is assumed that

Wg=32nm, (n1,n2)=(19,0), and s=3.812nm). By utilizing the values of variables

(Isemi_middle, Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge) in Table 4.2 (when (n1’,n2’) is

(19,0)), LP is performed and the simulation results are written in Table 4.3. Table 4.3

shows that N’ is not changed when PCD is changed. This means that, when (n1’, n2’)

is (19,0), it is hard to represent the change of IT and CT because the variables

(Isemi_middle, Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge) are not small enough to represent

it. Therefore, it is worth to utilize various (n1’,n2’) such as (19,0), (16,0), (13,0) and

(10,0). Moreover, as mentioned above, when CNTs unevenly positioned, NCD can be

changed and various PCD can exist (IT and CT can be changed severely). Therefore, to

evaluate the unevenly positioned CNTs precisely, in this paper, LP is performed with

various (n1’, n2’) (Figure 4.6 – Figure 4.11).

81

Table 4.2: Variables (Isemi_middle, Isemi_edge, Cgc_middle, and Cgc_edge) and semiconducting subbands (E1,0, E2,0, and E3,0) vs. chirality ((n1’,n2’))

(n1’,n2’) Isemi_middle

(uA) Isemi_edge

(uA) Cgc_middle (aF/um)

Cgc_edge (aF/um) E1,0 (eV) E2,0 (eV) E3,0 (eV)

(19,0) 9.529 11.771 151.433 229.400 0.2895 0.5791 1.1582(16,0) 6.825 8.471 145.963 214.357 0.3438 0.6877 1.3753(13,0) 5.058 6.758 140.220 198.887 0.4232 0.8463 1.6927(10,0) 2.367 3.124 133.681 182.434 0.5501 1.1003 2.2005(9,0) N/A N/A N/A N/A 0.6113 1.2225 2.4450

Table 4.3: The position of CNT defects (PCD), the required number of CNTs (N’), gate width (Wg’), errors between two models (Ei, and Ec) when the number of CNT defects (NCD) is 1, chirality ((n1’, n2’)) is (19,0), pitch (s’) is 3.812nm, and gate width (Wg) is 32nm

Case Number PCD N’ Wg’ (nm) EI (%) EC (%)

1 0 1 1 1 1 1 1 1 1 8 28.188 0.000 2.337 2 1 0 1 1 1 1 1 1 1 8 28.188 1.913 6.213 3 1 1 0 1 1 1 1 1 1 8 28.188 2.399 5.445 4 1 1 1 0 1 1 1 1 1 8 28.188 2.399 5.445 5 1 1 1 1 0 1 1 1 1 8 28.188 2.399 5.445 6 1 1 1 1 1 0 1 1 1 8 28.188 2.399 5.445 7 1 1 1 1 1 1 0 1 1 8 28.188 2.399 5.445 8 1 1 1 1 1 1 1 0 1 8 28.188 1.913 6.213 9 1 1 1 1 1 1 1 1 0 8 28.188 0.000 2.337

Avg. 8 28.188 1.758 4.925 Largest 8 28.188 2.399 6.213 Least 8 28.188 0.000 2.337

82

0 1 2 3 4 5 6

4

6

8

10

12

N'

NCD

N'_Avg_(19_0) N'_Larget_(19_0) N'_Least_(19_0) N'_Avg_(16_0) N'_Larget_(16_0) N'_Least_(16_0) N'_Avg_(13_0) N'_Larget_(13_0) N'_Least_(13_0) N'_Avg_(10_0) N'_Larget_(10_0) N'_Least_(10_0)

Figure 4.6: Average, largest, and least values for the required number of CNTs (N’) vs. chirality ((n1’, n2’)) and the number of CNT defects (NCD)

0 1 2 3 4 5 6

4

5

6

7

8

9

10

11

N'

NCD

N'_Avg_(19_0) N'_Avg_(16_0) N'_Avg_(13_0) N'_Avg_(10_0)

Figure 4.7: Average values for the required number of CNTs (N’) vs. chirality ((n1’, n2’)) and the number of CNT defects (NCD)

83

0 1 2 3 4 5 610

15

20

25

30

35

40

Wg' (

nm)

NCD

Wg_Avg_(19_0) Wg_Largest_(19_0) Wg_Least_(19_0) Wg_Avg_(16_0) Wg_Largest_(16_0) Wg_Least_(16_0) Wg_Avg_(13_0) Wg_Largest_(13_0) Wg_Least_(13_0) Wg_Avg_(10_0) Wg_Largest_(10_0) Wg_Least_(10_0)

Figure 4.8: Average, largest, and least values for the required gate width (Wg’) vs. chirality ((n1’, n2’)) and the number of CNT defects (NCD)

0 1 2 3 4 5 6

0

10

20

30

40

50

60

70

80

EI (%

)

NCD

E_I_Avg_(19_0) E_I_Largest_(19_0) E_I_Least_(19_0) E_I_Avg_(16_0) E_I_Largest_(16_0) E_I_Least_(16_0) E_I_Avg_(13_0) E_I_Largest_(13_0) E_I_Least_(13_0) E_I_Avg_(10_0) E_I_Largest_(10_0) E_I_Least_(10_0)

Figure 4.9: Average, largest, and least values for the error between IT and IT’ (EI) vs. chirality ((n1’, n2’)) and the number of CNT defects (NCD)

84

0 1 2 3 4 5 6

0

10

20

30

40

EC (%

)

NCD

E_C_Avg_(19_0) E_C_Largest_(19_0) E_C_Least_(19_0) E_C_Avg_(16_0) E_C_Largest_(16_0) E_C_Least_(16_0) E_C_Avg_(13_0) E_C_Largest_(13_0) E_C_Least_(13_0) E_C_Avg_(10_0) E_C_Largest_(10_0) E_C_Least_(10_0)

Figure 4.10: Average, largest, and least values for the error between CT and CT’ (EC) vs. chirality ((n1’, n2’)) and the number of CNT defects (NCD)

10 12 14 16 18 20

0

10

20

30

40

50

60

70

Erro

r (%

)

n1'

E_I_Avg E_I_Largest E_I_Least E_C_Avg E_C_Largest E_C_Least

Figure 4.11: Average, largest, and least values for the error between IT and IT’ (EI) and between CT and CT’ (EC) vs. chiralityi n1’

85

Figure 4.6 shows the simulation results of LP when NCD is changed from 0 to 6

and various (n1’, n2’) is utilized. Figure 4.6 shows that the required N’ generally

decreases as NCD increases because IT and CT decrease as NCD increases. The average

values from Figure 8 are shown in Figure 4.7. In Figure 4.7, as (n1’, n2’) decreases,

more N’ is required to represent IT and CT because when (n1’, n2’) decreases, the

values of variables (Isemi_middle, Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge) decrease.

However, in Figure 4.7, even though (n1’, n2’) is changed with somehow big

difference, overall N’ is not increased comparing to the change of (n1’, n2’) (this will

be discussed later). The required gate width (Wg’) to represent CT also can be

calculated from LP as shown in Figure 4.8. The values in Figure 10 are very similar

with those in Figure 4.6 because Wg’ is changed linearly as N’ is changed when s’

and d’ is fixed as written in (5). EI and EC depending on (n1’, n2’) and NCD are also

shown in Figure 4.9 and Figure 4.10 respectively. Figure 4.9 shows that when (n1’,

n2’) is (19,0), EI increases as NCD increases. This means that it is hard to represent the

change of IT and CT when (n1, n2) and (n1’, n2’) are same (This result shows the

consistency with the result in Table 4.3). As mentioned before by reducing (n1’, n2’),

the values of variables (Isemi_middle, Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge) can be

decreased; so, when (n1’, n2’) is smaller than (19,0), EI is not increased any longer as

NCD is increased.

However, as (n1’, n2’) decreases (and NCD is fixed), the values of EI (in Figure 4.9)

increases exponentially, but the values of EC (in Figure 4.10) are not almost changed

and overall values are much smaller comparing to the values of EI. To check this

86

phenomenon, EI (in Figure 4.9) and EC (in Figure 4.10) are redrawn in Figure 4.11

depending on n1’ (all values are re-calculated including whole NCD). As discussed

previously, in Table 4.2, the values of variables (Isemi_middle, Isemi_edge, Cgc_semi_middle,

and Cgc_semi_edge) decrease at the same time as (n1’, n2’) decreases. However,

Isemi_middle is decreased about 599.53 %, but Cgc_middle is decreased 25.747 % (Isemi_edge

and Cgc_semi_edge are not considered because, when N’ >3, IT’ and CT’ are increased

based on Isemi_middle and Cgc_middle). This means that the value of Isemi_middle is decreased

too quickly comparing to the decrease of Cgc_middle when (n1’, n2’) decreases.

Therefore, when N’ is increased in LP, CT’ in (4) can be increased more quickly than

IT’ in (3); so, LP for capacitance ((b) in LP) finds optimal value before LP for current

((a) in LP) find optimal value. This also can explain the reason why N’ (in Figure 4.7)

cannot be increased further and EI (in Figure 4.9) is increased exponentially as (n1’,

n2’) decreases. Therefore, new methodology to control only variables related to the

current (Isemi_middle and Isemi_edge) is necessary.

4.3.2 Doping Level

One of methodologies to change Isemi_middle and Isemi_edge without changing

Cgc_semi_middle, and Cgc_semi_edge is doping level (Ef’). When doping level of source and

drain regions in a CNTFET is changed, the current in each CNT can be changed, but

this does not change gate capacitance [1][2][15]. In [15], Ef’ is increased up to 0.75

eV (source/drain is doped up to 1.3%); so, this paper also change Ef’ from 0.6 eV to

0.75 eV for the consistency with [15]. Figure 4.12 shows that when chirality n1 is

87

decreased to (16,0) (Ef is fixed to 0.6 eV), current (Isemi_middle and Isemi_edge) and gate

capacitance (Cgc_middle and Cgc_edge) are decreased at the same time. At this point, as

shown in Figure 4.11, when chirality is smaller than (16,0), Ec is not decreased any

longer. Therefore, when chirality is (16,0), to increase only Isemi_middle and Isemi_edge ,

chirality is not decreased further and Ef is increased up to 0.75eV. As shown in

Figure 4.12, when chirality is fixed to (16,0) and Ef is increased, only Isemi_middle and

Isemi_edge increase. With these variables (Isemi_middle, Isemi_edge, Cgc_semi_middle, and

Cgc_semi_edge), EI and EC are calculated again using LP (Figure 4.13). Figure 4.11

shows that, when Ef’ is increased, EI decreases and EC increases because only

Isemi_middle and Isemi_edge increase. When EI and EC are considered at the same time in

Figure 15, it can be found that the smallest EI and EC (7.933% and 6.258%) can be

achieved when Ef’ is 0.675eV. This means that the change of IT and CT caused by

uneven defective CNTs (chirality ((n1, n2)) is (19,0) and NCD is changed from 0 to 6)

can be represented by evenly positioned CNTs with less than 8% errors in average.

These proposed methodologies can also be applied to various chirality ((n1,n2) in

Figure 4.4(a)) such as (16,0), (17,0), (20,0), and (22,0) and simulation results are

written in Table 4.4. Table 4.4 shows that, as (n1,n2) is increased, (n1’,n2’) and Ef’ are

also increased because when (n1,n2) is increased IT and CT are increased. As

mentioned before, when CNTs are unevenly positioned and N is changed from 3 to 9,

the NCCD is 466. So, 466 times simulation iteration is required in running MATLAB-

based CNTFET model. However, the found parameters ((n1’,n2’), s’, Ef’, and N’) is

for HSPICE-based model and, in the model, it is assumed that whole CNTs are

88

evenly positioned (with fixed pitch (s’), 3.812 nm); so, the number of PCD is only 7.

This means that when HSPICE simulation is performed with those parameters, only

7 times simulation iteration is required to represent the change of IT and CT. In this

paper, the Ratio of Simulation Iteration between two models is denoted by RSI and

the value is 66.429 for each chirality as written in Table 4.4. Table 4.4 also shows

that even though (n1,n2) and NCD is changed severely, the proposed LP can find the

required parameters with less than 9% errors.

(19,0)0.6

(17,0)0.6

(16,0)0.6

(16,0)0.625

(16,0)0.65

(16,0)0.675

(16,0)0.7

(16,0)0.725

(16,0)0.75

140

160

180

200

220

240 Cgc_middle Cgc_edge

Cap

acita

nce

(aF/

um)

(n1',n2') andEf (eV)

7

8

9

10

11

12 I_semi_middle I_semi_edge

Dra

in C

urre

nt (u

A)

Figure 4.12: Variables for linear programming (Isemi_middle, Isemi_edge, Cgc_middle, and Cgc_edge) vs. chirality((n1’, n2’)) and doping level (Ef’)

89

0.600 0.625 0.650 0.675 0.700 0.725 0.7500

2

4

6

8

10

12

14

16

18

20

Erro

r (%

)

Doping Level (Ef (eV))


Figure 4.13: Average, largest, and least values for the error between IT and IT’ (EI) and between CT and CT’ (EC) vs. doping level (Ef’) when chirality ((n1’, n2’)) is (16,0)

Table 4.4: Parameters ((n1’,n2’), s’, Ef’, N’) for linear programming, errors (Ei and Ec), and ratio of simulation iteration (RSI) depending on chirality ((n1, n2)) when the number of CNT defects (NCD) is changed from 3 to 9

(n1,n2) N (n1’,n2’) s’ (nm) Ef’(eV) N’ EI (%) EC (%) RSI (x)(22,0) 3 – 9 (17,0) 3.812 0.675 4 - 10 7.109 7.019 66.429(20,0) 3 – 9 (16,0) 3.812 0.7 4 – 10 7.681 6.446 66.429(19,0) 3 – 9 (16,0) 3.812 0.675 4 – 10 7.933 6.258 66.429(17,0) 3 – 9 (13,0) 3.812 0.75 4 – 10 8.982 6.131 66.429(16,0) 3 – 9 (10,0) 3.812 0.7 4 – 10 6.693 7.210 66.429

4.3.3 Pitch

In previous sections, when running LP, s’ is fixed to 3.812 nm. When s’ is

changed, Isemi_middle, Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge also can be changed at the

same time [1][2]. Therefore, it is worth to check whether the adjustment of s’ can

90

make EI and EC in Table 4.4 further reduced or not. The definition of pitch (s and s’)

is distance between the center of adjacent CNTs as shown in Figure 4.4. Therefore,

when s’ is decreased, s’ should be bigger than the twice d’. To determined the range

of pitch, the d’ depending on (n1’,n2’), the twice d’ (2×d’), and possible s’ are

calculated and written in Table 4.5. When s’ is reduced in Table 4.5, it is assumed

that s’ is reduced by 0.5 (If the step is smaller than 0.5, it is hard to find change in the

variables (Isemi_middle, Isemi_edge, Cgc_semi_middle, and Cgc_semi_edge)).

Figure 4.14 shows the change of the variables when (n1’,n2’) = (16,0) and (n1’,n2’)

= (10,0) (The case of (n1’,n2’) = (13,0) is not considered because there is only one

more step in s’ comparing to the case of (n1’,n2’) = (16,0); so, it is hard to find the

effect of s’). In Figure 4.14, it can be found that when (n1’,n2’) = (16,0) (and (n1’,n2’)

= (10,0)), Isemi_middle and Cgc_semi_middle are reduced to 15,329% and 17.809% (42.453%

and 38.765%) respectively. This means that Isemi_middle and Cgc_semi_middle are reduced

with almost same rate. Therefore, when (n1’,n2’) = (16, 0), EI can be further reduced,

but EC is a little increased as shown in Figure 4.15. In previous section, EI can be

reduced by increasing Ef. Therefore, only reduction of EI cannot make better result

and the increase of EC make the existing result worse. Otherwise, when (n1’,n2’) =

(10,0), as shown in Figure 4.11, EI has big error. However, by reducing s’, this big

error cannot be reduced as shown in Figure 4.15, because Isemi_middle and Cgc_semi_middle

are reduced with almost same rate. Therefore, it can be found that the change of s’

cannot make the previous results (which is obtained by optimizing chirality and

91

doping level) better; so, the change of s’ will not be considered in this paper any

longer.

Table 4.5: Diameter(d’), twice diameter (2×d’), and possible pitch (s’) depending on chirality ((n1’,n2’))

(n1’,n2’) d’ (nm) 2×d’ (nm) s’ (nm)

(16,0) 1.268 2.536 3.812 3.5 3

(13,0) 1.030 2.061

3.812 3.5 3

2.5

(10,0) 0.793 1.585

3.812 3.5 3 2.5 2

Figure 4.14.: Variables for linear programming (Isemi_middle, Isemi_edge, Cgc_middle, and Cgc_edge) vs. chirality ((n1’, n2’)) and pitch (s’)

(16,0) 3.812

(16,0)3.5

(16,0)3

(10,0)3.812

(10,0)3.5

(10,0)3.0

(10,0)2.5

(10,0)2.0

80

100

120

140

160

180

200

220 Cgc_middle Cgc_edge

Cap

acita

nce

(aF/

um)

(n1',n2') and s' (nm)

123456789 I_semi_middle

I_semi_edge

Dra

in C

urre

nt (u

A)

92

4.4. HSPICE Simulation

Table 4.4 in previous section shows that, by using LP, parameters ((n1’,n2’), s’, Ef’,

N’, and Wg’), which can be used in HSPICE-based CNTFET model and which can

represent the change of IT and CT caused by unevenly positioned CNTs, can be

achieved. By using the methodologies, in this section, the performance of CNTFET

is evaluated in HSPICE simulation. When a metric, which is independent of

technology and can be used to evaluate the circuit level performance (so, it can be

utilized to extrapolate future technology), is required, the delay and energy of driving

a normalized load (fan-out of 4, FO4) is generally utilized [15][25]. A “FO4 delay

and energy” is the delay and energy for one stage in an inverter chain as shown in

Figure 4.16. Figure 4.16 shows that each inverter in the inverter chain drives a

capacitive load (fan-out) that is 4 times larger than its input capacitance. By utilizing

this circuit, previously in [15], the performance of CNTFET is assessed (considering

undeposited CNTs and chirality variation probabilistically) to compare its

performance to that of MOSFET using HSPICE-based CNTFET model. However, in

the simulation, it is assumed that CNTs are evenly positioned.

To evaluate the effect of uneven space between CNTs fairly and deterministically

in HSPICE simulation, the simulation is performed considering the conditions (five

stage FO4 inverter chain, 8% or 32% undeposited CNTs, and 1.5±0.3 nm diameter

variation) given in [15]. To represent 8% and 32% undeposited CNTs

deterministically, in this paper, 8% (and 32%) undeposited CNTs is represented by

93

NCD = 1 (and NCD = 3) because N is 9. In the change of diameter, as explained before,

diameter of CNT is determined by chirality and, in this paper, the performance is

evaluated in chirality aspect (only n1 is changed). Wider variation in chirality (from

(16,0) to (22,0)) comparing that of [15] is chosen to discuss the relation between

chirality and performance (This will be discussed below). For example, in [15],

1.5±0.3 nm diameter variation is considered, but when chirality is (16,0), (17,0),

(19,0), (20,0), and (22,0), the diameter is 1.269nm, 1.348 nm, 1.507 nm, 1.586 nm,

and 1.745nm.

3.0 3.2 3.4 3.6 3.8

0

2

4

6

8

10

12

14

16

Erro

r (%

)

s' (nm)

2.0 2.4 2.8 3.2 3.6 4.0

0

10

20

30

40

50

60

70( n1',n2' )=(10,0)( n1',n2' )=(16,0)


Erro

r (%

)

s' (nm)

Figure 4.15:. Average, largest, and least values for the error between IT and IT’ (EI) and between CT and CT’ (EC) vs. pitch (s’) when (n1’, n2’) = (16,0) and (n1’, n2’) = (10,0)

94

Figure 4.16: Five stage FO4 inverter chain Table 4.6 shows that, delay and energy values of MOSFET, non-defective

CNTFET, and even defective CNTFET are almost same as the values in [15]. This

means that the test circuit is properly designed. The parameters ((n1’, n2’), s’, Ef’, N’,

and Wg’) are calculated under the given conditions (Table 4.7). When NCD is 3 and

(n1, n2) is (16,0), (19, 0), and (20,0) in Table 8, N’ is changed from 8 to 9 (or from 7

to 8); so, these two values are used in HSPICE simulation and two kind results are

written in Table 4.6. HSPICE simulation results in Table 4.6 shows that, when

chirality is changed with same step (e.g. ‘from (19,0) to (20,0)’ and ‘from (16,0) to

(17,0)’), the performance (delay and energy) is not changed with fixed step because

the relation between the performance and chirality is not simply linear [1][2]. Table

4.6 also shows that when CNTs are unevenly spaced, the delay and energy can be

increased 19.712% and 6.328% more comparing to the delay and energy values of

evenly spaced CNTs. In Table 8, EI and EC are smaller than EI and EC in Table 4.4

because parameters in Table 5 cover wider range of NCD (from 1 to 6). Table 8 also

shows that about 33.9 times smaller RSI can be achieved considering whole chirality

and undeposited CNTs.

95

4.5 Simulation Time and Memory

In previous chapter, it is found that, the uneven space between CNTs can be

evaluated with about 33.9 times smaller simulation runs in HSPCIE. However, to

achieve the results, additional MATLAB simulation to find proper parameters

((n1’,n2’), s’, Ef’, N’, and Wg’) is required. As shown in Figure 4.12, when (n1,n2) is

(19,0) and NCD is 1 (8%), 9 times MATLAB simulation is required. For example,

(n1’,n2’) should be changed from (19,0) to (16,0) first. Then Ef’ should be changed

from 0.6eV to 0.75eV by 0.25eV. Due to the various numbers of simulations runs in

the different simulation tools, it is hard to expect the total required simulation time

and memory usage from the given parameters such as (n1,n2) and NCD. Therefore, it

is worth to measure the simulation time and memory usage for the each simulation to

check that the proposed method is computationally feasible for common use.

The simulation time and memory usage for each parameter change are written in

Table 4.8 (when (n1,n2) is (19,0)). As mentioned above, 9 times parameter change is

required when NCD is 1 (8%). In this case, Table 4.8 shows that it talks about 30

seconds and 10 Mbytes memory space for each parameter change; so, total 268.209

seconds simulation time and average 11.023 Mbytes memory usage are required for

the ‘NCD is 1’ case. When NCD is 3 (32%), 18 times parameter change is required and,

for the each parameter change, about 180 seconds simulation time is required. This is

about 6 times more simulation time comparing to the ‘NCD is 1’ case because, when

NCD is 3, about 9 times more PCD exists. Therefore, in total simulation time, the ‘NCD

96

is 3’ case requires 3290.715 seconds. Regarding the memory usage, the ‘NCD is 3’

case require almost same memory usage (14.132 Mbytes) as the ‘NCD is 1’ case

(11.023 Mbytes), because, for the simulation, same functions and equations are

utilized just with different input values (parameters).

Table 4.6: Delay, energy, and ratios in five stage fan-out of four inverter chain depending on chirality ((n1, n2)) and the number of CNT Defects (NCD)

(n1, n2) NCD Delay

(ps) Energy (uW)

Delay Ratio

Energy Ratio # %

MOSFET N/A N/A 15.140 27.600 0 0

Non- Defective CNTFET

(22,0)

0 and 0 %

2.430 11.770 6.230 2.345 (20,0) 2.713 11.620 5.581 2.375 (19,0) 2.980 11.460 5.081 2.408 (17,0) 3.929 11.170 3.853 2.471 (16,0) 4.363 10.890 3.470 2.534

Even Defective CNTFET

[13]

(22,0) 1 8% 2.477 10.760 6.112 2.565 3 32% 2.608 8.505 5.805 3.245

(20,0) 1 8% 2.782 10.480 5.442 2.634 3 32% 2.931 8.308 5.165 3.322

(19,0) 1 8% 3.031 10.370 4.995 2.662 3 32% 3.184 8.247 4.755 3.347

(17,0) 1 8% 4.010 10.130 3.776 2.725 3 32% 4.240 8.010 3.571 3.446

(16,0) 1 8% 4.446 9.878 3.405 2.794 3 32% 4.705 7.880 3.218 3.503

Uneven Defective CNTFET

(22,0) 1 8% 2.831 11.450 5.348 2.410 3 32% 3.209 9.804 4.718 2.815

(20,0) 1 8% 3.468 10.860 4.366 2.541

3 32% 3.549 9.712 4.266 2.842 3.537 8.431 4.280 3.274

(19,0) 1 8% 3.513 10.860 4.310 2.541

3 32% 4.362 10.530 3.471 2.621 4.348 9.342 3.482 2.954

(17,0) 1 8% 4.599 10.540 3.292 2.619 3 32% 4.340 8.438 3.488 3.271

(16,0) 1 8% 5.062 10.370 2.991 2.662

3 32% 5.380 9.403 2.814 2.935 5.359 8.213 2.825 3.361

97

When (n1,n2) are changed from (16,0) to (22,0), the total number of parameter

change, simulation time, and memory usage are also analyzed and the results are

written on Table 4.9. Table 4.9 shows that total simulation time is almost linearly

changed depending on the number of parameter change because, even though (n1,n2)

is changed, the simulation time for each parameter change is almost fixed to about 30

(and 180) seconds when NCD is 1 (and 3). However, it is hard to find the relationship

among (n1,n2), NCD, and the number of parameter change because in the proposed

method, the parameters ((n1’,n2’) and Ef’) keep changing until EI and EC are not

reduced any longer. From Table 4.9, it can be found that it takes 891.627 seconds

simulation time on average (3290.715 seconds (about 55 minutes) maximum) and

12.063 Mbytes memory usage on average to find the proper values of parameters

((n1’,n2’), s’, Ef’, N’, and Wg’) when (n1,n2) and NCD are changed.

Table 4.7: Parameters ((n1’, n2’), s’, Ef’, N’, Wg’, Ei, and Ec ) for linear programming depending on chirality ((n1, n2)) when the number of CNT defects (NCD) is 1 or 3 (8% or 32%)

(n1, n2) NCD (n1’,n2’)

Ef’ (eV)

N’ EI (%)

EC (%)

RSI (x)# % Avg. Largest Least

(22,0) 1 8% (19,0) 0.675 9 9 9 0.763 2.092 93 32% (17,0) 0.725 8 8 8 1.716 3.507 84

(20,0) 1 8% (16,0) 0.825 9 9 9 5.792 1 93 32% (16,0) 0.725 7.952 8 7 1.845 3.743 42

(19,0) 1 8% (16,0) 0.75 9 9 9 1.031 1.961 93 32% (14,0) 0.95 8.083 9 8 2.295 3.539 42

(17,0) 1 8% (14,0) 0.8 9 9 9 2.544 1.782 93 32% (16,0) 0.6 7 7 7 1.921 4.784 84

(16,0) 1 8% (13,0) 0.9 9 9 9 1.628 1.654 93 32% (14,0) 0.6 7.726 8 7 3.741 4.371 42

98

Table 4.8: The required time and memory for MATLAB simulation when chirality ((n1,n2)) is (19,0) and the number of CNT defects (NCD) is 1 or 3 (8% or 32%)

NCD 1 and 8% NCD 3 and 32% Parameters Time

(s) Memory(Mbytes)

Parameters Time (s)

Memory(Mbytes)(n1’,n2’) Ef’ (n1’,n2’) Ef’

(19,0) 0.600 29.772 11.892 (19,0) 0.600 182.6493 12.192 (17,0) 0.600 29.663 11.296 (17,0) 0.600 183.0544 15.560 (16,0) 0.600 29.599 10.640 (16,0) 0.600 182.2334 15.616 (16,0) 0.625 29.816 11.768 (14,0) 0.600 181.9851 13.032 (16,0) 0.650 29.817 10.964 (14,0) 0.625 182.2665 11.952 (16,0) 0.675 29.804 9.464 (14,0) 0.650 183.0552 14.004 (16,0) 0.700 30.055 9.372 (14,0) 0.675 182.9719 15.176 (16,0) 0.725 29.764 10.224 (14,0) 0.700 181.9079 13.392 (16,0) 0.750 29.919 13.584 (14,0) 0.725 182.7123 13.984

(14,0) 0.750 182.0131 12.980 (14,0) 0.775 182.4864 14.712 (14,0) 0.800 182.3322 12.548 (14,0) 0.825 183.5845 15.684 (14,0) 0.850 183.5998 12.320 (14,0) 0.875 183.9065 14.556 (14,0) 0.900 183.168 14.788 (14,0) 0.925 183.2451 15.940 (14,0) 0.950 183.5437 15.936

Total Time

(s) 268.209

Avg. Memory (Mbytes)

11.023 TotalTime

(s) 3290.715

Avg. Memory (Mbytes)

14.132

As explained before, after the proper values of parameters are found by

MATLAB simulation, the values can be used to evaluate the effect of uneven space

between CNTs in HSPICE simulation. The simulation time and memory usage for

the HSPICE simulation (five stage FO4 inverter chain) are also measured and written

in Table 4.10. Table 4.10 shows that, in CNTFET HSPICE, simulation requires

about 14 times (27 times) more simulation time (memory usage) is required

99

comparing to MOSFET HSPICE simulation. However, in CNTFET HSPICE

simulation, there is not big difference in simulation time and memory usage among

non-defective, even defective and uneven defective CNTFET because, depending on

the type of defects, different parameters are used in the simulation and those

parameters do not require additional equations or calculation.

\

Table 4.9: The required step, time, and memory for MATLAB simulation depending on various chirality ((n1,n2)) when the number of CNT defects (NCD) is 1 or 3 (8% or 32%)

(n1, n2) NCD Number of

Parameter Change

Time (s)

Memory (Mbytes) # %

(22,0) 1 8% 6 178.364 11.607 3 32% 9 1635.014 15.158

(20,0) 1 8% 13 387.689 9.813 3 32% 9 1648.492 13.774

(19,0) 1 8% 9 268.209 11.023 3 32% 18 3290.715 14.132

(17,0) 1 8% 11 328.268 10.193 3 32% 2 365.759 12.086

(16,0) 1 8% 15 447.951 10.038 3 32% 2 365.810 12.810

Average 9.400 891.627 (14.860 min) 12.063

100

Table 4.10: Time and memory for HSPICE simulation depending on chirality ((n1, n2)) when the number of CNT defects (NCD) is 1 or 3 (8% or 32%)

(n1, n2) NCD Time

(s) Memory (Kbytes) # %

MOSFET N/A N/A 0.66 0.189

Non-Defective CNTFET

(22,0)

0 and 0 %

8.44 5.152 (20,0) 8.51 5.152 (19,0) 8.72 5.152 (17,0) 9.03 5.152 (16,0) 8.83 5.152

Even Defective CNTFET [13]

(22,0) 1 8% 8.41 5.198 3 32% 8.06 5.198

(20,0) 1 8% 8.30 5.198 3 32% 8.56 5.198

(19,0) 1 8% 8.72 5.198 3 32% 8.64 5.198

(17,0) 1 8% 8.95 5.198 3 32% 8.53 5.198

(16,0) 1 8% 8.91 5.198 3 32% 8.73 5.198

Uneven Defective CNTFET

(22,0) 1 8% 8.62 5.198 3 32% 8.73 5.198

(20,0) 1 8% 8.77 5.198

3 32% 8.75 5.198 8.86 5.198

(19,0) 1 8% 11.09 5.198

3 32% 13.19 5.198 12.33 5.198

(17,0) 1 8% 9.75 5.198 3 32% 8.92 5.198

(16,0) 1 8% 8.56 5.198

3 32% 8.92 5.198 8.89 5.198

101

4.6. Conclusion

The Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most

promising devices among emerging technologies to extend and/or complement the

traditional Si MOSFET. One of the defect types that can occur when fabricating a

CNTFET is the change of chirality and the absence of some CNTs. As result of these

types of defects, a CNTFET will show a change in operational characteristics

because drain current and gate capacitance will be affected due to the lower number

of CNTs (with various chirality) and the uneven space between CNTs.

HSPICE-based CNTFET model is widely used to design CNTFET circuit, but it

does not support uneven space between CNTs. To evaluate the uneven space effect,

MATLAB-based CNTFET model is proposed and it is shown that delay is increased

and deviated severely depending on the number and the position of unevenly

positioned CNTs in a CNTFET. However, the effect of uneven space cannot be

evaluated in circuit level (HSPICE) simulation because the proposed model is

MATLAB based and highly iterative simulation is required to consider whole

position of unevenly (and evenly) positioned CNTs depending on various number of

undeposited CNTs in a CNTFET.

This paper has presented the methodology to acquire the parameters such as

number, pitch, doping level, and chirality of CNTs which can be utilized in HSPICE

simulation and represent the uneven defective CNTFET. When the pitch and

chirality of CNTs are fixed, in a CNTFET, current and gate capacitance can be

102

increased linearly. Therefore, when an uneven defective CNTFET is given, its

current and gate capacitance are calculated using previously proposed MATLAB-

based model first. Then, current and gate capacitance are increased linearly using

linear programming until those values are almost same as the calculated current and

gate capacitance of the uneven defective CNTFET. The presented analysis shows

that when only chirality is changed in the linear programming, the linear

programming for capacitance finds optimal value before the linear programming for

current finds optimal value because the variable related to current is decreased too

quickly comparing to the variable related to capacitance when chirality is decreased;

so, current error is increased. To reduce the current related variables, in this paper,

the method to control doping level is suggested. By optimizing chirality and doping

level at the same time, the desired parameters can be achieved and those can

represent the effect of uneven defective CNTFET under 9% errors even though the

number, the position, and the chirality of CNT defects are severely changed. With

the achieved parameters, the effect of uneven space between CNTs can be assessed

in the five stage FO4 inverter chain and the number of simulation iteration can be

decreased. Simulation results show that the proposed method is computationally

feasible (the required simulation time and memory are about 15 minutes and 12

Mbytes (about 10 seconds and 5 Mbytes) respectively in MATLAB (HSPICE)

simulation) and unevenly spaced CNTs cause 19.712% and 6.328% more delay and

energy comparing to evenly spaced CNTs and linear programming method can

reduce about 33.9 times simulation runs.

103

Chapter 5 Design and Comparative Analysis of a CNTFET-based Ternary SRAM

Recently, as the number of memory-intensive application is increased and

portable electronic devices are required to provide low power consumption, the

demand for large and low power cache has been increased. To increase the cache (or

to store or access more information) and operate it with low power, current digital

system, which uses MOSFET technology and binary logic (only two levels of logic

(0 or 1, 0V or Vdd), requires the significant portion of total chip area and additional

device/circuit/architectural level low power techniques. Three valued, or ternary,

logic which offers three levels of logic has attracted increasing attention due to its

advantages over binary logic in digital systems. Ternary logic can transmit (or store)

104

more information on a given lines (or with given register length) and it also can

decrease the number of operations for a specific mathematical function and increase

the parallel and serial communication rate; hence, the complexity of interconnect and

chip area can be decreased with ternary logic. This means that ternary logic can

achieve simplicity and energy efficiency in digital system design. One of best way to

implement this ternary logic is multi-threshold design method. However, to

implement the multi-threshold in traditional MOSFET, additional bias voltages to the

base or the bulk terminal of the transistor is required. This can require additional

power controller (or voltage divider) and the complexity of power grid can be

increased [21][22][23][24].

As discussed in previous chapter, the Carbon NanoTube Field Effect Transistor

(CNTFET) is one of the most promising emerging technologies to extend and

complement silicon MOSFET; this is due to its excellent performance characteristics

(13 times CV/I improvement over a bulk n-type MOSFET at a 32 nm feature size)

and similarity in operational principles and device structure [1][2]. In CNTFET, the

threshold voltage of CNTFET is determined by the diameter of CNTs in a CNTFET;

so, multi-threshold voltage can be implemented without additional voltage bias.

Therefore, extensive researches [21][22][38][50][51][52] on the design and

implementation of ternary logic using CNTFET have been performed and suggested

ternary logic family (e.g. inverters, NAND, and NOR).

105

Based on the previously proposed Standard Ternary Inverter (STI) [38], in this

paper, four methodologies to design ternary CNTFET SRAM is proposed. First, the

method to utilize the traditional transistor sizing methods for binary MOSFET

SRAM cell to ternary CNTFET SRAM cell is proposed. Second, the methodology to

improve SNM is suggested. Third, the methodology to reduce power (or PDP) is

proposed. Fourth, the methodology to reduce write and read time is suggested. Even

though CNTFET does not require additional voltage bias for the base or the bulk

terminal, when 0.45V is stored on ‘q’ and ‘nq’ in the ternary CNTFET SRAM cell

(Vdd is 0.9V in this paper), additional voltage controller (or voltage divider) is still

required to make two bit lines 0.45V. This can increase the complexity of SRAM

circuit and the write (or read) operation. To make these simpler, in this paper,

another ternary CNTFET SRAM cell is proposed. By adding two more transistors, in

this ternary CNTFET SRAM cell, 0.45V can be stored on ‘q’ and ‘nq’ only by

making one bit line and a word line 0.9V (Generally, two bit lines and a word line

should be operated to store desired values in most SRAM cells).

Extensive simulations are performed to prove that two proposed ternary SRAM

cells show better performance comparing to existing binary (or ternary) MOSFET

(or CNTFET) SRAM cell. Additionally, the effect of process variation is also

evaluated considering the structure of MOSFET and CNTFET. Simulation results

show that TC SRAM has 4.193 times (2.024 times) better performance in PDP

aspect comparing to BM SRAM (BC SRAM). Another ternary CNTFET SRAM cell,

which does not require 0.45 V on two bit lines, require 3.733% more power

106

consumption comparing to the first proposed ternary CNTFET SRAM. When density

is decreased to low density (10 CNTs/um) in CNTFET SRAMs, write (read) delay

and power are increased 76.213% (0.075%) and 51.101% (4.727%) at the same time.

Otherwise, when density is increased to high density (100 CNTs/um), delay can be

decreased 25.238 % on average in CNTFET SRAMs. However, comparing to the

decrease of delay, more power (129.606%) has to be consumed; so, PDP is increased

75.621%. From these simulation results, it is found that for CNTFET SRAMs, 30

CNTs/um is proper density. When lithographic process variation is analyzed in

MOSFET and CNTFET SRAMs, simulation results show that binary MOSFET

SRAM’s write (and read) delay, power, and PDP are about 10.632 times, 41.212

times, and 32.615 times (3.931 times, 29.333 times, and 10.883 times) bigger than

other CNTFET SRAMs. This means that binary MOSFET SRAM is more sensitive

to lithographic process variation than other CNTFET SRAM cells. The simulation

results show that when the number of CNTs is decreased randomly in CNTFET

SRAMs, 42.082 times, 57.545 times, and 56.457 times (39.633 times, 330.222 times,

and 576.632 times) standard deviations for write (read) delay, power, and PDP are

increased respectively comparing to those for CNTFET SRAMs which has

lithographic variations. When the various density and process variation exists, Static

Noise Margin (SNM) is also measured. The results shows that the density causes

standard deviation for SNM less than 0.04% but, lithographic variation causes for

binary MOSFET SRAM to have 48.933 times more standard deviation in SNM than

107

those for other CNTFET SRAMs. When the number of CNTs is randomly decreased,

the standard deviation in SNM is increased 37.314 times in binary CNTFET SRAM.

5.1 Ternary Inverter

The one of most fundamental building blocks in digital systems is inverter. Three

type inverters, a negative ternary inverter (NTI), a standard ternary inverter (STI),

and a positive ternary inverter (PTI), are used in ternary system [41]. Depending on

input (denoted by x) and the type of inverter, three different output (denoted by yo, y1,

and y2) are determined as written in equation (2) and Table 1 (yo , y1, and y2 represent

the output of NTI, STI, and PTI respectively). Three logic levels such as ‘0’, ‘1’, and

‘2’ represent 0V, 0.45V, and 0.9V respectively when supply voltage is 0.9V in this

paper. From these three ternary inverters, STI will be used to construct ternary

SRAM cell.

⎭⎬⎫

⎩⎨⎧

=≠

==

−===⎭⎬⎫

⎩⎨⎧

≠=

==

2022

)(

2)(0002

)(

22

11

00

xifxif

xCy

xxxCyxifxif

xCy

(5.1)

Table 5.1: Truth table of STI, PTI, and NTI

INPUT X OUTPUT Y NTI (Y0) STI (Y1) STI (Y2)

0 2 2 2 1 0 1 2 2 0 0 0

108

5.2 Ternary CNTFET SRAM

Based on the previously proposed STI inverter [38] (Figure 4), in this paper, two

kinds Ternary CNTFET SRAM (TC SRAM) cell will be proposed. The performance

of CNTFET SRAM cell will be also compared with that of existing binary MOSFET

(and CNTFET) SRAM cell. For fair comparison, in this paper, the gate length of

whole MOSFET and CNTFET in this paper is 32 nm (minimum gate width is also

32nm), and when the gate width is determined in CNTFET circuit, general

width/length ratios (such as 0.5, 1, and 2), which is conventionally used in CMOS

circuit design, are used. The number of CNTS in a CNTFET is determined

considering pitch (In this chapter, it is assumed that the pitch is 32nm and various

pitch will be discussed later).

Figure 5.1: STI inverter ([38])

109

5.2.1 First Proposed Ternary CNTFET SRAM

In designing TC SRAM cell, previously suggested STI inverter (Figure 5.1) and

the conventional 6T SRAM cell (Figure 5.2) can be utilized as shown in Figure 6. In

Figure 5.3, for convenience of explanation, each three transistors in Figure 5.1 are

grouped together and a group number such as MN3, MN4, MP5, and MP6 is given

based on transistor name in Figure 5.2. With the group numbers and the position of

transistor in STI inverter, the name for each transistor in Figure 5.1 is given such as

MP61, MP62, MP63, MN41, MN42, and MN43. The threshold voltage of each

transistor is 0.290V, 0.423V, and 0.550V based on each chirality vector such as

(19,0), (13,0) and (10,0) respectively.

Figure 5.2: 6T SRAM cell

110

WLWL

vdd vdd

q nq

MN3 MN4

MN1 MN2

MP5 MP6

BL BLB

Figure 5.3: Grouping CNTFETs for sizing in TC SRAM cell Due to the high threshold voltages (0.423V and 0.550V) and the serial connection

of transistors in the STI inverter, it takes much longer time to read the stored value

comparing to Binary MOSFET (or CNTFET) SRAM; so, additional transistors are

required to read the stored value reliably and quickly. Two previously proposed

methodologies can be utilized; one is inserting read buffer to assist the change

voltage level Read Bit Line (RBL) and another is adding transistors to sink the RBL

charge to the ground [19][20]. First method was utilized in designing TC SRAM by

Sheng Lin [38] as shown in Figure 5.4 and second method is used and proposed in

this paper as shown in Figure 5.5. The proposed TC SRAM is named ‘first proposed

Ternary SRAM) in this paper. In Figure 5.4, the suggested method uses single-ended

read and write access mechanism for the write and read operation. The data on the

write bitline (WBL) is written into the memory cell through the write transmission

gates (MN1 and MP1) forces data. The read buffer is consists of one P-CNTFET and

111

one N-CNTFET (threshold voltage of the transistors is -0.559V and 0.559V

respectively). Before reading the stored value, Read Bit Line (RBL) is charged to

0.45V. Therefore, when the cell is storing a ‘0’ (when the cell is storing ‘2’), MN3

and MP3 are turned on and turned off (MN3 and MP3 are turned off and turned on);

so, the two values can be read through the read transmission gates (MN2 and MP2).

When the cell is storing ‘1’, both MN3 and MP3 are turned off; so, RBL remains at

0.45V. Therefore, to read the stored value in Lin’s TC SRAM cell, special sense

amplifier which can detect three voltage levels is required.

Figure 5.4: Lin’s TC SRAM cell [38] Figure 5.5 shows first proposed TC SRAM cell. The chirality vector of MN9,

MN10, MN11, and MN12 is (19,0); so, MN11 and MN12 are turned on when 0.45V

or 0.9V are stored in q or nq. Comparing with Lin’s TC SRAM cell, in the first

proposed TC SRAM cell, conventional Sense Amplifier can be utilized as shown in

Figure 5.6 When ‘out1 and out2’ is ‘0.9V and 0V’, ‘0.9V and 0.9V’, and ‘0.9V and

112

0V’, it can be found that the value of ‘0’, ‘1’, and ‘2’ is stored in TC SRAM

respectively (It is assumed that 0.9V come out when voltage difference is detected

from the two inputs of SA).

Figure 5.5: The first proposed TC SRAM cell

Figure 5.6: Sense amplifiers for TC SRAM

113

The sizing method for 6T Binary CNTFET SRAM cell (BC SRAM) is proposed

in [42]. Based on [42], in this section, the sizing methodology for TC SRAM cell is

proposed. When sizing each MOSFET in 6T SRAM cell, MN4/MN2 ratio and

MP5/MN1 ratio should be optimized [42][43]. An appropriate sizing ratio between

MN4 and MN2 is required to limit the voltage at node ‘nq’ to be lower than the

threshold voltage (Vth) such that the stored logic value does not change during the

read operation. During write operation, when the SRAM cell is required to write a

new data into the SRAM cell, the pass gate MN1 must be significantly more

conductive than the MP5: so, the voltage at node ‘q’ should be greater than Vth. To

apply this binary 6T SRAM designing method to ternary CNTFET SRAM cell, three

CNTFETs are grouped as shown in Figure 6 and the gate widths of the grouped three

transistors are changed at the same time. The voltage rise on node ‘nq’ versus

MN4/MN2 ratio and the voltage rise on node ‘q’ versus MP5/MN1 ratio are

measured as shown in Figure 5.7 and Figure 11 respectively [42][43]. Figure 10 and

Figure 5.8 show that voltage on ‘nq’ and ‘q’ of TC SRAM cell have same tendency

as those of BM SRAM cell. Then, considering Vth of 32nm MOSFET (0.160 V) and

32nm CNTFET (0.289 V which is the smallest Vth of CNTFET in TC SRAM),

MN4/MN2 ratio and MP5/MN1 ratio which can be used in Binary MOSFET SRAM

(BM SRAM), BC SRAM, and TC SRAM are achieved from Figure 5.7 and Figure

5.8. Table 5.2 shows the possible MN4/MN2 and MP5/MN1 ratio and each

transistor’s gate width (the ratio only between 0 and 3 values are discussed in this

paper).

114

0.0 0.5 1.0 1.5 2.0 2.5 3.00.0

0.1

0.2

0.3

0.4

0.5

Volta

ge R

ise

on N

ode

'nq'

MN4/MN2 Ratio

BM SRAM BC SRAM TC SRAM

Figure 5.7: MN4/MN2 ratio versus voltage rise at nq for SRAM cell

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Writ

e Vo

ltage

on

node

'q'

MP5/MN1 Ratio

BM SRAM BC SRAM TC SRAM

Figure 5.8: MP5/MN1 ratio versus voltage rise at q for SRAM cell

115

When SRAM cell is designed, SNM should be considered for static stability of

SRAM cell. The SNM is defined as the maximum value of DC noise voltage that can

be tolerated by the SRAM cell without changing the stored bit [44]. Figure 5.9 shows

graphical representation of SNM for BM (and BC) SRAM. As discussed in [45],

CNTFET has a steeper curve in the transition region due to the higher gain (which

contributes to a 22.5% improvement in noise margin). This steeper curve also

contributes to achieve bigger SNM in Figure 12.

Figure 5.10 shows Voltage Transfer Characteristics (VTC) of STI (black line)

inverter (Figure 5.1). Even though this VTC has same three different output voltage

levels from same three different input voltage levels, the SNM of this VTC has two

different SNM values as shown in Figure 5.11 (black line). This means the SRAM

cell which has this STI has different static stability depending on the stored value in

the SRAM cell. Therefore, in this paper, the middle voltage levels in the VTC of this

STI is expanded by changing chirality vector from (10,0) to (8,0) on MN32, MN42,

MP52, and MP62 in Figure 5.1 as shown in Figure 5.10 (white line). Figure 5.11

shows that this modified STI helps TC SRAM cell has four similar SNM regardless

of voltage levels (white line).

116

Table 5.2: Transistor ratio and gate width

Ratio Gate Width (nm)

MN4/MN2 MP5/MN1 MN1 MN2

MN3 MN4

MP5 MP6

BM SRAM

1.5 0.5 64 96 32 1.0 96 64 64

2.0 0.5 64 128 32 1.0 32 64 32

2.5 0.5 64 160 32 1.0 32 80 32

3.0 0.5 64 192 32 1.0 32 96 32

BC SRAM

1.0

0.5

64 64 32 1.5 64 96 32 2.0 64 128 32 2.5 64 160 32 3.0 64 192 32

TC SRAM

0.5 0.5 64 32 32 1.0 64 32 64

1.0 0.5 64 64 32 1.0 32 32 32

1.5 0.5 64 96 32 1.0 64 96 64

2.0 0.5 64 128 32 1.0 32 64 32

2.5 0.5 64 160 32 1.0 64 160 64

3.0 0.5 64 192 32 1.0 32 96 32

117

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9 BM SRAM BC SRAM

Voltage on node 'q' (V)

Vol

tage

on

node

'nq'

(V)

Figure 5.9: Voltage transfer characteristic of BM SRAM cell and BC SRAM cell for SNM

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9 STI Inverter Modified STI Inverter

Voltage X (V)

Volta

ge Y

(V)

Figure 5.10: Voltage transfer characteristic of STI inverter and modified STI inverter

118

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9 TC SRAM Modified TC SRAM

Voltage on node 'q' (V)

Vol

tage

on

node

'nq'

(V)

Figure 5.11 Voltage transfer characteristic of TC SRAM cell and modified TC SRAM cell

To use the existing BM SRAM sizing method in TC SRAM, in previous section,

the gate widths of grouped three CNTFETs are changed at the same time. In this

section, to improve the performance of TC SRAM cell (in PDP aspect), the method

of optimizing chirality of individual CNTFET in a TC SRAM is discussed (The

change of gate width and pitch for individual CNTFET will be discussed later). In a

TC SRAM, it is worth to change chirality in MN33, MN43, MP53, and MP63

because those CNTFETs are used as resistor (VTC is not almost changed). When

chirality vectors of other CNTFETs are changed, VTC is changed severely because

two transient point of VTC is determined by the chirality vectors of those CNTFET

(three voltage levels cannot be established). From simulation, it is checked that when

chirality vector ‘n’ in MN33, MN43, MP53, and MP63 is changed from 10 to 14,

there is not big change in SNM of TC SRAM. So, delay, power, and PDP are

119

measured when chirality is changed from 10 to 14 as shown in Figure 5.12. As

discussed before, delay and PDP values are different depending on the previously

stored value and newly memorized value in TC SRAM cell; so, largest, average, and

least values are drawn with upward-pointing triangle, square, and downward-

pointing triangle respectively in Figure 5.12. Delay and PDP values are also

represented by black and white symbols respectively. Figure 5.12 shows that, when

these chiralitys are increased to 14, average delay (PDP) is decreased (increased) in

2.217% (14.046%). Otherwise, when the chiralitys are decreased to 10, delay (PDP)

is increased (decreased) in 2.183% (28.269%). In an inverter, the finite slope of the

input signal causes a direct current path (short-circuit current) between VDD and

GND for a short period of time during switching (the NMOS and the PMOS

transistors are conducting simultaneously), which is main factor of dynamic power in

inverter [18]. By decrease the chirality in CNTFETs used as resistor, the short-circuit

currents can be decreased. Therefore, in this paper, chiralitys in MN33, MN43,

MP53, and MP63 are changed from 13 to 10 for better PDP.

In binary SRAM cell, there are two kinds of value change in ‘q’ and ‘nq’ such as

‘from 0.9V and 0V to 0V and 0.9V’ and ‘from 0V and 0.9V to 0.9 V and 0V’. It can

be easily found that the performance (delay, power, and PDP) in those two value

change are same because two cases are same change in ‘q’ and ‘nq’ of the binary

SRAM cell (when the structure of the cell is symmetric). Otherwise, in ternary

SRAM cell, there are six kinds of value change exist such as ‘from 0V and 0.9V to

0.45V and 0.45V’, ‘from 0.9V and 0V to 0.45V and 0.45V’, ‘from 0V and 0.9V to

120

0.9V and 0V’, ‘from 0.9V and 0V to 0V and 0.9V’, ‘from 0.45V and 0.45V to 0V

and 0.9V’ and ‘from 0.45V and 0.45V to 0.9V and 0V’. It also can be found that, in

these six cases, three cases have same performance because the proposed SRAM cell

has symmetric structure. As mentioned previously, 0, 1, and 2 represent 0V, 0.45V,

and 0.9V respectively. Therefore, binary SRAM cell has one kind of value change

such as 0 -> 2 (2 -> 0) and ternary SRAM cell has three kinds of values change such

as ‘0 -> 1 (2 -> 1)’, ‘0 -> 2 (2 -> 0)’, and ‘1 -> 0 (1 -> 2)’.

10 11 12 13 140

10

20

30

40

50

60

Chirality (n)

Del

ay (p

s)

0

10

20

30

40

50

60

Delay (Largest) Delay (Average) Delay (Least) PDP (Largest) PDP (Average) PDP (Least)

PDP

(aJ)

Figure 5.12: Average delay and power delay product when chirality vectors in MN33, MN43, MP53, and MP63 are changed

After utilizing the previously mentioned methodology to optimize the gate widths

and chiralitys of CNTFETs in TC SRAM cells, three values (0, 1, and 2) can be

written and read as shown in Figure 5.13 and Figure 5.14 respectively. Found

optimized MN4/MN2 ratio and MP5/MN1 ratio are written in Table 5.3 also. Write

121

operation of first proposed TC SRAM is similar to that of traditional binary SRAM

cell. After setting up the desired voltage level in BL and BLB, MN1 and MN2 are

turned on. For read operation in TC SRAM cell, as mentioned before, MN9 and

MN10 are turned on with high voltage of WLR. Figure 5.14 shows that BL and BLB

are discharged more quickly when 0 or 2 are stored than when 1 is stored because

smaller voltage is applied to the gate of MN9 and MN10 when 1 is stored.

Figure 5.13: Write operation of the first proposed TC SRAM cell

122

Figure 5.14: Read operation of the first proposed TC SRAM cell Detailed delay, power, PDP, and SNM are measured and written in Table 5.3.

Table 5.3 shows that TC SRAM has 4.193 times (2.024 times) better performance in

PDP aspect comparing to BM SRAM (BC SRAM). However, TC SRAM is slower

than BC SRAM in average and has smaller SNM than BM (and BC) SRAM. Smaller

SNM is unavoidable because, in TC SRAM, three voltage levels are stored with the

supply voltage level (e.g. 0.9V) which is also used in Binary SRAM cell. Simulation

results for Sheng Lin’s TC SRAM are also written in Table 5.4. Simulation is

performed under same conditions (such as same clock’s cycle time, rise (and fall)

time, points to measure delay, and capacitance in bit lines) which are used in this

paper; so, simulation results in Table 5.4 are different from those in [38]. To

compare the performance fairly between the first proposed TC SRAM and Sheng

Lin’s TC SRAM, only one pass transistor should be used (MP1 and MP2 in Figure 7

123

should be removed). However, the number of transistor is also critical condition in

comparing performance of SRAM cells; so, in this paper, Sheng Lin’s SRAM

includes MP1 and MP2 in comparing performance. Table 5.4 shows that Sheng Lin’s

TC SRAM has six different write (and read) delay, power, PDP depending on the

change of values because his circuit is asymmetric. Comparing to the first proposed

TC SRAM, his TC SRAM has more delay, power and PDP (5.700%, 34.980%, and

58.328% on average) and those values are more deviated (104.964%, 13.871%, and

58.133% in delay, power, and PDP on average respectively) in write operation. In

read operation, Sheng Lin’s TC SRAM has less delay (17.736%) on average (but

almost same delay in largest delay) and additional power is necessary to operate read

buffer and charge RBL; so, power for read operation is measured in Sheng Lin’s TC

SRAM (Table 5.4). Moreover, the required power to charge RBL is determined by

the capacitance of RBL (10fF is used in this paper) and it is increased as the size of

SRAM is increased. Table 5.4 shows that 2.839 uW is required to read 2. Especially,

when 1 is read, theoretically, the voltage value in RBL should not be changed (MP3

and MN3 should not work) during read operation. However, as mentioned before,

threshold voltage for MN3 (MP3) in Figure 5.4 is 0.559V (-0.559V) and the voltage

in nq is 0.45V when 1 is stored; so, MP3 and MN3 is slightly turned on at the same

time in HSPICE simulation (so, power is consumed (0.621uW)) and the voltage level

in RBL keeps decreasing (more 0.1V) for given clock time in this paper.

124

Table 5.3: Transistor ratio and performance

Change

of Values

Ratio Performance SNM(mV)

Write Read MN4 /MN2

MP5/MN1

Delay(ps)

Power (uW)

PDP (aJ)

Delay (ps)

BM SRAM

0 -> 2 (2 -> 0) 2.0 1.0 49.009 1.648 80.762 58.061/

N/A 364.962

BC SRAM

0 -> 2 (2 -> 0) 1.0 0.5 25.922 1.504 38.984 73.211 /

N/A 456.388

First Proposed

TC SRAM

0 -> 1 (2 -> 1) 0.5 0.5 54.259 0.036 1.966

129.450 /

281.930

221.539 /181.573

0 -> 2 (2 -> 0) 0.5 0.5 49.851 0.880 43.844

1 -> 0 (1 -> 2) 0.5 0.5 29.558 0.405 11.972

Avg. 0.5 0.5 44.556 0.440 19.261 205.690 201.556Std. Dev. 0 0 13.174 0.423 21.870 107.820 28.260

Table 5.4: Read and write delay of Lin’s TC SRAM cell

Write Read SNM (mV) Change

of Values

Delay (ps)

Power(uW)

PDP(aJ) Values Delay

(ps) Power(uW)

PDP (aJ)

Lin’s TC

SRAM

2 -> 1 76.363 1.223 93.369 0 159.040 0.026 4.126

299.993/99.339

0 -> 1 81.554 0.282 22.9840 -> 2 45.714 0.122 5.578 1 63.409 0.621 39.345 2 -> 0 40.364 1.154 46.5601 -> 0 17.293 0.549 9.500 2 282.110 2.400 677.064 1 -> 2 21.286 0.234 4.983Avg. 47.096 0.594 30.495 Avg. 168.186 1.015 240.179 199.666Std. Dev. 27.002 0.482 34.584 Std.

Dev. 109.637 1.235 378.763 141.883

125

As mentioned before, the first proposed TC SRAM shows better performance

than BM (and BC) SRAM in PDP aspect, but in write delay, the first proposed TC

SRAM is 1.729 times slower than BC SRAM on average. In read delay, the first

proposed TC SRAM is 2.81 times slower than BC SRAM. Therefore, new

methodology to reduce delay in the first proposed TC SRAM is required.

When MN4/MN2 and MN5/MN1 ratio in Table 5.3 is considered, it is also found

that MN1 and MN2 should be more conductive than other transistors (In this paper,

MN1 and MN2 will be names ‘write circuit’ because those transistors are only used

for writing some values in TC SRAM). This means that it is worth to increase the

chirality in the write circuit to make more current flow through MN1 and MN2. To

increase current, gate width and then number of CNTs in each CNTFET can be

increased at the same time as did before. However, in TC SRAM, area is already

increased too much due to the high number of transistor comparing binary SRAM

and CNTFET’s advantage is that the current can be increased only by increasing

chirality (circuit area can be saved). Figure 5.15 shows that, as chirality increases,

delay and PDP decrease at the same time because more current can flow through

write circuit and power consumption is almost not changed because the chirality of

CNTFETs used as resistor is decreased before. At some point (when chirality is 20

and 22), PDP is increased because more current flows (more power is consumed)

than the reduced transient time. With same methodology, read time also can decrease

by increasing chirality in read circuit (MN9, MN10, MN11, and MN12) and Figure

5.16 shows that read delay can decrease as chirality increase.

126

16 18 20 22 24 26 28 300

10

20

30

40

50

60

70

Chirality (n)

Del

ay (p

s)

0

10

20

30

40

50

60

70


PD

P(aJ)

Figure 5.15: Largest, average, and least write delay and power delay product when chiralitiy in write circuits (MN1 and MN2) is changed in the first proposed TC SRAM

16 18 20 22 24 26 28 30

100

150

200

250

300

350

400

450

500

Rea

d (p

s)

Chirality (n)

Largest Read Delay Average Read Delay Least Read Delay

Figure 5.16: Largest, average, and least read delay when chirality in read circuit (MN9, MN10, MN11, and MN12) is changed in the first proposed TC SRAM

127

5.2.2 Second Proposed Ternary CNTFET SRAM

In first proposed TC SRAM, to store value ‘1’, BL and BLB should be set to

0.45V. This means that generally more complicated or additional voltage control (or

supply) is required to operate ternary SRAM. To utilize the traditional voltage

controller (or supply) for binary SRAM (which can have only 0V and 0.9V) in

ternary SRAM, in this paper, two transistors (MN7 and MN8) are added in first

proposed TC SRAM (this SRAM will be named second proposed TC SRAM in this

paper) as shown in Figure 5.17. These two transistors also can make write operation

simpler and reduce the number of bit line when ‘1’ is stored. The write operation for

the second proposed TC SRAM is shown in Figure 5.18 (the read operation for

second proposed TC SRAM is not shown in this paper because that is same as the

read operation of first propose TC SRAM).

Figure 5.17: The second proposed TC SRAM

128

Figure 5.18: Write operation of the second proposed TC SRAM Figure 5.18 shows that, by just applying 0.9 V on two lines (BL and WLR), ‘1’

can be stored in ternary SRAM (‘X’ in Figure 5.18 means the voltage of this line

does not affect to the operation). Considering generally three lines should be

controlled in binary (and ternary) SRAM to write a value and the huge capacitance

of each line, it can be expected that this scheme can reduce power consumption when

‘1’ is stored (The capacitance of bit lines is not considered in this paper). When ‘1’ is

stored, the value in SRAM is changed without support of BL and BLB (MN1 and

MN2 are closed); so, it takes longer time and more power is consumed due to the

increase of transient time. When ‘0’ or ‘2’ are stored, second proposed TC SRAM

also takes more time and consumes more power than first proposed TC SRAM

129

because the capacitance in ‘q’ and ‘nq’ are increased due to MN7 and MN8. The

detailed performance of second proposed TC SRAM is written in Table 5.5.

Table 5.5: The performance of the second proposed TC SRAM

Change

of Values

Performance SNM (mV)

Write ReadDelay(ps)

Power (uW)

PDP (aJ)

Delay(ps)

Second Proposed

TC SRAM

0 -> 1 (2 -> 1) 58.764 0.069 4.050

129.450/291.270

221.539 /181.573

0 -> 2 (2 -> 0) 51.067 0.893 45.596

1 -> 0 (1 -> 2) 30.143 0.411 12.382

Avg. 46.658 0.458 20.676 210.360 201.556 Std. Dev. 14.811 0.414 21.980 114.424 28.260

Table 5.5 shows that delay, power, and PDP of second proposed TC SRAM is

4.505%, 3.773%, and 6.846% in average bigger than those of first proposed TC

SRAM respectively. To improve performance, as applied to first proposed TC

SRAM, chirality can be increase in write circuit and read circuit (In second proposed

circuit, write circuit is consisted of four transistors such as MN1, MN2, MN7 and

MN8). Figure 5.19 and Figure 5.20 show delay (or PDP) decrease as chirality

increase in write circuit and read circuit as shown in first proposed TC SRAM. In

Figure 5.19, largest delay cannot be decreased continuously depending on the

130

increase of chirality. Delay has largest value when value is changed from 0 (or 2) to

1 as written in Table 6. In the second proposed TC SRAM, 0 -> 1 (or 2 -> 1)

operation is performed by MN7 and MN8. With the increase of chirality in MN7 and

MN8, overall delay can be decrease as shown in Figure 5.21, but sometimes it takes

longer time for values in q (nq) to settle down to the final value, 0.45 V. This means

that wider detection range for 0.45 V is required in the second proposed TC SRAM

comparing to the first proposed TC SRAM.

16 18 20 22 24 26 28 300

10

20

30

40

50

60

70


Chirality (n)

Del

ay (p

s)

0

10

20

30

40

50

60

70

PD

P(aJ)

Figure 5.19: Largest, average, and least write delay and power delay product when chiralitiy in write circuits (MN1, MN2, MN7 and MN8) is changed in the second proposed TC SRAM

131

16 18 20 22 24 26 28 30

100

150

200

250

300

350

400

450

500

Rea

d (p

s)

Chirality (n)

Largest Read Delay Average Read Delay Least Read Delay

Figure 5.20: Largest, average, and least read delay when chirality in read circuit (MN9, MN10, MN11, and MN12) is changed in the second proposed TC SRAM

Figure 5.21: Delay of 0 -> 1 (or 2 -> 1) when chiralitiy in write circuits (MN1, MN2, MN7 and MN8) is changed in the second proposed TC SRAM

132

5.3 Process Variation

When the process variation is discussed in CNTFET circuit, generally two kinds

of process variations (conventional process variation and CNT-specific variation) are

considered. Previous research shows that the most conventional process variations

(such as channel length, channel width, oxide thickness, and threshold voltage

variations) contribute smaller impact in CNTFET comparing to the impact in

MOSFET because of the superior transport and electrostatic properties of CNTFET.

However, the process variations which can directly change the number of CNTs and

the pitch in each CNTFET (CNT-count variations) can significantly degrade the

performance of CNTFET circuit [57]-[61].

To evaluate the effect of the conventional process in the above mentioned SRAM

cells, in this paper, lithographic process variation (gate length and gate width) is

considered first because in the conventional variations, lithographic process variation

can change the parameters (gate length and width) with exactly same amount in the

MOSFET and CNTFET SRAM cells at the same time; so, the effect of process

variation can be evaluated fairly. As the proposed SRAM cells are CNTFET-based,

the CNT-count variation, the pitch and the number of CNTs in each CNTFET are

also considered. Before discussing these process variations, the density of CNTFET

should be determined first because, basically depending on the density, the

performance of CNTFET-based circuit is changed and different minimum gate width

and number of CNTs is used in the design of CNTFET circuits.

133

5.3.1 Density

When the proposed SRAM cells are designed and simulated in the previous

chapter, it is assumed that pitch is 32nm; so, the minimum gate width is 32nm and

there is one CNT. In this case, density is about 30 CNTs/um and it is called by

normal density (ND) in this paper. Previous research shows that high density (>100

CNTs/um) is required for CNTFET to have better (or comparable) performance to

MOSFET in basic digital logic circuit (SRAM is not included) [15]. However,

currently possible density is 10 CNTs/um (With this density, most semiconducting

CNTs can be aligned) [49]. Therefore, it is worth to measure the performance of

previously discussed SRAM cells when the density is changed. With using three

different density such as high (100 CNTs/um), normal (30 CNTs/um), and low (10

CNTs/um) density, previously mentioned sizing methodology is applied again and

performance is measured (Table 5.6) (The low density, normal density, and high

density are denoted as LD, ND, and HD respectively). Table 5.6 shows that when

the density is changed from ND to LD, write (read) delay and write (and read) power

are increased 76.213% (0.075%) and 51.101% (4.727%) because when the density is

changed to LD, gate width is increased but the number of CNTs are not increased.

This causes huge delay and the delay increase transient time in the SRAM cell; so,

more dynamic power is consumed in the operations but the increase of power is

relatively small comparing to the increase of delay. This increase of delay and power

causes 188.769% (3.716%) write (read) PDP increase respectively. When the density

134

is changed from ND to HD, more CNTs can be deposited in the same gate width

(32nm) in each CNTFET; so, write and read delay can be decreased 25.289% and

58.253% respectively. However, write and read power is increased 129.606%

(149.364%); so, these increase make write (read) PDP 75.621% (6.945%) increased.

This means more power should be consumed comparing to the delay decrease.

Regarding SNM, Table 5.6 shows that the density change the SNM less than 0.04%

because basically SNM is changed by threshold voltage and gate width sizing ratio

between CNTFET; so, when the density is changed in the whole CNTFETs at the

same time, SNM is not almost changed.

Table 5.6: Density and performance

Density

Average Performance SNM(mV)

Write Read Delay (ps)

Power(uW)

PDP (aJ)

Delay(ps)

Power(uW)

PDP (aJ)

BM SRAM N/A 49.009 1.648 80.762 58.061 0.071 4.109 364.962

BC SRAM

Low 27.539 1.616 44.503 72.679 0.063 4.594 455.767Normal 25.922 1.504 38.984 73.211 0.078 5.724 456.388

High 23.595 4.014 94.720 34.051 0.077 2.627 464.792First

Proposed TC

SRAM

Low 83.752 0.908 87.129 207.400 0.004 0.910 201.836Normal 44.556 0.440 19.261 205.680 0.004 0.880 201.556

High 31.549 0.763 19.863 80.334 0.015 1.211 198.042

Second Proposed

TC SRAM

Low 91.677 0.939 91.198 210.010 0.003 0.701 201.836Normal 46.658 0.458 20.676 210.350 0.003 0.701 201.556

High 31.983 0.784 21.204 83.104 0.013 1.054 198.042

Lin’s TC

SRAM [13]

Low 86.430 1.064 93.129 167.833 1.082 250.476 199.779Normal 47.096 0.594 30.495 168.186 1.015 240.179 199.666

High 35.572 1.318 56.371 76.968 2.638 259.781 197.880

135

5.3.2 Lithography

When the gate length and width is discussed in the previous paper, it is assumed

that the gate length of CNTFET and MOSFET is 32nm. This means, when the

CNTFET and MOSFET are manufactured, 32nm technology is utilized and process

variation can exist based on the 32nm. To evaluate the effect of lithographic process,

in this paper, 1000 times Monte Carlo simulation is performed with Gaussian

distribution (±5% distribution at the ±3 sigma level) in the gate width and length of

whole SRAM cells which are discussed in this paper. Standard deviation of write

(and read) delay, power, and PDP are measured and shown in Figure 5.22, Figure

5.23, and Figure 5.24 (Figure 5.25, Figure 5.26, and Figure 5.27) respectively (More

detailed simulation results are also provided in Table 5.10).

BM BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.0

0.5

1.0

3.5

4.0

Stan

dard

Dev

iatio

n of

Ave

rage

Writ

e D

elay

(ps)

Figure 5.22: Standard deviation of average write delay with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

136

BM BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.000

0.005

0.010

0.015

0.160

0.165

0.170

0.175

Stan

dard

Dev

iatio

n of

Ave

rage

Writ

e P

ower

(uW

)

Figure 5.23: Standard deviation of average write power with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

BM BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.00

0.25

0.50

0.75

14.00

14.25

14.50

14.75

15.00

Stan

dard

Dev

iatio

n of

Ave

rage

Writ

e PD

P (a

J)

Figure 5.24: Standard deviation of average write power delay product with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

137

BM BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Sta

ndar

d D

evia

tion

of A

vera

ge R

ead

Del

ay (p

s)

Figure 5.25: Standard deviation of average read delay with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

BM BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.000

0.001

0.002

0.003

0.004

0.030

0.031

0.032

0.033

0.034

0.035

Sta

ndar

d D

evia

tion

of A

vera

ge R

ead

Pow

er (u

W)

Figure 5.26: Standard deviation of average read power with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

138

BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Sta

ndar

d D

evia

tion

of A

vera

ge R

ead

PDP

(aJ)

Figure 5.27: Standard deviation of average read power delay product with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

The figures show that BM SRAM’s write (and read) delay, power, and PDP are

about 10.632 times, 41.212 times, and 32.615 times (3.931 times, 29.333 times, and

10.883 times) bigger than other CNTFET SRAM cells. This means that BM SRAM

cell is more sensitive to lithographic process variation than other CNTFET SRAM

cells. As explained before, CNTs are used as channel between drain and source in a

CNTFET; so, lithographic process causes smaller impact (comparing to MOSFET)

to the gate capacitance (not the current) of each CNTFET. Figure 5.23 shows that, in

the BC SRAM cell, about 10 times reduction in the standard deviation of write delay

can be achieved when the density is decreased because when the density is decreased,

gate width is increased; so, the 32nm lithographic variation gives smaller impact to

the low density BM SRAM cells. However, in other TC SRAM cells (Figure 5.23),

139

the reduction (or change) in the standard deviations of write delay for those SRAM

cells are relatively small because even though the impact of the 32nm lithographic

variation is relatively small in the low density CNTFET SRAM cells, there are more

transistor comparing to those in BC SRAM cells. For read delay (Figure 5.25), the

density cannot make bit different in the whole SRAM cells because, in the read

operation, the status of each CNTFET is not changed and only some CNTFETs are

utilized in the operation. In the power aspect, Figure 5.23 and Figure 5.26 show that

the lithographic process variation and the density cannot make big change because,

as mentioned before, those factors cannot change current in each CNTFET.

Especially, in the read operation of first and second proposed TC SRAM (Figure

5.26), only four CNTFETs for read circuit are used for read operation, very small

variation exists. Based on these write (and read) delay and power values, PDP is

calculated and depicted in Figure 5.24 (and Figure 5.27). Under same lithographic

and density variation, SNM is also measured and the results are written in Figure

5.28. Figure 5.28 shows that BM SRAM cell is about 48.933 times more sensitive to

lithographic variation than other CNTFET SRAM cells and the density cannot make

big change in SNM values (Detailed SNM values are provided in Table 5.12).

5.3.3 The number of CNTs

As mentioned before, in a CNTFET manufacturing process, all desired CNTs

cannot be deposited to the substrate of CNTFET (the number of CNTs can be

changed) and this can make CNTFET’s performance severely degraded [1][2][7]. To

140

measure this performance degradation, 1000 times Monte Carlo simulation is

performed in ND and LD CNTFET SRAM cells with random limit distribution

function which decreases the number of CNTs in each CNTFET randomly until the

SRAM cells does not work.

BM BC BCLD

FirstTC

First TCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.0

0.2

0.4

0.6

0.8

10.0

10.5

11.0

11.5

12.0

Sta

ndar

d D

evia

tion

of A

vera

ge S

NM

(mV

)

Figure 5.28: Standard deviation of average SNM with Gaussian distribution (±5% distribution at the ±3 sigma level) in 32nm gate width and length.

The number of CNTs can be also decreased in HD CNTFET-based SRAM cells

and the number of CNTs can be increased in ND and LD CNTFET-based SRAM

cells. However, in these cases, the distance between CNTs (pitch) can be changed

unevenly in each CNTFET, but current HSPICE-based CNTFET model (which is

also used in this paper) cannot support the unevenly positioned CNTs [35]. The other

cases, pitch and the number of CNTs are increased or decreased evenly, are already

discussed when we measure the performance of CNTFET SRAM cells with different

141

density (Table 5.6). When the number of CNTs is decreased in ND and LD CNTFET

SRAM cell, the type of position such as evenly or unevenly cannot be a problem

because as written in Table 5.3 and Table 5.4, the ratio between MN4/MN2 and

MN5/MN3 is 2 or 0.5. This means that the number of CNTs in each CNTFET is 2 or

1.

When the number of CNTs is decreased randomly, average standard deviation for

write (and read) delay, power, and PDP is measured in CNTFET SRAM cells and

the results are shown in Figure 5.29, Figure 5.30, and Figure 5.31 (Figure 5.32,

Figure 5.33, and Figure 5.34) respectively (More detailed simulation results are also

provided in Table 5.11). The simulation results show that when the number of CNTs

is decreased randomly in CNTFET SRAM cells, 42.082 times, 57.545 times, and

56.457 times (39.633 times, 330.222 times, and 576.632 times) more standard

deviation are caused in write (read) delay, power, and PDP comparing to those of

CNTFET SRAM cells which has lithographic variations. From these results, it can

be found that as found in [47][48][50], CNT-count variation can degrade

performance more severely comparing to lithographic variation in CNTFET circuits.

Especially, when read delay and read power are measured in First TC SRAM, First

TC SRAM LD, Second TC SRAM, and Second TC SRAM LD (Figure 5.29 and

Figure 5.30), it can be found that standard deviation is very small. As shown in

Figure 5.5 and Figure 5.17, those SRAM cells have read circuit and CNTFET in the

read circuit has only one CNT; so, in CNT-count variation, the number of CNTs is

not changed. When the performance for Lin’s TC SRAM cell is analyzed, it is found

142

that Lin’s TC SRAM cell has 5.111 times, 8.440 times and 7.872 times (15.938 times,

8.594 times, and 27.862 times) more standard deviations in write (read) delay, power,

and PDP than those of other SRAM cells. In Lin’s SRAM cell (Figure 5.4), the

number of CNTs can be decreased until the number of CNTs in MN1, MP1, MN2,

and MP2 becomes partially 0 because the number of CNTs is decreased until SRAM

cell does not work. From the simulation results, it can be found that when, in Lin’s

SRAM cell, two CNTFETs (N-CNTFET and P-CNTFET) are necessary for each

write and read transmission gates to secure similar stability to those for other

CNTFET SRAM cells.

BC BC LD FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0

10

20

30

40

50

Sta

ndar

d D

evia

tion

of A

vera

ge W

rite

Del

ay (p

s)

Figure 5.29: Standard deviation of average write delay with random limit distribution (±1 absolute distribution) in the number of CNTs.

143

BC BC LD FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.0

0.2

0.4

0.6

0.8

1.0

Sta

ndar

d D

evia

tion

of A

vera

ge W

rite

Pow

er (u

W)

Figure 5.30: Standard deviation of average write power with random limit distribution (±1 absolute distribution) in the number of CNTs.

BC BC LD FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0

20

40

60

80

100

120

Sta

ndar

d D

evia

tion

of A

vera

ge W

rite

PD

P (a

J)

Figure 5.31: Standard deviation of average write power delay product with random limit distribution (±1 absolute distribution) in the number of CNTs.

144

BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0

10

20

30

40

50

60

70

80

90

100

110

120

130

Sta

ndar

d D

evia

tion

of A

vera

ge R

ead

Del

ay (p

s)

Figure 5.32: Standard deviation of average read delay with random limit distribution (±1 absolute distribution) in the number of CNTs.

BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0.0

0.2

0.4

0.6

0.8

1.0

Stan

dard

Dev

iatio

n of

Ave

rage

Rea

d Po

wer

(uW

)

Figure 5.33: Standard deviation of average read power with random limit distribution (±1 absolute distribution) in the number of CNTs.

145

BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0

50

100

150

200

250

300

350

400

Sta

ndar

d D

evia

tion

of A

vera

ge R

ead

PDP

(aJ)

Figure 5.34: Standard deviation of average read power delay product with random limit distribution (±1 absolute distribution) in the number of CNTs.

SNM is also measured when the number of CNTs is decreased randomly (Figure

5.35), Figure 5.35 shows that BC SRAM and BC SRAM LD shows 37.314 times

bigger standard deviation by CNT-count variation comparing to those by

lithographic variation. However, otherwise, there are almost zero standard deviations

for other SRAM cells. As written in Table 3, different ratio between P-CNTFET and

N-CNTFET is necessary in BC SRAM cell; so, when the number of CNTs for each

CNTFET is decreased randomly, the ratio can be changed. However, in other SRAM

cells, minimum gate width (and number of CNTs) is used; so, the number of CNTs

in SRAM cells is not changed (Detailed SNM values are provided in Table 5.12).

146

BC BCLD

FirstTC

FirstTCLD

SecondTC

SecondTCLD

LinTC

LinTCLD

0

2

4

6

8

10

12

14

16

18

20

22

Sta

ndar

d D

evia

tion

of A

vera

ge S

NM

(mV

)

Figure 5.35: Standard deviation of average SNM with random limit distribution (±1 absolute distribution) in the number of CNTs.

5.4 Summary

Based on the simulation results from previous chapters, Table 5.7, Table, 5.8, and

Table 5.9 summarize the discussed SRAMs’ performance and sensitivity to process

variations by assigning a ranking. Table 5.7 shows that, in delay and SNM aspect,

BC SRAM shows better performance than other SRAMs, but the two proposed TC

SRAMs consume less power; so, the proposed SRMAs have better performance in

PDP aspect. Regarding the standard deviation to lithographic process variation, BM

SRAM is the most sensitive to the process variation (Table 5.8). In Figure 5.26,

Figure 5.27, and Table 5.10, the standard deviation values (read delay and power) for

First Proposed TC SRAM and Second Proposed TC SRAM are written as 0, but

147

those have very small number. A raking is determined by the small numbers and

written in Table 5.8. The standard deviations to process variation in number of CNTs

are also calculated and written in Table 5.9. Table 5.9 shows that Lin’s TC SRAM

has the most sensitivity to the variations because some CNTFETs in write and read

transmission gates do not work when the number of CNTs is decreased randomly.

Some values in Figure 5.32, Figure 5.33, and Figure 5.34, Table 5.11, and Table 5.12

are written as 0, but those also have very small values. A raking is calculated based

on the values and written in Table 5.9.

5.4 Conclusion

This paper has presented the two ternary CNTFET SRAMs based on the

previously suggested standard ternary inverter. To utilize the conventional transistor

sizing methods, whole transistors in ternary CNTFET SRAMs are grouped and

optimized at the same time. Chirality in individual CNTFET is also changed to

improve SNM and to reduce power. To reduce write and read time in ternary

CNTFET SRAM, the method to increase chirality in write circuit and read circuit is

also proposed. By utilizing these methods, first proposed ternary CNTFET SRAM

shows 4.193 times (2.024 times) better performance comparing to binary MOSFET

SRAM (binary CNTFET SRAM) in PDP aspect. Second proposed ternary CNTFET

SRAM makes it possible to store ‘1’ with less bit lines and voltage levels by adding

two more transistors at the expense of 3.733% more power. Extensive simulations to

find proper density and to evaluate the effect of process variation are also performed.

148

With the simulations, it is found that 30 CNTs/um is proper for CNTFET SRAMs

and MOSFET SRAMs is more vulnerable (21.749 times) to lithographic process

variation comparing to CNTFET SRAMs. In CNTFET SRAMs, it is also found that

CNT count variation make 316.544 times more variation comparing to lithographic

process variation. SNM is also analyzed when those density and process variations

are changed and the results show that the density almost cannot change SNM

because the pitch and the number of CNTs for whole CNTFET in SRAMs are

changed at the same time. When the process variations change the ratio between

PFET and NFET in SRAMs, it can make variation in SNM and it is CNT count

variation makes 3.045 times more variation comparing to lithographic variation.

Table 5.7: The rank of performance

Density Average Performance

Write Read SNMDelay Power PDP Delay Power PDP BM SRAM 6 9 6 1 6 5 3 BC SRAM 1 7 4 3 7 7 1

BC SRAM (LD) 2 8 5 2 5 6 2 First Proposed

TC SRAM 3 1 1 6 3 3 6

First Proposed TC SRAM (LD) 7 4 7 7 3 4 4

Second Proposed TC SRAM 4 2 2 9 1 1 6

Second Proposed TC SRAM (LD) 9 5 8 8 2 2 4

Lin’s TC SRAM [13] 5 3 3 5 8 8 9

Lin’s TC SRAM (LD) [13]l 8 6 9 4 9 9 8

149

Table 5.8: The rank of standard deviation to the process variation in lithography


Write Read SNMDelay Power PDP Delay Power PDP BM SRAM 9 9 9 9 9 9 9

BC SRAM 6 7 8 2 7 5 8


TC SRAM 2 4 1 6 1 3 4




Lin’s TC SRAM [13] 8 5 4 3 5 7 6

Lin’s TC SRAM (LD) [13]l 7 6 7 4 8 8 5

Table 5.9: The rank of standard deviation to the process variation in the number of CNTs


Write Read SNMDelay Power PDP Delay Power PDP BC SRAM 5 6 5 6 5 5 7


TC SRAM 3 2 1 4 2 2 1




Lin’s TC SRAM [13] 7 7 7 7 7 7 5

Lin’s TC SRAM (LD) [13]l 8 8 8 8 8 8 6

150

5.5 Appendix Table 5.10: The process variation in lithography

Average Performance Write Read

Delay (ps)

Power (uW)

PDP (aJ)

Delay (ps)

Power (uW)

PDP (aJ)

BM SRAM

Mean 50.741 1.748 89.086 57.738 0.080 4.589 Std. Dev. 3.761 0.170 14.648 3.150 0.033 1.891

FF 48.479 1.902 102.942 55.187 0.111 6.365 SS 54.609 1.643 81.191 60.064 0.059 3.395

BC SRAM

Mean 25.874 1.503 38.891 73.214 0.078 5.722 Std. Dev. 0.429 0.006 0.761 0.182 0.002 0.153

FF 25.660 1.507 39.118 73.072 0.080 5.842 SS 25.996 1.499 38.528 73.362 0.076 5.598

BC SRAM (LD)

Mean 27.545 1.616 44.515 72.680 0.063 4.591 Std. Dev. 0.043 0.006 0.234 0.182 0.002 0.156

FF 27.510 1.621 44.694 72.539 0.065 4.714 SS 27.578 1.611 44.324 72.830 0.061 4.465

First Proposed TC

SRAM

Mean 44.554 0.440 19.213 205.719 0.002 0.653 Std. Dev. 0.166 0.002 0.120 1.026 0.000 0.009

FF 44.510 0.442 19.388 204.908 0.002 0.660 SS 44.596 0.439 19.111 206.549 0.002 0.646

First Proposed TCSRAM

(LD)

Mean 83.777 0.908 87.161 207.446 0.004 1.215 Std. Dev. 0.193 0.003 0.481 1.019 0.000 0.008

FF 83.617 0.911 87.546 206.645 0.004 1.222 SS 83.925 0.906 86.775 208.276 0.004 1.209

Second Proposed TCSRAM

Mean 46.665 0.458 20.684 210.383 0.003 0.557 Std. Dev. 0.331 0.002 0.208 1.160 0.000 0.000

FF 46.396 0.459 20.851 209.491 0.003 0.559 SS 46.931 0.456 20.514 211.346 0.003 0.554

Second Proposed

TC SRAM (LD)

Mean 91.681 0.939 91.204 211.732 0.003 0.859 Std. Dev. 0.373 0.003 0.576 1.109 0.000 0.010

FF 91.377 0.942 91.671 210.887 0.003 0.867 SS 91.985 0.936 90.743 212.660 0.003 0.851

Lin’s TC SRAM

[13]

Mean 47.160 0.592 30.487 168.287 1.015 240.234Std. Dev. 0.734 0.005 0.463 0.858 0.002 0.496

FF 46.696 0.585 30.848 168.978 1.017 240.608SS 47.722 0.577 30.159 167.279 1.013 239.834

Lin’s TC SRAM [13] (LD)

Mean 91.296 0.538 36.734 168.681 1.074 250.266Std. Dev. 0.561 0.006 0.750 0.875 0.003 0.558

FF 90.836 0.542 37.270 167.913 1.076 250.669SS 91.767 0.532 35.956 169.350 1.072 249.773

151

Table 5.11: The process variation in the number of CNTs

Average Performance Write Read

Delay (ps)

Power(uW)

PDP (aJ)

Delay (ps)

Power (nW)

PDP (aJ)

BC SRAM

Mean 31.277 1.429 45.782 100.578 0.272 27.794Std. Dev. 9.331 0.201 18.103 20.143 0.372 37.893

FF 40.553 1.565 66.692 86.002 0.877 89.121SS 24.211 1.200 33.342 115.810 0.085 8.850

BC SRAM (LD)

Mean 37.151 1.620 61.338 99.752 0.290 29.346Std. Dev. 10.976 0.198 22.422 19.933 0.397 40.017

FF 26.796 1.763 81.865 85.438 0.935 93.987SS 47.590 1.509 40.975 114.710 0.091 9.379

First Proposed

TC SRAM

Mean 49.763 0.440 21.925 205.626 0.004 1.165Std. Dev. 5.332 0.006 3.006 0.075 0.000 0.001

FF 44.535 0.445 24.942 205.550 0.004 1.166SS 55.075 0.435 18.955 205.700 0.004 1.164

First Proposed

TC SRAM (LD)

Mean 92.618 0.880 90.796 207.375 0.004 1.216Std. Dev. 8.605 0.044 4.832 0.025 0.000 0.000

FF 84.180 0.922 95.535 207.350 0.004 1.216SS 101.191 0.838 86.133 207.400 0.004 1.216

Second Proposed

TC SRAM

Mean 50.536 0.459 23.414 210.300 0.003 0.859Std. Dev. 4.531 0.005 3.066 0.050 0.000 0.002

FF 46.139 0.463 26.492 210.250 0.003 0.861SS 54.996 0.454 20.385 210.350 0.003 0.857

Second Proposed

TC SRAM (LD)

Mean 96.740 0.909 94.236 209.975 0.003 0.865Std. Dev. 5.273 0.044 4.545 0.025 0.000 0.001

FF 91.634 0.949 98.643 209.950 0.003 0.866SS 101.930 0.867 89.865 210.000 0.003 0.864

Lin’s TC SRAM

[13]

Mean 49.241 0.588 31.287 170.898 1.198 286.610Std. Dev. 29.257 0.468 35.333 97.418 1.101 354.044

FF 85.495 1.194 72.774 283.850 2.375 674.100SS 31.114 0.285 10.543 123.422 0.413 28.283


Mean 92.263 1.056 99.450 157.306 1.273 286.446Std. Dev. 45.786 0.933 111.543 116.416 1.102 369.560

FF 147.375 2.258 241.490 222.375 2.449 690.801SS 64.706 0.455 28.430 27.168 0.489 16.876

152

Table 5.12: SNM vs. process variation

Process Variation

Lithography CNTs

BM SRAM

Mean 374.531

N/A Std. Dev. 11.701 FF 383.832 SS 365.268

BC SRAM

Mean 456.759 480.058 Std. Dev. 0.556 20.710

FF 457.216 500.640 SS 456.331 459.475

BC SRAM (LD)

Mean 456.135 479.460 Std. Dev. 0.555 20.746

FF 456.592 500.080 SS 455.709 458.840

First Proposed

TC SRAM

Mean 201.603 201.550 Std. Dev. 0.118 0.000

FF 201.703 201.550 SS 201.517 201.550

First Proposed

TC SRAM (LD)

Mean 201.888 201.550 Std. Dev. 0.117 0.000

FF 201.983 201.550 SS 201.800 201.550

Second Proposed

TC SRAM

Mean 201.602 201.550 Std. Dev. 0.113 0.000

FF 201.699 201.550 SS 201.517 201.550

Second Proposed

TC SRAM (LD)

Mean 201.887 201.550 Std. Dev. 0.112 0.000

FF 201.980 201.550 SS 201.800 201.550

Lin’s TC SRAM

[13]

Mean 199.822 199.670 Std. Dev. 0.171 0.000

FF 199.971 199.670 SS 199.703 199.670


Mean 199.932 199.670 Std. Dev. 0.171 0.000

FF 200.081 199.670 SS 199.813 199.670

153

Chapter 6 Summary and Future Work 6.1 Summary of Contributions

The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device

to supersede the MOSFET at the end of the technology roadmap of CMOS. When

designing and manufacturing a CNTFET, additional features such as pitch, number

and position of the CNTs must be considered to assess its performance. One of the

defect types that can occur when fabricating a CNTFET is the absence of some

CNTs following the deposition/growth step. As result of the this type of defect, a

CNTFET will show a change in operational characteristics because drain current,

gate capacitance, and delay will be affected due to the lower number of CNTs with

uneven spacing between them present in the channel of the transistor.

154

In Chapter 2, a new model by which the drain current, the gate capacitance and

the delay can be found when not all CNTs are deposited on the substrate. This results

in an uneven CNT spacing in the channel; new equations are derived and shown to

be applicable to both defective and defect-free CNTFETs. The proposed model has

been implemented in MATLAB and has been extensively simulated to show that

defects due to undeposited CNTs have a significant impact on the operation of a

CNTFET. Delay as degradation in performance is shown to be related to both the

number and position of the defects; an extensive delay analysis on both deterministic

and probabilistic basis is presented.

To mitigate the change in delay, in Chapter 3 Two solutions are proposed; these

approaches are based on adjusting the gate width of the CNTFET by lithography

(and removing CNTs) as part of the fabrication process. These two methods reduce

the average delay and its deviation, respectively. A probabilistic delay analysis is

then presented. The performance of the proposed two adjustment methods is

evaluated by considering CNT features (such as chirality and defect distribution)

deterministically and probabilistically. By deterministic (probabilistic) simulation,

the first method reduces on average the delay by 6.968% (7.811%) while the

deviation is increased (decreased) by 32.444% (9.788%). The second method

reduces deterministically (probabilistically) on average the deviation by 44.159%

(47.476%) with 2.166% (4.409%) delay reduction.

155

In Chapter 4, novel methodology to find parameters (number, pitch, doping level,

and chirality of CNTs) which can be used in HSPICE and represent the CNT count

variation using linear programming is proposed. Simulation results shows that the

unevenly spaced CNTs can cause the increase of 19.712% and 6.328% in delay and

energy comparing to those of evenly spaced CNTs in circuit level simulation and the

number of simulation runs can be decreased to 33.9 times on average at the expense

of 6% error in representing the effect of uneven spacing between CNTs.

Based on the previously mentioned CNTFET circuit design and evaluation

methodology, in Chapter 5, two ternary CNTFET SRAM is proposed and evaluated.

First proposed ternary CNTFET SRAM shows 4.193 times (2.024 times) better

performance comparing to binary MOSFET SRAM (binary CNTFET SRAM) in

PDP aspect. Second proposed ternary CNTFET SRAM make it possible to store

0.45V on ‘q’ and ‘nq’ only by using one bit line and a word line with two kind

supply voltage (0V and 0.9V) at the expense of 3.733% more power and two more

transistors. Extensive simulations to evaluate the change of CNT density and the

effect of process variations are also performed considering the structure of MOSFET

and CNTFET. Simulation results show that 30 CNTs/um is proper for CNTFET

SRAMs and binary MOSFET SRAM shows about 10 time more sensitive to

lithographic process variation comparing to CNTFET SRAMs. It is also found that

CNT count variation make 19.324 times more performance variation comparing to

lithographic process variation in CNTFET SRAMs.

156

6.2 Future Works

In Chapter 4, to evaluate the effect of uneven space between CNTs, linear

programming methodology is proposed and the effect is evaluated in a five stage

FO4 inverter chain. To expect the effect of uneven space in more complicated and

real circuit, it is worth to run simulation in more various circuits such as basic logic

gates and ISCAS85 benchmark circuits. However, due to the different structure

between MOSFET and CNTFET, in CNTFET circuit design, more parameters such

as pitch, chirality, and number of CNTs have to be controlled carefully to optimize

the delay and power in CNTFET circuit. Therefore, new methodology to optimize

these parameters for CNTFET circuit design is necessary.

When CNTFET-based ternary SRAM is suggested in Chapter 5, previously

proposed STI inverter [38] is utilized because, due to its symmetric structure,

conventional sizing methodology for binary MOSFET SRAM can be utilized and

4.193 times (2.024 times) better performance (in PDP aspect) comparing to Binary

MOSFET (Binary CNTFET SRAM) can be achieved by controlling chirality of the

diode connected CNTFETs in the ternary SRAM. However, the number of

CNTFETs in the SRAM cell is 12. So, it is worth to reduce the number of CNTFETs

at the expense of small performance degradation. Therefore, it would be interesting

topic to design new ternary SRAM which has fewer transistors and compare its

performance to the proposed ternary CNTFET SRAMs.

157

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