Modeling VHDL Modeling VHDL in POSEin POSE

OverviewOverview

MotivationMotivation Quick Introduction to VHDLQuick Introduction to VHDL Mapping VHDL to POSE (the Mapping VHDL to POSE (the

Translator)Translator) Simulator OverviewSimulator Overview

MotivationMotivation Circuit Complexity on the Rise (# Circuit Complexity on the Rise (#

Transistors)Transistors) P4 (Prescott = 125 million, EE = 178 million)P4 (Prescott = 125 million, EE = 178 million) Athlon 64 (Venice = 114 million, X2 = 233.2 Athlon 64 (Venice = 114 million, X2 = 233.2

million)million) NVidia 7800 GTX – 302 millionNVidia 7800 GTX – 302 million ATI X1800 Series – 321 millionATI X1800 Series – 321 million

Simulation is becoming a bottleneck it the Simulation is becoming a bottleneck it the design cycle (it can take days to run a design cycle (it can take days to run a simulation)simulation)

Use multiple processors to speedup Use multiple processors to speedup simulationsimulation

OverviewOverview

MotivationMotivation Quick Introduction to VHDLQuick Introduction to VHDL Mapping VHDL to POSE (the Mapping VHDL to POSE (the

Translator)Translator) Simulator OverviewSimulator Overview

VHDL - IntroVHDL - Intro

VVHSICHSIC HHardwareardware DDescriptionescription LLanguageanguage VVeryery HHighigh SSpeedpeed IIntegratedntegrated CCircuitircuit Language for modeling ICsLanguage for modeling ICs

Two ways of describing ICsTwo ways of describing ICs Structural – Model the circuit using gate Structural – Model the circuit using gate

operatorsoperators Behavioral – Using code (ifs, loops, etc.)Behavioral – Using code (ifs, loops, etc.)

Using simulation, logic designs can Using simulation, logic designs can be verifiedbe verified

VHDL – ExampleVHDL – Example entity AND_GATE isentity AND_GATE is port (A, B: in BIT; Y: out BIT);port (A, B: in BIT; Y: out BIT); end AND_GATE;end AND_GATE;

architecture AND_GATE_struct of AND_GATE isarchitecture AND_GATE_struct of AND_GATE is beginbegin Y <= A and B;Y <= A and B; end AND_GATE_struct;end AND_GATE_struct;

VHDL – Example (II)VHDL – Example (II) entity AND_GATE isentity AND_GATE is port (A, B: in BIT; Y: out BIT);port (A, B: in BIT; Y: out BIT); end AND_GATE;end AND_GATE;

architecture AND_GATE_behav of AND_GATE isarchitecture AND_GATE_behav of AND_GATE is beginbegin process (A, B) beginprocess (A, B) begin if (A = ‘1’) and (B = ‘1’) thenif (A = ‘1’) and (B = ‘1’) then Y <= ‘1’;Y <= ‘1’; elseelse Y <= ‘0’;Y <= ‘0’; end if;end if; end process;end process; end AND_GATE_behav;end AND_GATE_behav;

VHDL – Example (III)VHDL – Example (III) entity NOT_GATE isentity NOT_GATE is port (A: in BIT; Y: out BIT);port (A: in BIT; Y: out BIT); end NOT_GATE;end NOT_GATE;

entity AND_GATE isentity AND_GATE is port (A, B: in BIT; Y: out BIT);port (A, B: in BIT; Y: out BIT); end AND_GATE;end AND_GATE;

entity NAND_GATE isentity NAND_GATE is port (A, B: in BIT; Y: out BIT);port (A, B: in BIT; Y: out BIT); end NAND_GATE;end NAND_GATE;

architecture NAND_GATE_struct of NAND_GATE isarchitecture NAND_GATE_struct of NAND_GATE is signal andOutput : BIT;signal andOutput : BIT; component NOT_GATE port (A: in BIT; Y: out BIT); end component;component NOT_GATE port (A: in BIT; Y: out BIT); end component; component AND_GATE port (A, B: in BIT; Y: out BIT); end component;component AND_GATE port (A, B: in BIT; Y: out BIT); end component; beginbegin myAndGate : AND_GATE port map (A=>A, B=>B, Y=>andOutput);myAndGate : AND_GATE port map (A=>A, B=>B, Y=>andOutput); myNotGate : NOT_GATE port map (A=>andOutput, Y=>Y);myNotGate : NOT_GATE port map (A=>andOutput, Y=>Y); end NOT_GATE_struct;end NOT_GATE_struct;

VHDL KernelVHDL Kernel Continuously loop through simulation cyclesContinuously loop through simulation cycles Simulation CyclesSimulation Cycles

Computation/ProcessingComputation/Processing Calculate simulation time for next simulation Calculate simulation time for next simulation

cycle based on ‘earliest next event’cycle based on ‘earliest next event’ If time advances, move onto next simulation cycleIf time advances, move onto next simulation cycle Otherwise, enter delta cycleOtherwise, enter delta cycle

Delta CycleDelta Cycle Similar to a Simulation Cycle but has less Similar to a Simulation Cycle but has less

computation and simulation time has not moved computation and simulation time has not moved forward from last cycle (e.g. – no postponed forward from last cycle (e.g. – no postponed processes)processes)

OverviewOverview

MotivationMotivation Quick Introduction to VHDLQuick Introduction to VHDL Mapping VHDL to POSE (the Mapping VHDL to POSE (the

Translator)Translator) Simulator OverviewSimulator Overview

TranslatorTranslator

Source (VHDL) to Source (POSE/C++)Source (VHDL) to Source (POSE/C++) Only a subset of VHDL so farOnly a subset of VHDL so far Generates POSE/Charm++/C++ CodeGenerates POSE/Charm++/C++ Code Simple checks (identifiers are valid, etc.)Simple checks (identifiers are valid, etc.) C++ provides Portable CodeC++ provides Portable Code

Mapping VHDL to C++Mapping VHDL to C++

Each Component becomes a Poser Each Component becomes a Poser (Object in C++)(Object in C++) Granularity of the simulation can be Granularity of the simulation can be

controlled by the usercontrolled by the user Signals and shared variables become Signals and shared variables become

member variablesmember variables Processes become member functionsProcesses become member functions Contexts created for each process to hold Contexts created for each process to hold

localslocals POSE Event Queues hold pending wire POSE Event Queues hold pending wire

changeschanges

Interesting ProblemsInteresting Problems

Load BalancingLoad Balancing Zero Time (Delta Cycles)Zero Time (Delta Cycles) Pausing Execution of ProcessesPausing Execution of Processes

Load BalancingLoad Balancing

The components in VHDL form a tree The components in VHDL form a tree structurestructure Components in the tree closer to the root become Components in the tree closer to the root become

locations with high communicationlocations with high communication Optimization: If value just “passes through parent node”, Optimization: If value just “passes through parent node”,

forward value to all targetsforward value to all targets Score based mappingScore based mapping

Bursts of ActivityBursts of Activity Entire portions of the simulation may go “inactive” Entire portions of the simulation may go “inactive”

for several simulation cycles and then suddenly for several simulation cycles and then suddenly become highly active because of some triggerbecome highly active because of some trigger

Phase based load balancing (hard, future work)Phase based load balancing (hard, future work)

VHDL StructureVHDL Structure

Zero Time (Delta Cycles)Zero Time (Delta Cycles)

Forward progression without moving Forward progression without moving simulation time forwardsimulation time forward Ordering of “Events” within a single Ordering of “Events” within a single

simulation cyclesimulation cycle Object Virtual Time (OVT) in POSE not Object Virtual Time (OVT) in POSE not

sufficient for this task (at least how it sufficient for this task (at least how it was intended to be used)was intended to be used)

Pausing Execution of Pausing Execution of ProcessesProcesses

Sequential Statements (Behavioral Code)Sequential Statements (Behavioral Code) Most of the sequential statements map wellMost of the sequential statements map well

if-then-else, loops, etc.if-then-else, loops, etc. The “Wait” StatementThe “Wait” Statement

A sequence of statements may need to suspendA sequence of statements may need to suspend Cannot use POSE’s “elapse( )” function to Cannot use POSE’s “elapse( )” function to

elapse time since other activity may be taking elapse time since other activity may be taking placeplace

Solution: Allows the C++ functions that Solution: Allows the C++ functions that represent the processes to suspend executionrepresent the processes to suspend execution Return at some statement and then restart after Return at some statement and then restart after

that statementthat statement To do this efficiently… use ‘goto’s and To do this efficiently… use ‘goto’s and

‘switch’s… :(‘switch’s… :(

OverviewOverview

MotivationMotivation Quick Introduction to VHDLQuick Introduction to VHDL Mapping VHDL to POSE (the Mapping VHDL to POSE (the

Translator)Translator) Simulation OverviewSimulation Overview

Simulation StructureSimulation Structure Each Component Becomes a PoserEach Component Becomes a Poser

Control messagesControl messages Signals and variables become local to PoserSignals and variables become local to Poser

Send message to self if assignment will be in the futureSend message to self if assignment will be in the future Port values are transmitted between componentsPort values are transmitted between components

Send messages to parent/child component(s)Send messages to parent/child component(s) Communication intensive (especially if Communication intensive (especially if

modeled to the gate level)modeled to the gate level) Load balancer needs to be aware of Load balancer needs to be aware of

communication costs and/or patternscommunication costs and/or patterns One VCDGenerator per ProcessorOne VCDGenerator per Processor

Handles outputHandles output

VHDL – Simulation CycleVHDL – Simulation Cycle

VHDL - SimulationVHDL - Simulation

NAND ExampleNAND Example

VHDL – Simulation Cycle VHDL – Simulation Cycle (II)(II)

Components do not need to be synchronizedComponents do not need to be synchronized Components can be optimisticComponents can be optimistic

Portions of the simulation can be ahead (in time) of other Portions of the simulation can be ahead (in time) of other portionsportions

““Optimism” is limited by strategy/POSE-Optimism” is limited by strategy/POSE-configuration and GVT calculationconfiguration and GVT calculation

Components can skip cycles where they are Components can skip cycles where they are idleidle Wakeup event allows components to skip the Wakeup event allows components to skip the

simulation cycles where they do no worksimulation cycles where they do no work Separate drive/process events allow delta cycles to Separate drive/process events allow delta cycles to

be skippedbe skipped

Future WorkFuture Work Additional support for VHDLAdditional support for VHDL Add support for VerilogAdd support for Verilog

Create a second front end that can parse VerilogCreate a second front end that can parse Verilog Allow the AST or a second IR to represent the super-set Allow the AST or a second IR to represent the super-set

of VHDL and Verilogof VHDL and Verilog Load BalancingLoad Balancing

Score-Based RefinementScore-Based Refinement Phase-BasedPhase-Based

Automatic Granularity Detection: Break apart Automatic Granularity Detection: Break apart large components or combine smaller large components or combine smaller components without making the user modify components without making the user modify codecode

And so much more…And so much more…