Department of Electroscience

Master of Science Thesis Henrik Hassander & Christian Lindholm

in cooperation withAcreo AB

February 2004

Modelling and implementation of a10-bit 80 MSPS current-steering DAC

with internal bandgap referencein a 0.18 µm CMOS process

Abstract A 10-bit quadrature differential digital to analog converter has been designed in a 0.18 µm CMOS process. This DAC is a part of the SoCTRix project at Acreo. There has been a large effort put into MATLAB modelling of DAC behaviour and errors. A design flow was built up to systemize and simplify the layout work. To minimize external components, a bandgap was implemented in the same design. The main design goal was to reach high linearity while keeping power consumption low. A secondary goal has been to keep the total chip area low. In an effort to make the DAC commercially viable it has been designed to give a high yield.

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Preface This thesis work has been carried out at Acreo AB in Lund. The thesis is part of our Master of Science degree from Lund Institute of Technology – LTH, Lund University. We would like to thank our advisors Karl Norling from Acreo, Martin Anderson from Department of Electroscience, LTH and all co-workers at Acreo. We would also like to thank our examiner at LTH, Jiren Yuan.

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1 Abbreviations........................................................................ 7 2 Introduction .......................................................................... 9

2.1 Design goals...................................................................................................9 3 Theory................................................................................. 11

3.1 DAC Theory.................................................................................................11 3.2 Performance measures .................................................................................11

3.2.1 Offset error...........................................................................................11 3.2.2 Gain error .............................................................................................12 3.2.3 Differential Nonlinearity......................................................................12 3.2.4 Integral Nonlinearity............................................................................13 3.2.5 Monotonicity........................................................................................14 3.2.6 Glitches ................................................................................................14 3.2.7 Settling time .........................................................................................14 3.2.8 Signal-to-Noise and Distortion Ratio...................................................14 3.2.9 Spurious Free Dynamic Range ............................................................14 3.2.10 Resolution ............................................................................................15 3.2.11 Accuracy ..............................................................................................15 3.2.12 Effective Number Of Bits ....................................................................15

4 DAC Architecture............................................................... 17 4.1 Choice of architecture ..................................................................................17 4.2 Current-Steering DACs................................................................................17

4.2.1 Thermometer code ...............................................................................18 4.2.2 Thermometer-Binary segmentation .....................................................18

5 Modelling of errors in a current-steering DAC................... 21 5.1 Causes of errors in current-steering DACs ..................................................21

5.1.1 Output impedance vs. SFDR................................................................21 5.1.2 Output impedance vs. gain error..........................................................21 5.1.3 Mismatch vs. SFDR.............................................................................22 5.1.4 Mismatch vs. INL ................................................................................22 5.1.5 Influence of noise on circuit performance ...........................................23 5.1.6 Influence of graded errors on performance..........................................23 5.1.7 Mismatch calculations .........................................................................24

5.2 MATLAB model..........................................................................................25 5.3 MATLAB simulations .................................................................................25

5.3.1 Simulating the nominal case ................................................................25 5.3.2 Simulating the impact of reduced matching ........................................27 5.3.3 Simulating the impact of switching schemes.......................................28 5.3.4 Simulating the impact of limited output impedance ............................30

6 System implementation ...................................................... 31 6.1 System description .......................................................................................31 6.2 Implementation of sub-circuits ....................................................................32

6.2.1 Current source......................................................................................32 6.2.2 The binary-to-thermometer decoder ....................................................35 6.2.3 Latches .................................................................................................37 6.2.4 Bandgap reference ...............................................................................40 6.2.5 Voltage-to-current converter................................................................45 6.2.6 Voltage-to-current converter bias circuitry..........................................48

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7 Results and conclusion ....................................................... 49 7.1 The complete system....................................................................................49 7.2 Challenges of system simulations................................................................49 7.3 Simulation results.........................................................................................50 7.4 Conclusions..................................................................................................50 7.5 Possible improvements for future development ..........................................51

8 Measurements ..................................................................... 53 8.1 Introduction..................................................................................................53 8.2 Static measurements.....................................................................................53 8.3 Dynamic measurements ...............................................................................54

9 References .......................................................................... 57 Appendix A............................................................................... 59 Appendix B............................................................................... 63 Appendix C............................................................................... 69

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1 Abbreviations

Abbreviation Explanation

ADC, A/D Analog-to-Digital Converter

DAC, D/A Digital-to-Analog Converter

DNL Differential Non-Linearity

DRC Design Rule Check

ENOB Effective Number Of Bits

FFT Fast Fourier Transform

INL Integral Non-Linearity

LSB Least Significant Bit

LVS Layout Versus Schematic

MSB Most Significant Bit

MSPS Mega Samples Per Second

OP Operational Amplifier

PSRR Power Supply Rejection Ratio

SE Silicon Ensemble

SFDR Spurious Free Dynamic Range

SNDR Signal to Noise and Distortion Ratio

SNR Signal to Noise Ratio

SR-flip-flop Set reset flip flop

VLSB Voltage amplitude of one quantization step

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2 Introduction

Wireless communication systems today require more and more digital signal processing. But somewhere along the line of a transmitter or a receiver there is a radio signal, an analog signal. This requires the use of a digital-to-analog converter in a transmitter or an analog-to-digital converter in a receiver. These communication systems are often mobile and thus require all of the circuits involved to have low power consumption. In IC manufacturing today, the trend is to keep shrinking the processes as much as possible. For digital circuits this is a good thing since it means smaller circuits with lower power consumption. For analog circuits however it is starting to become a bit of a problem. The smaller the process becomes the more the power supply voltage is lowered. This means that the signal headroom is decreased and the number of circuits that are possible to implement are reduced. In this thesis a DAC was designed in a 0.18 um process at Acreo AB in Lund. MATLAB models were developed to study the behavior of current-steering DACs and how different errors affects the performance. An internal reference in the form of a bandgap has also been implemented. The actual design was created and simulated in Cadence custom IC design tools.

2.1 Design goals

The goal is to design a quadrature 10-bit DAC with good linearity and low power consumption. The architecture chosen was a current-steering DAC, more information on this later on. The load was decided to be 60 Ω with a full-scale differential current of 10 mA(each output supplying 0 to 5mA). This equates to a differential voltage swing of 600 mV. The filter following the DAC set these requirements. The requirement on update rate was set to 80 MSPS.

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3 Theory

3.1 DAC Theory

The digital to analog converter converts a discrete time signal with discrete amplitude to a continuous time signal with discrete amplitude. In the case where the digital word is binary and there is a given voltage (or current) reference, the output is

∑=

−=N

kk

krefout bVV

12 ( 3.1 )

where the vector b is the binary word and N is its length (the DAC’s resolution). The minimum voltage change on the output, corresponding to a change of 1 LSB, is

Nref

LSB

VV

2= ( 3.2 )

The maximum output signal can be calculated from equation ( 3.1 ). The decimal value is

NN

k

k −

=

− −=∑ 2121

( 3.3 )

which gives the maximum output voltage

LSBrefMAX VVV −= ( 3.4 )

These equations give us the output as shown in Figure 3.1, where the input signal is a 2-bit ramp from 00 to 11.

Figure 3.1 Digital to analog conversion with a 2-bit DAC.

3.2 Performance measures

Due to nonlinearity, noise, mismatch, power supply etc, the output signal is not ideal. The unit used when defining the following errors is LSB.

3.2.1 Offset error The output when the input vector, B, is 0 is defined as the offset error, Eoffset [1].

11

( )0=

≡BLSB

outoffset V

BVE ( 3.5 )

3.2.2 Gain error The gain error is defined as the output deviation from the ideal output with a full-scale input, minus the offset error.

( ) ( ) offsetN

BLSB

outgain E

VBVE

N

−−−≡−=

1212

( 3.6 )

The offset and gain errors are described graphically in Figure 3.2.

Figure 3.2 DAC gain and offset errors.

These two errors are disregarded when describing differential and integral nonlinearity errors.

3.2.3 Differential Nonlinearity The difference between each output step of a real and an ideal DAC is the DNL error. The vector of DNL errors is

( ) ( )120

11−≤<

−−−≡

NBLSB

outoutB V

BVBVDNL ( 3.7 )

The vector’s maximum is often used in specifications to show the worst-case error.

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Figure 3.3 Transfer curve with errors on the left, and the DNL vector on the right.

3.2.4 Integral Nonlinearity The INL errors are calculated as the deviation from a straight line, which is adapted to the transfer curve. The line could be between the start and end points of the curve, or calculated with some kind of linear regression. As for the DNL, the vector’s maximum is often used to specify the INL.

Figure 3.4 INL errors compared to a straight line between start and end points.

The equation for the INL vector is

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( ) ( )120

_

−≤≤

−≡

NBLSB

fitoutoutB V

BVBVINL ( 3.8 )

where Vout_fit is the straight line from zero to full-scale. If the DNL and INL formulas are combined we get an expression for DNL and INL.

1−−= BBB INLINLDNL ( 3.9 )

∑=

+=B

kkB DNLINLINL

10 ( 3.10 )

3.2.5 Monotonicity A DAC has monotonic behaviour if the output always increases with an increasing input. Monotonicity is guaranteed if the maximum INL error is smaller than 0.5 LSB and the DNL error less than 1 LSB. The non-monotonicity often occur when the input is changed from “01…1” to “10…0” in binary weighted DAC’s.

3.2.6 Glitches If there is skew between the input bits or the clock, glitches can occur. For example, if an input word is changed from “1000” to “0111” and the MSB is slower than the other bits. Then the input is “1111” before it changes to “0111”. The LSB step will begin with a peak and then settle to the desired voltage.

3.2.7 Settling time Since the output is a step and there is always parasitic capacitance, it needs time to settle within the error margin (usually 0.5 LSB). The time it takes will limit the maximum number of samples per second.

3.2.8 Signal-to-Noise and Distortion Ratio SNDR is the most important dynamic specification. It depends on the resolution of the DAC and most of the other errors such as mismatch, nonlinearity, clock jitter, noise and settling time. SNDR can be calculated with equation ( 3.11 ), where VQ_RMS is a LSB and Vdist_RMS is the distortion.

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

++=

RMSdistRMSnoiseRMSQ

RMSout

VVV

VSNDR

_2

_2

_2

_log20 ( 3.11 )

3.2.9 Spurious Free Dynamic Range SFDR is the ratio between the signal amplitude and the largest spurious tone of the output signals’ spectrum.

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Figure 3.5 Frequency spectrum showing SFDR.

3.2.10 Resolution The resolution is defined as the number of analog levels. Which is 2N for a converter with N physical input bits. However, this does not say anything about the actual performance of the DAC.

3.2.11 Accuracy The absolute accuracy of the converter is the difference between the ideal and the actual performances, where the offset, gain and nonlinearity errors are included. Relative accuracy is the absolute accuracy without the gain and offset errors.

3.2.12 Effective Number Of Bits A converter with N-bits resolution has most likely not an accuracy of N effective bits. When calculating the ENOB, the formula for the maximum SNR with a quantized input signal is used [1].

76.102.6 += NSNR ( 3.12 )Distortion is added to the noise, which results in the equation for ENOB.

02.676.1−

=SNDRENOB ( 3.13 )

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4 DAC Architecture

4.1 Choice of architecture

There are four different architectures that are suitable for the required sampling rate.

• Pipelined • R-2R ladder • Resistor string • Current steering

The pipelined converter would need to use 10 fairly fast operational amplifiers for 10-bit operation. These would consume a lot of power to operate at the speeds required. The output from the pipelined converter is voltage and would therefore have to be converted into current in order for the next stage to work. The R-2R and resistor string architecture have the same basic flaw. It does not make efficient use of the power. This is caused by the fact that here is always a current flowing through the resistive network. It is also hard to match the resistors for 10-bit accuracy without a significant penalty in either area or power. This leaves only the current steering architecture, which is chosen because it is possible to reach 10-bit accuracy at the required speed.

4.2 Current-Steering DACs

The basic principle of a N-bit current-steering DAC is N current sources connected in parallel. The digital input word controls which source that is connected to the load. A larger digital word gives more current sources in parallel that results in a larger output signal. One big advantage with this architecture is that almost all current goes through the output, and that makes this architecture power efficient. This type of converter is also superior when it comes to high-speed D/A converters. A 1-bit differential converter is shown in Figure 4.1. The complementary input signals make the current pass through the left or the right output. The differential voltage on the output is

( )NPLout IIRV −= ( 4.1 )

Figure 4.1 A 1-bit current-steering DAC with current source and digital input b.

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The power losses for this type of converter come from generating the bias and synchronization of the input signal. This also means that the power consumption will scale fairly well with the update frequency since the power consumption in a digital net is proportional to the frequency.

4.2.1 Thermometer code A way, different from the binary, to represent a digital word is with thermometer code.

Decimal Binary Thermometer

0 000 0000000

1 001 0000001

2 010 0000011

3 011 0000111

4 100 0001111

5 101 0011111

6 110 0111111

7 111 1111111

Table 4.1 Decimal numbers coded with binary and thermometer code.

The number of bits required for the thermometer code is

12 −= BNTN ( 4.2 )

where NB is the number of binary bits. This results in a larger amount of hardware when there is a large word-length. However, the thermometer coded D/A converter also has positive qualities. For example, if a binary number changes from “100” to “011” there may be a glitch. If the same change is done with the thermometer code it just changes one bit, and this glitch problem is gone and the DNL errors are reduced. If the converters current sources have different current, the “011” level might give more current than the “100” level, which means that the converter is non monotonic. This is impossible with a fully thermometer coded current-steering converter because the number of active current sources always increases with the input, and this guarantees monotonicity.

4.2.2 Thermometer-Binary segmentation Due to fast increasing number of inputs for high accuracy fully thermometer coded DACs, it is common with segmented converters [2] where the LSBs are binary and the MSBs thermometer coded. A segmented DAC is used to get most of the advantages with fewer of the disadvantages from both coding techniques. Below are some positive and negative things about thermometer and binary coding.

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Thermometer Positive

• Low glitch energy • Monotonicity • Small DNL errors

Negative • Digital decoding with more area and power consumption • Increased number of control signals

Binary Positive

• Low digital power consumption • Smaller area • Small number of control signals

Negative • Monotonicity not guaranteed • Larger DNL errors

The price in digital power and area was rather small compared to the benefits of smaller glitch energy and DNL errors, so a split with 8 thermometer and 2 binary bits was chosen for this DAC. This results in a thermometer unit current, It, equal to four binary units, Ib. One can either represent the thermometer unit as 1 current source with 4 times the binary unit current, 2 sources with 2 times the unit current or 4 unit sources. With 1 source, the standard deviation for the transistor mismatch on a wafer is

( )σ4,4mN ∈ ( 4.3 )and with 4 sources of the same size as above

( ) ( )σσ 2,44,4 2 mmN =∈ ( 4.4 )

Therefore it is better to use 4 thermometer sources because the required matching is decreased, and it is easier to apply different layout techniques such as common-centriod. It is also easier to match the sources because they are the same size as the binary sources and they will have the same bias.

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5 Modelling of errors in a current-steering DAC

In this chapter the cause of some of the errors causing performance degradation will be discussed. Some approximate formulas for estimating performance are shown. Both static and dynamic errors are taken into consideration. A MATLAB model of a current steering DAC is shown. Some simulation results from this model are presented.

5.1 Causes of errors in current-steering DACs

5.1.1 Output impedance vs. SFDR The limited output impedance of the current source will cause an error in the output signal. This is caused by the fact that the output impedance is dependant on how many current sources that are on at any given time. This will cause a signal dependent current sharing between the load and the output impedance of the current source. It can be shown [3] that the output voltage as a function of time can be written as below:

( )

impL ZtN

R

ItNtV)1)(sin(2

)1)(sin(+

+

+=

ωω

( 5.1 )

where I is the current through one current source, RL is the load resistance, Zimp is the output impedance of one current source and N is the total number of current sources. By doing a taylor series expansion and identifying the harmonics it’s possible to decide the influence of Zimp on SFDR. The series expansion was done in maple for both the single-ended case and the differential case. In Appendix A the complete maple code can be seen for both cases. In the single-ended case the SFDR is dependant on the second order harmonic, which is the dominant overtone. In the differential case, assuming perfect matching, the second order harmonic is cancelled and the SFDR is dominated by the third overtone. The ratio between the signal and the second order harmonic in the single-ended case is, according to [3], approximately given by:

impL

imp

ZN

R

ZN

SFDR24

+= ( 5.2 )

For a 10-bit converter SFDR should be at least 60 dB. In this case with RL=60 Ω this would mean that Zimp would have to be at least 15.3 MΩ in the desired frequency range. In the differential case an output impedance of 455 kΩ is enough to meet the demands. A demand that is much easier to meet, especially if high frequency operation is desired.

5.1.2 Output impedance vs. gain error Since the current is shared between the load and the output impedance of the current source array a gain error will occur. The size of this error is decided by how many

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current sources are on and the value of the load resistor. The worst case occurs when all current sources are conducting. The full-scale gain error is easily determined by the following equation:

impL

imp

in

out

ZRZ

VV

+=

1023 ( 5.3 )

The only problem with this simple equation is that it doesn’t take the frequency dependence of Zimp into consideration. Since the frequency behaviour of Zimp is hard to determine analytically one has to rely on simulations for this.

5.1.3 Mismatch vs. SFDR Variations in the manufacturing process causes mismatch between current sources. This means that there will be a variation in current over the area of the chip. A detailed analysis has been performed in [2] and the result is shown below

2log1034

3log20 unitNSFDR σπ−+⎟

⎠⎞

⎜⎝⎛≈ ( 5.4 )

where σunit is the mismatch between current sources, for instance 4% mismatch means that σunit equals 0.04. This is only an approximate equation because it only takes the mismatch in the MSBs into account. But it gives an idea of what to expect and it can be used to calculate an approximate demand on mismatch. For an average SFDR of 65 dB in a 10-bit DAC less than 4.2 % mismatch is required.

5.1.4 Mismatch vs. INL The mismatch also affects the DC performance. The mismatch causes each current source to deliver a slightly different current. This causes non-linearity in the transfer function. To determine the tolerable mismatch based on INL performance the following equation can be used [4]

NCII

221

=σ with ⎟

⎠⎞

⎜⎝⎛ +=

25.0_ yieldnorminvC ( 5.5 )

where σI/I is the standard deviation of a unit current source, N is the number of bits, inv_norm is the inverse cumulative normal distribution and yield specifies the percentage of DACs with an INL below ½ LSB. Figure 5.1 shows the yield plotted versus the current source mismatch.

Figure 5.1 Yield versus mismatch.

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In a 10-bit DAC this means that the matching has to be around 0.5% to get a reasonable yield.

5.1.5 Influence of noise on circuit performance There are basically two types of noise on the output of the DAC. One is thermal noise from the load resistor. The other one is the noise from the current sources. The thermal noise for a resistor is given by the formula below:

BWkTRVrms ⋅= 4 ( 5.6 )

where k is Boltzmann’s constant, T is the temperature, R is the resistor value and BW is the noise bandwidth. The noise from the current source is harder to analyze analytically and therefore has to be computed from simulations. These noise sources should be compared with the quantization noise. The quantization noise exists because the input signal is quantized. The general formula for calculating the SNR caused by quantization noise is given below.

dBNV

V

SNR N

LSB

ref

76.102.6223log20

12

22log20 +=⎟⎟⎠

⎞⎜⎜⎝

⎛=

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

= ( 5.7 )

In order to calculate the total SNR of the DAC one has to add up all noise sources. The formula will then look like below

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

+⋅+=

22

1023412

22log20

IunitLOADLSB

ref

VBWkTRV

V

SNR ( 5.8 )

where VIunit is the RMS noise voltage from one current source. When the noise level is the same as the quantization noise level a 3 dB loss in SNR occurs and if the noise level is half that of the quantization noise the loss in SNR is 1 dB.

5.1.6 Influence of graded errors on performance In the above analysis the mismatch errors are assumed to be uncorrelated. This is not entirely true in a real implementation. The fabrication process causes linear graded errors. These can be caused by a linear graded thickness in gate-oxide for instance. There are also symmetrical errors caused by resistance in interconnect wires on chip. In addition to these errors there are also parabolic errors that emerge during manufacturing. All these errors degrade the performance of the DAC. To lessen the impact of these errors a hierarchical symmetric switching scheme is used as described in [5]. The basic concept is to switch the current sources so that they as a group cancel the linear and symmetrical errors. An illustration of this can be seen in Figure 5.2 below.

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Figure 5.2 Illustration of the hierarchical symmetric switching scheme.

First current source 1 is switched on and then when number 2 is switched on it cancels out the symmetrical error. Number 3 and 4 cancel their symmetrical error in the same way and together with 1 and 2 they cancel the graded error as well. As described earlier each thermometer coded current source is divided into four separate current sources. This means that there will be four arrays of 255 current sources. Each one of these arrays has their current sources placed according to the switching scheme above. To further reduce the impact of gradients a common-centroid layout scheme is used, meaning that all current sources will have a common centre. This is accomplished by mirroring the four arrays about the centre. This method works well to cancel linear gradients but does less to cancel parabolic gradients.

5.1.7 Mismatch calculations The mismatch model used was described in [6]. The reason for using this model is the fact that it has been verified by measuring on a large amount wafers so that the results are reliable. The model takes the VT and β mismatch into account where β = µCoxW/L is the current factor. The VT mismatch is modelled as follows:

WLA

VV VT

T

T 0

0

0 =σ ( 5.9 )

and β as

WLA 0β

βσβ

= ( 5.10 )

where AVT0 and Aβ are process dependent constants. This is where problems arise. To find out what value these constants have. In the best case the value of these constants are supplied by the manufacturer. If they are not one has to resort to approximations. Fortunately the constants are mostly dependent on the process technology (gate size) and not so much on the particular manufacturer. In a current-steering DAC the mismatch of interest is that between current sources. The formula below describes the mismatch in current in relation to VT and β mismatch:

2

2

20

02

2

2

)(4

ββσσσ

+−

=TGS

T

d

d

VVV

II ( 5.11 )

From this formula the current mismatch can be calculated given the size of the transistor and its bias point (overdrive voltage).

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5.2 MATLAB model

To study the impact of all the errors above together a MATLAB model was created. The model consists of three files DAC.m which is the model of the DAC, swmatris.m which generates the matrix for the switching scheme and run_DAC.m in which simulation parameters are entered. The code for these files can be seen in Appendix B. At first an ideal ADC is used to create the input signal to the DAC. Some noise is added to the input signal of the ADC to avoid spurious tones in the final spectrum. Parameters like those described above are fed into the model. These include noise, gradients and output impedance for instance. A current source matrix is created in MATLAB using the data on gradients and random errors (mismatch). An example of how this matrix may look can be seen in Figure 5.3 below.

Figure 5.3 Distribution of current in sources depending on the location on chip

What it shows is the current distribution as a function of the location on chip. To create the output current the currents from the different current sources are added according to input signal and switching scheme. The current is then converted into a voltage taking the limited output impedance into account. Finally the noise is added to the output signal. A spectrum of the output is created using an FFT. The spectrum can then be analyzed to calculate dynamic performance such as SFDR, SNDR and ENOB. The advantage of MATLAB simulations as opposed to circuit simulations is speed. MATLAB simulations are many times faster than a circuit simulator. This makes it possible to run many simulations and look at yield figures.

5.3 MATLAB simulations

During all simulations the sample frequency was kept at 80 MHz, the input signal was an 11 MHz sine wave (or ramp in the case of INL and DNL simulations). The current source output impedance has a value of 8 MΩ if nothing else is stated. The noise applied was extracted from cadence simulations and inserted into the model. The linear and parabolic gradients were arbitrarily chosen to a value that seems reasonable since there was no data available on such errors.

5.3.1 Simulating the nominal case The figures below were simulated with a current source mismatch of 0.5 % and using a hierarchical symmetric switching scheme. To look at yield figures 10000 simulations were run and the result was plotted as a histogram.

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Figure 5.4 Output spectrum.

Figure 5.5 SFDR.

Figure 5.6 ENOB.

Figure 5.7 INL.

Figure 5.8 DNL.

In Figure 5.4 a typical output spectrum from one of these simulations can be seen. Figure 5.5 shows the number of DACs with a certain SFDR. Up to around 72 dB it looks like normal distribution. After that there is a significant peak in number of DACs. This is caused by the fact that the SFDR is limited by other factors than mismatch. This causes the normal distribution to peak around 72.5 dB because there is another spurious tone that is larger than the one caused by mismatch and noise. Figure 5.6 shows the ENOB yield. It behaves more like normal distribution since it’s dependent on SNDR, which is integrated over the entire spectrum and therefore more dependent on noise and mismatch. Figure 5.7 and Figure 5.8 shows the static performance in form of INL and DNL respectively. They also behave like normal distributions although slightly skewed toward a lower value.

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5.3.2 Simulating the impact of reduced matching In the next following figures the impact of increased mismatch is shown by changing current source matching from 0.5% to 1.5%.

Figure 5.9 Output spectrum.

Figure 5.10 SFDR.

Figure 5.11 ENOB.

Figure 5.12 INL.

Figure 5.13 DNL.

In Figure 5.9 the output spectrum is shown. It shows that there are a bit more and larger spurious tones than before. Figure 5.10 shows the SFDR and it can be seen that the result is still skewed toward a higher value but there are more DACs at lower values. What is also interesting to note from this figure is that some DACs actually have better SFDR than at 0.5 % mismatch. This is due to the fact that in a few cases the mismatch actually cancels the effect of gradients. The ENOB plot in Figure 5.11 shows the same behaviour.

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Figure 5.12 and Figure 5.13 showing INL and DNL shows more of a deterioration in performance when mismatch increases. Not very many of the DACs are below the wanted level of 0.5 LSB INL. At 1.5 % mismatch the equation ( 5.5 ) shown earlier predicts that only 70 % of the DACs will be below 0.5 LSB INL. The simulations suggest that it’s even fewer than that. This is most probably caused by the gradients which aren’t taken into account in equation ( 5.5 ).

5.3.3 Simulating the impact of switching schemes The next step is to study the impact of the switching scheme. For the results below the current source matching is decreased to 0.5 % again. Instead of using the hierarchical symmetric switching scheme the current sources are just placed in increasing order so that the first current source resides in the upper left corner and the second one is one step to the right an so on. The current source matrix still comprises of four quadrants laid out in a common-centroid manner. From now on this will be referred to as the conventional switching scheme.

Figure 5.14 Output spectrum.

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Figure 5.15 SFDR.

Figure 5.16 ENOB.

Figure 5.17 INL.

Figure 5.18 DNL.

As can be seen from the spectrum in Figure 5.14 the second harmonic overtone becomes dominant and other spurs have also increased in amplitude. This is caused by gradients that are not cancelled well in the conventional switching scheme. Since a common-centroid layout is used the linear gradients are perfectly cancelled, the parabolic gradients however, are not. From Figure 5.15 showing SFDR it can be seen that the mean value has gone from around 72.5 dB to around 56 dB. That equates to a loss of 16.5 dB in SFDR. Looking at Figure 5.16, showing the ENOB, a significant loss in performance is seen here as well. It has gone from 9.8 bits to 8.8 bits, which equates to a loss of 6 dB in SNDR so it is not as bad as the SFDR. In Figure 5.17 and Figure 5.18 where INL and DNL are shown it can be seen that the INL has gone from around 0.5 LSBs to 2.9 LSBs. This is also caused by the fact that gradients aren’t cancelled well in the conventional switching scheme. The DNL however is not any different with this switching scheme. This is easily understood since DNL is the difference between two adjacent current sources. This means that the error is not that big since the distance between two sources is fairly small which means that the change in current caused by gradients will be fairly small as well.

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5.3.4 Simulating the impact of limited output impedance Another interesting simulation that can be done is testing the impact of output impedance. By lowering the output impedance in the model to 455 kΩ and looking at the output spectrum. Figure 5.19 below shows the spectrum from this simulation.

Figure 5.19 Output spectrum.

The spectrum clearly shows that the third harmonic overtone is now the dominating one as expected from the previous calculations. SFDR is around 60 dB, also expected from the calculations above.

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6 System implementation

6.1 System description

Since the DAC is meant for a zero IF transceiver, with the data stream modulated on quadrature I and Q carriers, there are actually two DACs on the same chip. A functional diagram of the DAC can be seen in Figure 6.1.

Figure 6.1 Functional diagram of the DAC.

The input signal passes through the input DFFs to make sure that the signal is in synch with the clock. It is then split up so that 2 bits are passed directly to the latches and 8 bits go through the binary-to-thermometer decoder. The binary-to-thermometer decoder generates 255 control signals, which are then put in to the latch network. From the latches the 2 binary bits are fed to their respective switch and the 255 control signals go into their switches. The switches are connected to the current sources. The main matrix consists of 1020 thermometer current sources and 3 binary current sources. When it comes to the thermometer coded current sources there are 4 sources connected to each switch. The binary switches have 1 and 2 current sources for their respective bits. The switches are placed outside the current source matrix to avoid interference between digital and analog parts. To ensure that the control signals arrive to the switches at the same time a clock tree is used to distribute the clock signal. The two DACs have a common reference for better matching between the two. The reference consists of a bandgap reference that generates a voltage, which is fed to the voltage-current converter. The bandgap has a control signal that allows an external reference to be used. This feature is realised by having a switch in series with the bandgap output, which allows the bandgap to be disconnected from the voltage-current converter. The voltage-current converter utilizes an external resistor to generate the reference current. The reason for this is that an off-chip resistor has better tolerance and less temperature dependency. It also gives the opportunity to measure

31

the voltage in that node. Since both input and output voltages from the voltage-to-current converter are measurable the offset voltage in it can be calculated.

6.2 Implementation of sub-circuits

The sub-circuits in this chapter are tested under widely varying conditions. The first step is usually to test on a schematic level. When a working circuit is made on the schematic level a layout is created. From this layout the parasitic resistances and capacitances are extracted. A simulation is done to see that the layout version behaves the same as the schematic or at a level that is acceptable. To make sure that the final fabricated circuit will work it is tested in the corners of the process. A corner is defined as a worst case of sorts. It can be either a high/low temperature or some maximum/minimum value specified in the process from the manufacturer or a minimum/maximum supply voltage. The manufacturer guarantees that all process variables will be within a certain interval and the corner defines the end point of this interval. The process corners in this report are specified as typical, ff, ss, sf and fs where typical is as the name implies the typical case. The rest are defined as where a transistor N- or P-MOS is either fast or slow. For example ss means that both N- and P-MOS are at their slowest. On top of this there is usually a worst-case corner as well. In an amplifier this is usually ss, maximum temperature and minimum supply voltage because this will give a minimum amount of voltage swing and slowest performance.

6.2.1 Current source The main task for the current source is to provide a constant current over the entire frequency and output voltage range. This means that the output impedance should be as large as possible.

6.2.1.1 Theory In its simplest form a current source for a differential current-steering DAC might look like in Figure 6.2 below.

Figure 6.2 A simple current source.

The top transistor PM0 is the current source and PM1 and PM2 are the switches. The signals driving the switches are complementary so that only one of the two switches is on at any given time. The problem with the simple current source is its limited output impedance. The output impedance can be increased by cascoding the current source. In Figure 6.3 a cascode current source is shown.

32

Figure 6.3 A cascoded current source.

In order to bias this current source and get the maximum possible voltage swing available on the output, a wide-swing architecture is used [1]. It works by biasing PM0 so that its drain-source voltage is as close to the minimum voltage possible without going into the triode region. In order to achieve this the bias circuit shown in Figure 6.4 is used.

Figure 6.4 Bias generation circuit.

6.2.1.2 Implementation The size of the current source transistor is determined by mismatch calculations. It has to have a certain area to achieve the required matching as described in section 5.1.7. The size of the cascode is determined by simulations to achieve maximum output impedance. The cascode will also have some impact on matching but the exact numbers are hard to determine. The switches are made as small as possible to reduce glitches on the output. One difference from the theory above is the fact that there are four current sources connected to each switch for layout technical reasons. When it comes to the bias circuitry there are some differences from the theory above. Since there are only four bias circuits per DAC, because of area and power constraints, each bias circuit is loaded by 255 current sources. To keep the reference voltages stable the current in each bias circuit is 8 times the current in one current source. This lowers the output impedance of the bias circuit. To further help keeping the voltage stable both Vb1 and Vb2 are decoupled to VDD_A. The reason for connecting the decoupling capacitor to VDD instead of GND is that the output current is determined by Vgs-PM0, which is referred to VDD.

6.2.1.3 Results Shown in Figure 6.5 is the result from a simulation on output impedance. In order to achieve 10-bit performance the output impedance in one current source has to be larger than 455 kΩ. The smallest unit is four current sources connected through one switch and that is what has been simulated. This means that in the figure below the

33

value has to be above 113,75 kΩ in order to achieve 10-bit performance. This is true for all frequencies below 635 MHz. Which means that theoretically this is the limit on the analog bandwidth. This limited output impedance causes a gain error at higher frequencies as described earlier. In Table 6.1 the gain error in % can be seen versus frequency. Another important parameter when it comes to the current source is the amount of noise that one current source produce. As describe earlier in section 5.1.5 the noise level has to be lower than the quantization noise. Simulations show that one current source has about 303 nV RMS noise. Using equation ( 5.8 ) one can calculate the SNR of the DAC. The load resistor is 60 Ω and differentially this equates to a voltage noise of 8.9 µV RMS with a bandwidth of 40 MHz. The quantization noise has a value of 169 µV RMS with a 600 mV full-scale voltage. Putting these numbers into the equation for SNR yields a value of 61.94 dB, which is very close to the theoretical maximum of 61.96 dB.

Figure 6.5 Output impedance versus frequency.

Output frequency [MHz] Gain error [%]

1 0.02

8.125 0.2

16 0.38

32 0.77

64 1.53

128 2.95

256 5.66

Table 6.1 Gain error versus frequency.

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6.2.2 The binary-to-thermometer decoder

6.2.2.1 Theory A systematic approach of the binary to thermometer decoder is based on a 2-bit converter [7]. To increase the number of binary inputs, a new logic level is added for each extra bit. Truth tables and De Morgan’s laws are used between every stage to find the optimum number of gates.

Figure 6.6 A 2-bit inverting binary to thermometer decoder.

This results in an arbitrary equation for every level of even or odd binary bits. The equations are shown below. The left equation is for even, and the right for odd bits. N is the number of binary bits, and tx inside the brackets is the output from the previous stage.

⎪⎪⎩

⎪⎪⎨

⎧

−≤<−⋅

−=

−<≤+

=−

−−

−−

−−

− 1212,

12,

120,

112

11

11

1NN

Nx

NN

NNx

x

xbt

xb

xbt

t

N

( 6.1 )

⎪⎪⎩

⎪⎪⎨

⎧

−≤<−+

−=

−<≤⋅

=−

−−

−−

−−

− 1212,

12,

120,

112

11

11

1NN

Nx

NN

NNx

x

xbt

xb

xbt

t

N

( 6.2 )

This method makes it easy to automatically generate a schematic with the desired number of inputs.

Figure 6.7 Even respectively odd binary number of inputs at schematic level.

35

6.2.2.2 Design A SKILL script was written to generate the decoder schematic. The script can be found in Appendix C. When adding an input bit, it gets a large fan-out, . In this 8-bit converter the binary MSB’s were buffered to compensate for the increasing rise and fall time.

12 −N

Verilog-XL produces a verilog netlist when a simulation is executed, and that netlist was used to import the design into Silicon Ensemble. The matrix signals must be rearranged somewhere between the Flip-Flops and switches to fit our switching scheme. To facilitate the layout work, the output pins placements were changed in SE. By combining GDS and DEF-exports from SE, the design was imported back to Cadence Virtuoso for DRC, extraction, LVS, simulation and some post route optimization [8].

Figure 6.8 Design flow for the binary to thermometer decoder.

6.2.2.3 Results The simulated maximum delay through the decoder was 645 ps on a schematic level, which is more than enough with our clock strategy. Since there is a delay of 50 ps between the clock to the flip-flops and the latches the actual delay will be 695 ps. This delay sets the DAC’s highest update rate to 720 MHz. The extra delay is there to make sure that the latch is in its non-transparent mode when new data is clocked in. The flip-flop is triggered on the positive edge and the latch is in its transparent mode when the clock is high and in its latched mode when the clock is low.

36

Figure 6.9 The decoder’s maximum tolerated delay at 80 MSPS.

6.2.3 Latches

6.2.3.1 Theory A matrix of latches is used to synchronize all thermometer-coded bits with the binary ones. The output bits are differential and connected to the switch array. The outputs are designed to switch on one side before it switches off the other because we want to keep the current sources from turning off during switching. The outputs intersect just above zero volts since the switches are made with PMOS transistors.

Figure 6.10 Desired outputs from the latches.

8 bits converted to thermometer code and 2 binary bits results in 257 latches, which will dominate the total digital power consumption. This, combined with the desired intersection point of the outputs, made it impossible to use standard cells.

6.2.3.2 Design The latch is based on a modified clocked SR-flip-flop [9]. The set and reset inputs are replaced with data and inverted data, D and DN in Figure 6.11 below.

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Figure 6.11 Schematic of the latch.

The first inverters have slow N and fast P-transistors to delay signals with rising edges, and the last inverters buffers the outputs. NM8 and NM9, the clock transistors, are minimum size to reduce clock feed through. The buffers also contribute to this. The current source matrix layout sets the switch array height, which is equal to the height of the latches to simplify their connections. There are 32 rows of latches in the array, the same as the switches and current sources. Since there are 8 thermometer and 2 binary bits, it results in 8 latches per row, and one row with an extra latch. To prevent skew between the outputs of this large block, a clock tree was implemented.

6.2.3.3 Results The output delays when receiving a positive edge from the clock tree are shown in Table 6.2. The arrows stand for rising or falling edges of the signal.

clk ↑ t [ps]

D ↑ 225

DN ↓ 163

D ↓ 216

DN ↑ 291

Table 6.2 The maximum output delay without clock tree.

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The switch is on when Vg drops below 180 mV, which is the maximum required intersection point. This was achieved at all corners. See Table 6.3.

Intersection point [mV] VDD [V]

T [°C]

Typical ss sf fs ff

0 6 4 30 4 9 1.65

110 17 11 68 7 26

0 9 6 44 5 14

27 12 8 52 6 17 1.8

110 25 17 86 11 36

0 13 9 56 6 19 1.9

110 30 22 100 13 44

Table 6.3 The intersection points at all process and environmental corners.

There is clock feed through when data is stored on the latch. The first inverter reduces this spike by 23.4 dB. And the buffer decreases it with 17.3 dB.

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6.2.4 Bandgap reference

6.2.4.1 Theory The basic idea behind a bandgap reference is to create a stable voltage reference independent of process variations and temperature. The basic principle of the bandgap is to use a forward biased diode (base-emitter junction) as a base for the reference voltage. Because the voltage over the base-emitter junction has a negative temperature coefficient one has to compensate for this by adding a voltage that is proportional to absolute temperature (PTAT). The PTAT is realized by amplifying the voltage difference between two forward biased junctions biased at different current densities. Figure 6.12 below shows the conventional bandgap architecture in a CMOS process. Although independent bipolar transistors are not available in CMOS, well transistors with their collector connected to the substrate (ground in a p- substrate) usually are.

Figure 6.12 The conventional bandgap architecture.

It can be shown [1] that to get a zero temperature coefficient at some temperature T the following demand must be met:

( ) ( ) 01ln1ln1 0

1

2020

0

=⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟

⎠⎞

⎜⎝⎛−+⎟⎟

⎠

⎞⎜⎜⎝

⎛+−=

∂∂

− TT

qkm

JJ

qkKVV

TTV

GBEref ( 6.3 )

where T0 is the reference temperature, VBE0-2 is the base emitter voltage for Q2 at the reference temperature, K is a factor dependent on the different current densities, k is Boltzmann’s constant, q is the elementary charge and m is a temperature constant approximately equal to 2.3. By solving ( 6.3 ) and identifying Vref it can be shown that:

( )q

kTmVV Gref0

00 1−+=− ( 6.4 )

where VG0 is the bandgap voltage of silicon at 0 K (equal to 1.206 V). In the case where T0 = 300 K this implies that:

VVref 24.10 =− ( 6.5 )

for zero temperature dependence. Which is basically the bandgap voltage plus a correction term for second order effects, hence the name bandgap reference for this type of reference. The problem with the conventional bandgap is that in a 0.18 µm process the 1.24 V output voltage referred to ground leaves little headroom to the supply voltage, which normally sits at 1.8 V. In the DAC, the bandgap reference voltage is fed to a voltage-

40

to-current converter, which creates the reference current for the current sources. Since getting this converter to work with an input voltage that close to the supply voltage is fairly hard it is desirable to have an output voltage from the reference that is closer to ground. For reasons stated above the architecture chosen for the bandgap is a low-voltage one [10]. The advantage with this kind of architecture is that it gives a larger margin to the supply voltage. Another nice feature of this architecture is the fact that the output voltage is easily changed.

6.2.4.2 Implementation The low voltage architecture implemented is shown below in Figure 6.13. The basic principle of this architecture is the same as for the conventional one. It uses two junctions biased at different current densities. Since PM1 and PM3 are biased equally and are of the same size the current through Q0 and Q1 is identical. To get a different current density through Q0 and Q1 transistor Q1 is made larger than Q0. Practically, this is solved by paralleling a number of identical devices. The output voltage from the bandgap can, according to [10], be written as:

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

52

03 R

dVR

VRV ff

ref ( 6.6 )

where Vf0 is the voltage over Q0 and dVf is the voltage over R5. For a more detailed description of the bandgap see [10]. As seen from ( 6.6 ) the output voltage is only dependent on the ratio between the resistors and not on the absolute value.

Figure 6.13 Schematic of the low-voltage bandgap architecture.

Other things that can be noticed in the schematic are the three rightmost transistors that work as a startup circuit for the bandgap. It is simply made up of an inverter where PM5 has a small W/L ratio and NM1 has a fairly large W/L ratio. If Vref is lower than the threshold voltage for NM1 the inverter output will go high which will turn on transistor NM5. NM5 pulls the gate voltages on PM1, PM2 and PM3 low, which force the bandgap to reach its normal bias point. When the output reaches its nominal value the inverter will go low and turn off NM5 and the bandgap returns to its normal operation. Another detail to be noted is C0, which sits there to stabilize the circuit.

41

With this type of circuit in an on-chip environment it’s hard to analytically calculate the values of the resistors. This is because the resistor values are also dependent on temperature. To solve this problem the optimizer function in cadence was utilized. It works by giving it a number of variables to sweep and a few demands to meet. In this particular case the values of R4 and R2 were set and R5 and R3 were swept. The demands to meet were set as an absolute value as close to 500 mV as possible and Vref-max –Vref-min lower than 300 µV from 0 to 110º C. During the layout phase a few things were taken into consideration. Since the ratios between the resistors sets the output voltage and also affects the temperature stability it’s important that the resistors are well matched. To assure adequate matching the resistors were divided into unit blocks of similar size. These unit blocks are then distributed evenly over the total area that the array of resistors consumes. To ensure that the matching is adequate after all the unit blocks are connected together one has to consider the impact of parasitic resistance. The parasitic resistance comes from interconnect wires and contacts. The resistor array has been laid out so that the relative error caused by parasitic resistance is the same for all resistors. The bipolar transistors also have to be well matched. To ensure good matching a common centroid layout scheme was used. By placing Q0, which is a single transistor, in the middle and the individual blocks that make up Q1 around it a square matrix with a common centre for both Q0 and Q1 was created. An outer ring of dummy transistors ensures that all transistors have an equal surrounding environment.

6.2.4.3 Results Simulations were run over the specified temperature range of 0-110 ºC to verify its function. In Figure 6.14 below the output voltage vs. temperature can be seen in the typical case with a supply voltage of 1.8 V. Simulations were also run in the different process corners and different supply voltages to make sure that the bandgap operates properly under worst case conditions. The results of these simulations can be seen in Table 6.4 below. For future reference it was also interesting to see how low the supply voltage could go before the output strays to far from the nominal value. The result of this can be seen in Figure 6.15 below. The conclusions that can be drawn from this figure is that the bandgap works very well down to around 1.2 V supply voltage. The influence of power supply noise was investigated by looking at the power supply rejection ratio, PSRR. The simulation was run with an external capacitor of 470 pF through a model of the bond wire. A plot of PSRR versus frequency can be seen in Figure 6.16. The PSRR is good at low and medium frequencies. At low frequencies because the opamp gain is high there and the feedback loop will eliminate a lot of the noise. At medium frequencies the capacitor on the output will attenuate the noise. At high frequencies it’s very hard to eliminate the noise because the external capacitor’s effectiveness is limited by the bond wire. Finally a test was made to see how long it takes for the output voltage to stabilize after power on. The simulation was done with an off-chip capacitor with a value of 470 pF. This value was chosen because up to this value the increase in PSRR is notable. Any larger than this provides very little gain in PSRR and only increases startup time. The result is shown in Figure 6.17 below. The first part of the curve is where the startup circuit is still on and provides extra current to charge the external capacitor. Around 350 mV the startup circuit deactivates and the capacitor is charged with a constant current.

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Figure 6.14 Reference output voltage versus temperature.

Corner VDD [ V ] Absolute

resistance variation

Vout @ 27 °C

[mV]

∆Vout for 0 –110 °C

[mV]

∆Vout/(Vout @ 27 °C)

[%]

Power consumption

@ 27 °C [µW]

typical 1.65 -15 % 502.4 0.73 0.15 166

typical 1.8 -15 % 502.3 0.85 0.17 185

typical 1.9 -15 % 502.2 0.9 0.18 199

typical 1.65 0 % 500.3 0.33 0.066 160

typical 1.8 0 % 500.2 0.28 0.056 179

typical 1.9 0 % 500.2 0.3 0.060 193

typical 1.65 + 15 % 499.0 0.64 0.13 156

typical 1.8 + 15 % 498.9 0.57 0.11 174

typical 1.9 + 15 % 498.9 0.53 0.11 187

ss 1.9 -15 % 502.2 0.9 0.18 195

ff 1.9 -15 % 502.2 0.9 0.18 201

sf 1.9 -15 % 502.3 0.9 0.18 202

fs 1.9 -15 % 502.1 0.9 0.18 193

Table 6.4 Output voltage and relative error in different process corners.

43

Figure 6.15 Output voltage versus supply voltage.

Figure 6.16 PSRR versus frequency.

Figure 6.17 Transient response during startup.

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6.2.5 Voltage-to-current converter

6.2.5.1 Theory Since the reference has a voltage output and a current reference is needed for the current sources a design is needed to convert between the two. Figure 6.18 below shows the basic concept behind the converter [11].

Figure 6.18 Schematic of voltage-to-current converer

The same basic function could be performed using only the transistor and resistor. However it would not be as accurate and not as temperature stable. The simple circuit would have a transfer function like below:

inm

ref VRgR

I ⎟⎟⎠

⎞⎜⎜⎝

⎛+

=/1111 ( 6.7 )

So what the opamp in the above figure does, is to work as a gain-boost for the transistor and it essentially increases the transconductance of the overall circuit so that the transfer function looks like below instead:

in

m

ref V

RgAR

I

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

⎟⎟⎠

⎞⎜⎜⎝

⎛++

=1111

11 ( 6.8 )

where A is the open-loop gain of the opamp. If the gain is large enough it can be approximated by:

RVI in

ref = ( 6.9 )

so that the current is only dependent on the input voltage and the resistor value.

6.2.5.2 Implementation In this design the opamp was realized with a folded-cascode architecture [11]. The advantage of this is that the converter is fully functional down to 0 V input voltage. In Figure 6.19 the schematic of the converter is shown.

45

Figure 6.19 Schematic of the complete voltage-to-current converter

The purpose of the converter is, as stated, to generate the reference currents for the DAC. Each DAC needs 8 reference currents since the bias is distributed over the chip. Since there are two DACs the total number of currents needed is 16. In Figure 6.19, only three of these are shown. To generate all these currents the output current from the converter is mirrored through PM11 and PM12 down to NM20, which forms a current mirror with the 16 output transistors. The capacitor on the output of the opamp is there to stabilize the circuit. Since Vout is fed to an off-chip resistor it will have to pass through a bond-wire. This will make the whole circuit susceptible to instability by decreasing the phase margin. It is therefore important to make the capacitor slightly larger than it would be with an on-chip resistor.

6.2.5.3 Results Important things to check for in a design like this are stability, linearity and temperature stability. In Figure 6.20 below the AC response is shown. Phase margin in this figure is around 82º. With a model of the bond wire and external parasitic capacitance connected to Vout, phase margin is degraded to around 75º leaving plenty of margin for unforeseen effects. Linearity in this case means how well the output current tracks the input voltage. The easiest way to verify this is by looking at the output voltage versus input voltage since the voltage over the resistor determines the output current. The results of this can be seen in Figure 6.21. The converter is linear within 0.5% from 100 mV to 850 mV. The error around its intended working voltage of 500 mV is 0.02%. The degradation in performance at lower and higher voltages is caused by lower loop-gain in the opamp when its output voltage comes closer to the supply. Temperature versus out current if plotted in Figure 6.22. It shows that the output current changes around 90 nA from 0-110ºC. This equates to a 0.2 % change in output current.

46

Figure 6.20 Bode plot of the voltage-to-current converter

Figure 6.21 Output versus input voltage

Figure 6.22 Reference current versus temperature

47

6.2.6 Voltage-to-current converter bias circuitry

6.2.6.1 Theory The opamp used in the V-I converter is a folded-cascode architecture. This means that it needs four different bias voltages. Two for the current source on the N- and P-side respectively and two for the cascodes on each side. The bias net used is depicted in Figure 6.23 below.

Figure 6.23 Schematic of the bias circuitry.

This type of bias circuit is called stable transconductance [1]. This is because it keeps gm of the transistors in the opamp stable regardless of supply voltage, process and temperature variations. It works by stabilizing the transistors transconductance to the resistors conductance as shown in [1].

6.2.6.2 Implementation The four rightmost transistors work as a startup circuit. The startup circuit is necessary because the bias circuitry has two stable states, one being its normal operating region the other being zero current. R0 is the resistor that stabilizes the transistor transconductance. In this case it’s realized with an on-chip resistor. It could be realized with an off-chip resistor but the external parasitics can cause oscillation. The disadvantage to using an on-chip resistor is the fact that its value is dependant on temperature and that its absolute value will have a large variation. The temperature coefficient is fairly low and shouldn’t be a problem though.

6.2.6.3 Results The performance aspects of interest can only be tested together with the V-I converter. If it works the way it’s supposed to it shouldn’t have any effect on the performance of the V-I converter.

48

7 Results and conclusion

7.1 The complete system

A layout of the complete system can be seen in Figure 7.1 below.

Figure 7.1 Layout of the complete chip

The bandgap reference and voltage-to-current converter resides in the middle of the chip. On each side of it there is one DAC, one for the I-channel and one for the Q-channel as described earlier. The lower part of the DAC is the current source matrix. The part above that, that resembles an arrow, is just the interconnect wiring from the matrix to the switches. The next part above that consists of switches, latches, digital decoding net and DFFs. Everything outside the main layout consists of decoupling capacitors.

7.2 Challenges of system simulations

The complete quadrature DAC and bandgap ends up being around 19000 transistors. This makes simulations on the complete system fairly difficult and mostly time consuming. It is not too difficult on a schematic level but the results provided from it are not good enough to accurately predict the final chip behavior. This is because parasitics in interconnect wires and circuits to a large extent determine the performance of the system. The problem encountered when trying to simulate with extracted parasitics is that it is extremely time consuming. Another problem is the fact that the layout of the complete system is so complex that the extraction tools can not do an extraction of the whole chip. The only way to get somewhat accurate results is by running the most critical blocks with extracted parasitics and less critical blocks in schematic.

49

Another difficulty during the final stages of simulation is the impact of bond wires on performance. This is mainly because there are no good models for the bond wires and a small change in the model leads to large changes in performance.

7.3 Simulation results

The DAC was tested with the specified load of 60 Ω at 80 MSPS. The input signal was an 11 MHz sine wave. The outcome of this simulation can be seen in Figure 7.2.

Figure 7.2 Differential sine wave current output.

As can be seen from this plot the response is fairly controlled with some minor glitches before a transition. The simulation was done without bond wires for reasons explained earlier. Estimated power consumption is around 22 mW for both DACs and bandgap reference. Of these 22 mW 2mW is consumed in the digital parts and 20 mW is consumed in the analog parts. The power wasted in the pads is not included in this figure.

7.4 Conclusions

Is has been shown that it’s possible to design a 10-bit DAC in a 0.18µm CMOS process. It has been shown that there are three limits on the update rate of the converter and one of them will decide the final update rate. The first limit is output impedance, which places a limit on the highest output frequency that can be reproduced without too much distortion. This doesn’t really limit the update rate unless operation up to Nyquist is wanted. In this converter the maximum output frequency is limited to 635 MHz, which, if operation up to Nyquist is desired, limits the update frequency to 1.27 GHz. The second limit is imposed by the digital net because of its delay. The data from the digital net must be available within half a clock cycle. The delay through the digital net is 695 ps, which limits the update rate to 720 MHz. Another limiting factor is the slew-rate of the output or settling time. The DAC has to settle before the next step is taken. The settling time is around 2 ns, which limits the update frequency to 500 MHz. Finally there is actually one more limit on

50

update frequency that is much harder to decide. That is the one caused by noise on supply lines and ringing on the output both of which are caused by bond wires. The biggest challenge is to accurately model all errors that are not shown in a circuit simulator such as noise and mismatch. There are also many other unknown factors that might degrade performance such as substrate coupling, crosstalk between digital and analog and the impact of bond wires.

7.5 Possible improvements for future development

The most probable cause of error in the chip is power supply noise. Preliminary simulations show that noise from the digital supply can get coupled over to the output signal. So in future versions some way of isolating the digital supply from the analog parts might have to be implemented. Measurements will show how much of a problem this really is.

51

52

8 Measurements

8.1 Introduction

All measurements have been performed with a single-ended load of 50 Ω and a full-scale current of 5 mA. During dynamic measurements the differential signal was converted to a single-ended signal using a balun. The output signal was analyzed using a spectrum analyzer. During the static measurements the differential-to-single-ended conversion was done with a precision opamp and the output was measured with a multimeter.

8.2 Static measurements

To verify the function of the bandgap reference its output voltage was measured on two different chips. The nominal output was 500 mV. On one chip it was measured to 499 mV and the other was measured to 511 mV. INL and DNL were measured by using a ramp as input signal to the DACs. The results are presented below:

Figure 8.1 I-DAC DNL Figure 8.2 Q-DAC DNL

Figure 8.3 I-DAC INL Figure 8.4 Q-DAC INL

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As can be seen DNL is within ±0.4 LSB and INL within ±0.6. Due to noise during the measurements the measured results are slightly pessimistic. To make more accurate measurements it would have been preferable if one could have taken the mean value of several measurements instead of just one. Due to time constraints this was not possible, however, a short measurement series was done by taking the mean value of 4 measurements on each level for the first 100 data values. It could be seen that the performance was slightly better than the one presented above.

8.3 Dynamic measurements

To determine the DACs dynamic performance SFDR, THD, SNDR and ENOB were measured. The results from these measurements can be seen below:

SFDR [dBc] @ fsignal [MHz]

40 [MSPS] 80 [MSPS] 125 [MSPS] 175 [MSPS]

0.756 78 77 77

1.7 73 73 73 73

3.3 73 72 71

5.5 67 68 69 67

7.3 65 70 68

9.7 60 69 67 63

13 57 66 65

17 54 62 65 62

22 61 61

37 55 54 58

47 57

61 52 52

86 49

Table 8.1 Measured SFDR performance at different update rates

THD [dB] @ fsignal

[MHz] 40 [MSPS] 80 [MSPS] 125 [MSPS] 175 [MSPS]

0.756 -72.2 -71.4 -71.0

1.7 -67.4 -70.8 -69.2 -68.0

3.3 -68.0 -68.4 -66.9

5.5 -64.6 -63.9 -61.9

7.3 -62.7

9.7 -60.0

Table 8.2 Measured THD performance at different update rates

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Figure 8.5 ENOB versus signal frequency

From Table 8.1 and 8.2 it can be seen that the performance is good for all but the highest frequencies. Figure 8.5 shows the ENOB versus signal frequency at 80 MSPS. It can be seen that the performance is good all the way up to 22 MHz. There were some problems during the measurements with the equipment used. Due to the fact that the clock from the pattern generator deteriorated the performance an external clock source was used. The external source triggered the pattern generator, which sent the data to the DAC. It proved to be difficult getting this to work perfectly due to the internal delay of the pattern generator. This might have caused some deterioration of the measured performance.

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Below some typical output spectrums are presented:

Figure 8.6 Measured output spectrum at 80 MSPS with a 9.7 Mhz input signal

Figure 8.7 Measured output spectrum at 80 MSPS with a 22 Mhz input signal

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9 References

[1] David A. Johns and Ken Martin, ”Analog Integrated Circuit Design”, John Wiley & Sons Inc, ISBN 0-471-14448-7.

[2] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, “CMOS Data Converters for Communications”, Kluwer Academic Publishers, 2000, ISBN 0-7923-7780-X.

[3] A. Van den Bosch, M. Steyaert & W. Sansen “SFDR-Bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters”, in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999, pp.1193 –1196.

[4] Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert and Willy Sansen, ”A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter”, IEEE Journal of Solid-state Circuits Vol. 36, March 2001.

[5] Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh and Nobuharu Yazawa, ”A 10-b 70-MS/s CMOS D/A Converter”, IEEE Journal of Solid-state Circuits Vol. 26, April 1991.

[6] Marcel J. M. Pelgrom, AAD C. J. Duinmaijer, Anton P. G. Welbers, ”Matching Properties of MOS Transistors”, IEEE Journal of Solid-state Circuits Vol. 24, October 1989.

[7] K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, and J. Jacob Wikner, “A 14-Bit Dual Current-Steering DAC”, SSoCC, 2003.

[8] H. Hassander and C. Lindholm, ”Simulering, layout och verifiering av mixed-mode-kretsar i Cadence”, Del av rapport i IC-projekt – Electroscience LTH , Maj 2003.

[9] Jan M. Rabaey, “Digital Integrated Circuits a Design Perspective”, Prentice Hall International, 1996, ISBN 0-13-394271-6.

[10] Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi and Koji Sakui, ”A CMOS Bandgap Reference Circuit with Sub-1-V Operation”, IEEE Journal of Solid-state Circuits Vol. 34, May 1999.

[11] Johan H. Huijsing, “Operational Amplifiers Theory and Design”, Kluwer Academic Publishers, 2001, ISBN 0-7923-7248-0.

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Appendix A

The following pages shows the Taylor expansion done in Maple. The first one is the single-ended case and the other one is the differential. Single-ended: //The output signal as a function of gimp=1/Rl > f:=N*Ir*(x+1)/(2*gl+gimp*N*(x+1));

//Taylor expansion to the 5th order > tay:=mtaylor(f,x,5);

//Replace x with sin(wt) to be able to identify harmonics > tayt:=subs(x=sin(wt),tay);

//Break out all terms containing sin or cos > tayc:=combine(tayt,trig);

//Calculate the coefficient for cos*(2wt) which is the //second harmonic > HDS:=coeff(tayc,cos(2*wt));

//Calculate the coefficient for sin(wt) which is the //signal > A:=coeff(tayc,sin(wt));

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//Set the demand on SFDR to at least 60 db > Q:=simplify(HDS/A)=.001;

//Load equals 60 ohms > gl:=1/60;

//10 bits gives N=1024 > N:=1024;

//Solve for gimp > gimp:=fsolve(Q,gimp);

//The minimum needed output impedance becomes > R:=1/gimp;

Differential: //The output signal as a function of gimp=1/Rl > f:=N*Ir*(x+1)/(2*gl+gimp*N*(x+1));

//The complementary output signal > fc:=-subs(x=-x,f);

//Taylor expansion to the 7th order > tay:=mtaylor(f,x,7);

//Taylor expansion to the 7th order of the complement > tayc:=mtaylor(fc,x,7);

//Create the differential signal. Removes odd order //harmonics > taydiff:=tay+tayc;

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//Replace x with sin(wt) to be able to identify harmonics > tayt:=subs(x=sin(wt),taydiff);

//Break out all terms containing sin or cos > taycomb:=combine(tayt,trig);

//Calculate the coefficient for sin(3wt) which is the //third harmonic > HDS:=-coeff(taycomb,sin(3*wt));

//Calculate the coefficient for sin(wt) which is the //signal > A:=coeff(taycomb,sin(wt));

//Set minimum SFDR to 60 dB > Q:=simplify(HDS/A)=0.001;

//Set load to 60 ohms > gl:=1/60;

//10 bits gives N=1024 > N:=1024;

//Solve for gimp > gimp:=fsolve(Q,gimp);

//The minimum needed output impedance becomes > R:=1/gimp;

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Appendix B

Here are the MATLAB programs that were written to simulate the function and the impact of different errors on the DAC. function [SFDRar,nobbar,maxinl,maxdnl,Itot]= DAC(nSample,Fsamp,Fsig,overtoner,noit,funk,sv); %ADC %Ramp if (funk==1) data = [0:1:1023]; end %Sin if (funk==2) w = 2*pi*Fsig; tid = [0:nSample-1]./Fsamp; brus = 0.3*rand(size(tid)); data = round(1023*(1+sin(w*tid))/2+brus); end %OFDM if (funk==3) Fsig=(312.5e3:312.5e3:26*312.5e3); w=2*pi.*Fsig; tid=[0:nSample-1]./Fsamp; phi=2*pi*rand(26); sig=zeros(26,nSample); for i=1:26 sig(i,:)=0.07807*sin(w(i)*tid+phi(i)); end sigtot=sum(sig); brus = 0.3*rand(size(tid)); data = round(1023*(1+sigtot)/2+brus); end %DAC Rimp = 8e6;%Vid 20 MHz Rl= 60; N =1023; Iref=5e-3/N; sd=0.502/100; gradient=4/400; gradpolx=5/400; gradpoly=5/400; Lnoise=6.3e-6; Inoise=3.03e-7; %Konventionell symmetrisk matris %i=1; %for k=1:16 % for l=1:16 % imatris(k,l)=i;

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% i =i+1; % end %end %Generera hierarkiskt switchad matris [imatris]=swmatris; %Generera gradienter t=[-1:2/31:1]; xpolgrad=-gradpolx*t.^2-gradpolx; ypolgrad=-gradpoly*t.^2+gradpoly; xgrad=[0.5-gradient:2*gradient/31:0.5+gradient]+xpolgrad; ygrad=[0.5-gradient:2*gradient/31:0.5+gradient]+ypolgrad; for k=1:32 for l=1:32 gradmat(k,l)=xgrad(k)+ygrad(l); end end %Sortera strömmatrisen så att koordinaterna för källa 1 ligger först i vektorn ims for k=1:255 [a,b]=find(imatris==k); ims(k,:)=[a,b]; end imsp=ims; imsn=flipud(ims); %Starta iterationsprocessen for j=1:noit %Generera strömkällor Irefs=Iref+Iref*sd*randn(32,32); Ibin=Iref+Iref*sd*rand(1,3); Ibinp=Ibin; Ibinn=fliplr(Ibinp); Itot=Irefs.*gradmat; %Spara strömmatrisen if (sv==1) save strom_matris Itot else load strom_matris end %Generera brus Noisetot=sqrt(N*Inoise^2+2*Lnoise^2)*randn(size(data)); %Räkna fram total ström genom att räkna fram varje summa av strömkällor Iutsump=zeros(1,1024); Iutsumn=zeros(1,1024); for i=1:4:1020 for k=1:3 Iutsump(i+k)=Iutsump(i+k-1)+Ibinp(k); Iutsumn(i+k)=Iutsumn(i+k-1)+Ibinn(k); end

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rowp=imsp(fix(i/4)+1,1); colp=imsp(fix(i/4)+1,2); rown=imsn(fix(i/4)+1,1); coln=imsn(fix(i/4)+1,2); %Summera källorna enligt common-centroid (varje kvadrant flippad %så att enskilda källor får gemensamt centrum) Iutsump(i+4)=Iutsump(i)+Itot(rowp,colp)+Itot(rowp,33-colp)+Itot(33-rowp,33-colp)+Itot(33-rowp,colp); Iutsumn(i+4)=Iutsumn(i)+Itot(rown,coln)+Itot(rown,33-coln)+Itot(33-rown,33-coln)+Itot(33-rown,coln); %Summera källorna utlagda likadant (ingen rotation av kvadranter) %Iutsump(i+4)=Iutsump(i)+Itot(rowp,colp)+Itot(rowp,17-colp)+Itot(17-rowp,17-colp)+Itot(17-rowp,colp); %Iutsumn(i+4)=Iutsumn(i)+Itot(rown,coln)+Itot(rown,17-coln)+Itot(17-rown,17-coln)+Itot(17-rown,coln); end for k=1022:1024 Iutsump(k)=Iutsump(k-1)+Ibinp(k-1021); Iutsumn(k)=Iutsumn(k-1)+Ibinn(k-1021); end for i=1:length(data) Ioutp(i)=Iutsump(data(i)+1); Ioutn(i)=Iutsumn(1024-data(i)); end %Räkna ut utspänningen voutp= (2*Ioutp)./((2/Rl)+(1/Rimp)*2*data); voutn= (2*Ioutn)./((2/Rl)+(1/Rimp)*(2046-2*data)); Idiff=Ioutp-Ioutn; vdiff=voutp-voutn+Noisetot; Vref1=max(vdiff)-min(vdiff); Vref=600e-3; %Utför analys av resultatet beroende på vilken test som körts if funk==1 A=[ones(size(data))', data']; yfnutt=vdiff'; c = A\yfnutt; inl=(vdiff'-A*c)./(Iref*Rl); for m=1:length(data)-1 dnl(m)=(vdiff(m+1)-vdiff(m)-2*Iref*60)/(Iref*60); end maxdnl(j)=max(abs(dnl)); MaxDNL=maxdnl(j) maxinl(j)=max(abs(inl)); MaxINL=maxinl(j) SFDRar=0; nobbar=0; j end matrX=[1:32]; matrY=[1:32]; if funk==2 fullfft;

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FOM nob1=FOM(63:67); SFDRvar=FOM(44:48) figure(1) SFDRvar=str2num(SFDRvar); SFDRar(j)=SFDRvar; nob1=str2num(nob1); nobbar(j)=nob1; maxinl=0; maxdnl=0; j end if funk==3 fullfft; FOM nobbar=0; SFDRar=0; maxinl=0; maxdnl=0; end end

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function m=swmatris(); m=zeros(4,8); mtmp=zeros(8,8); i=1; for j=1:4 m(i,j)=256 - 4*(j-1); end for k=1:4 m(i,j+k)=m(i,j) + 4*(k-1)-1; end for i=2:4 for j=1:8 m(i,j)=m(1,j)-64*(i-1); end end m2=flipud(m) - 16; mtmp=[m;m2]; mtmp4=fliplr(flipud(mtmp)); mtmp1=fliplr(flipud(mtmp4)) - 2; mtmp2=fliplr(mtmp1) - 30; mtmp3=fliplr(flipud(mtmp2)) - 2; m=[mtmp1 mtmp2 ; mtmp3 mtmp4];

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clear; nSample=4096; Fsamp=80e6; Fsig=11e6; overtoner=9; noit=100; Vref=600e-3; funk=2;%1=Ramp 2=Sinus 3=OFDM save_yes=1;%1=Skapa och spara stromkallor [SFDR,ENOB,maxinl,maxdnl,Itot]=DAC(nSample,Fsamp,Fsig,overtoner,noit,funk,save_yes); matrX=[1:32]; matrY=[1:32]; %figure(1) %surf(matrX,matrY,Itot); matrX=[1:noit]; matrY=[1:noit]; if funk==1 figure(2) hist(maxinl,50); xlabel('INL [LSB]'); ylabel('Number of DACs') figure(3) hist(maxdnl,50); xlabel('DNL [LSB]'); ylabel('Number of DACs') end if funk==2 figure(2) hist(SFDR,50); xlabel('SFDR [dB]'); ylabel('Number of DACs') figure(3) hist(ENOB,50); xlabel('ENOB [Number of bits]') ylabel('Number of DACs') end

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Appendix C

This is the SKILL code used to generate the binary-to-thermometer decoder schematic. procedure(bin2term(nbr) ;_Oct 9 03 chrli 87 cvSch = geGetWindowCellView(window(44)) ;schematic window number INV = geGetWindowCellView(window(27)) ;inverter window number NAND = geGetWindowCellView(window(28)) ;NAND window number NOR = geGetWindowCellView(window(29)) ;NOR window number NA = 0.375 ;These values are the location of the NB = 0.125 ;symbols’ pins NYx = 1.25 NYy = 0.25 IYx = 0.75 IYy = 0.1875 IA = 0.1875 nbr = nbr – 1 ;nbr from above is the number of binary inputs x = 0 old_x = 0 wireID = 0 for( i 1 nbr nbrElements = expt(2 i) - 1 if( (mod(i 2) > 0) ;Checks if it is an odd then ;or even stage for( k 1 nbrElements dbCreateInst(cvSch NOR nil list(x (1-k)) "R0" 1) ) dbCreateInst(cvSch INV nil list(x -nbrElements) "R0" 1) for( k 1 nbrElements dbCreateInst(cvSch NAND nil list(x (-nbrElements - k)) "R0" 1) ) else for( k 1 nbrElements dbCreateInst(cvSch NAND nil list(x (1-k)) "R0" 1) ) dbCreateInst(cvSch INV nil list(x -nbrElements) "R0" 1) dbCreateInst(cvSch INV nil list(old_x -nbrElements) "R0" 1) for( k 1 nbrElements dbCreateInst(cvSch NOR nil list(x (-nbrElements - k)) "R0" 1) ) ) ; ** if mod ** if( (i > 1 ) ;Check where to connect wires then ;And them connecting them for oldNbr = expt(2 i) – 1 ;the entire stage for( k 0 (oldNbr - 1 ) x1 = old_x + NYx x2 = x y1 = -k + NYy y2 = -k + NA

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if( (k == (expt(2 (i - 1)) - 1)) then x1 = x1 - (NYx - IYx) y1 = y1 - (NYy - IYy) ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** nbrE = expt(2 (i + 1)) - 1 for( k 0 (nbrE - 1) x1 = x x2 = x - 0.25 y1 = -k + NB y2 = y1 if( (k == oldNbr) then y1 = -k + IA y2 = y1 ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** x1 = x - 0.25 x2 = x1 y1 = NB y2 = (-nbrE + 1) + NB schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) for( k 0 (nbrElements - 1) x1 = old_x + NYx x2 = x y1 = -k + NYy y2 = -(nbrElements + 1) + NA - k if( (k == ((nbrElements - 1) / 2)) then x1 = old_x + IYx y1 = -k + IYy ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** x1 = x x2 = -2 y1 = -((nbrE - 1) / 2) + IA y2 = y1 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) sprintf(data_in "data_in<%d>" i) xL = x2 yL = y1 + 0.0625

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schCreateWireLabel(cvSch id (xL:yL) data_in "lowerLeft" "R0" "fixed" 0.1 nil) ) ; ** if i ** if( (i == nbr ) then nbrE = expt(2 (i + 1)) - 1 x2 = x + NYx + 1 for( k 0 (nbrE - 1) x1 = x + NYx y1 = -k + NYy y2 = y1 if( (k == ((nbrE - 1) / 2)) then x1 = x + IYx y1 = -k + IYy y2 = y1 ) ; ** if k ** id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) sprintf(data_out "data_out<%d>" k) xL = x2 - 0.75 yL = y1 + 0.0625 schCreateWireLabel(cvSch id (xL:yL) data_out "lowerLeft" "R0" "fixed" 0.1 nil) ) ; ** for k ** ) ; ** if i ** if( (i == 1) then x1 = 0 x2 = -0.25 for( k 0 2 y1 = -k + NB y2 = y1 if( (k == 1) then y1 = -k + IA y2 = y1 ) ; ** if k ** schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** for k ** x1 = x2 y1 = NB y2 = NB - 2 schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) x1 = 0 x2 = -2 y1 = NA y2 = y1

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id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) xL = x2 yL = y1 + 0.125 schCreateWireLabel(cvSch id (xL:yL) "data_in<0>" "lowerLeft" "R0" "fixed" 0.1 nil) y1 = IA - 1 y2 = y1 yL = y1 + 0.125 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) id = car(id) schCreateWireLabel(cvSch id (xL:yL) "data_in<1>" "lowerLeft" "R0" "fixed" 0.1 nil) x1 = -0.5 x2 = 0 y1 = NA y2 = NA - 2 schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0) ) ; ** if i ** old_x = x x = expt(i 3) + 4 ) ; ** for i ** msb = expt(2 (nbr + 1)) - 2 x = old_x x1 = x + 5 x2 = x1 + 2 y1 = -(msb / 2) + IA y2 = y1 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0625) id = car(id) sprintf(data_out "data_out<%d:0>" msb) xL = x1 yL = y1 + 0.125 ;The next rows puts bus-labels ;on the right place schCreateWireLabel(cvSch id (xL:yL) data_out "lowerLeft" "R0" "fixed" 0.15 nil) x1 = -4 x2 = x1 - 2 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625 0.0625 0.0625) id = car(id) msb = nbr sprintf(data_in "data_in<%d:0>" msb) xL = x2 yL = y1 + 0.125 schCreateWireLabel(cvSch id (xL:yL) data_in "lowerLeft" "R0" "fixed" 0.15 nil) ) ; ** procedure bin2term **

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