Modern Floorplanning Based on Fast Simulated Annealing

1

Modern Floorplanning Based on Fast Simulated Annealing

Tung-Chieh Chen* and Yao-Wen Chang*#

Graduate Institute of Electronics Engineering*Department of Electrical Engineering#

National Taiwan University, Taipei, TaiwanApril 5, 2005

http://www.ntu.edu.tw/chinese/PageB.php

National Taiwan University 2

Outline․ Introduction․ Fast simulated annealing scheme․ Fixed-outline floorplanning․ Bus-driven floorplanning․ Conclusion






Introduction․ Popular modern floorplanning constraints

Fixed-die (fixed-outline) constraint Block positions and interconnect constraints

․ Two types of modern floorplanning problems Fixed-outline floorplanning (FOF) Bus-driven floorplanning (BDF)

Need to consider the interconnect and block positions simultaneously.

․ Our floorplanner is based on the B*-tree floorplan representation and a fast three-stage simulated annealing scheme,

called Fast-SA.



Previous Work․ Fixed-outline floorplanning (FOF)

Adya et al. (ICCD 2001) -- Parquet Present new moves to guide local search.

Lin et al. (ASPDAC 2004) -- GFA Use evolutionary search.

However, both success rates are not high enough when whitespace is small.

․ Bus-driven floorplanning (BDF) Rafiq et al. (ISPD 2002, ISCAS 2002)

The bus is composed of wires connecting only two blocks.

Not general for real bus designs. Xiang et al. (ICCAD 2004)

General BDF allows a bus to connect multiple blocks. Use the sequences pair (SP) representation.



Our Contribution․ Propose a fast three-stage simulated

annealing scheme (Fast-SA).․ For the fixed-outline floorplanning (FOF)

Propose a new objective function and an adaptive Fast-SA.

Obtain much higher success rates. ․ For the bus-driven floorplanning (BDF)

Explore the feasibility conditions of the B*-tree with the bus constraints.

Reduce 20% (50%) dead space on average for the floorplanning with hard (soft) blocks, compared with the most recent work by Xiang et al.



B*-Tree Floorplan Representation․ Chang et al., “B*-tree: A new representation for

non-slicing floorplans,” DAC-2k. Given a B*-tree, the legal floorplan can be obtained in

amortized linear time. Left child: the lowest, adjacent block on the right (xj = xi + wi). Right child: the first block above, with the same x-coordinate

(xj = xi). n0

n7

n8

n9

n1

n2

n3

n4

n5

n6

A compacted floorplan The corresponding B*-tree

b0

b7

b8

b9b1 b2

b3

b6b5

b4

(x0, y0)

x1 = x0

w0 x7 = x0 + w0



Outline․ Introduction․ Fast simulated annealing

scheme․ Fixed-outline floorplanning․ Bus-driven floorplanning․ Conclusion



Simulated Annealing (SA) Using B*-trees

․ Non-zero probability for up-hill climbing: p = min{1, e-ΔC/T}

․ Perturbations (neighboring solutions)

Op1: Rotate a block. Op2: Move a node/block to

another place. Op3: Swap two nodes/blocks. Op4: Resize a soft block.

․ The cost function is basedon problem requirements.(fixed-outline constraint, bus constraint, etc.)

Initialize B*-tree and Temperature

Start

Perturb B*-tree

Keep new B*-tree

Better solution?

End

Update Temperature

Cooling/Good enough?

Should we accept?

Y

N

Y

N

Recover last B*-tree

Y

N



Simulated Annealing Schedule․ Classical annealing schedule

Classical temperature updating function, λ is set to a fixed value (0.85 as recommended by most previous work)

Tnew = λTold, 0 < λ< 1

․ TimberWolf annealing schedule (Sechen and Sangiovanni-Vincentelli, DAC-86)

Increase λ gradually from its lowest value (0.8) to its highest value (approximately 0.95) and then gradually decreases λ back to its lowest value.



Fast Simulated Annealing (1/2)․ Reduce the number of “up-hill” moves in the

beginning․ Consists of three stages

The high-temperature random search stage

The pseudo-greedy local search stage

The hill-climbing search stage

․ Comparisons for the temperature vs. search time:

Time

Temperatur

e

Classical SA TimberWolf SA Fast-SA

Time

I II III

Time(a) (b) (c)

SCost

State (Solution space)

local optima global optimum

Probability for up-hill climbing: p = min{1, e-ΔC/T}



Fast Simulated Annealing (2/2)․ Temperature update

․ If is large, the temperature decreases slowly.

․ If is small, the temperature decreases quickly.

knn

T

kn

n

ncT

Pavg

T

cost1

cost1n 2

1ln

The temperature for nth iterationAverage uphill costInitial acceptance rateAverage cost change since the SA startedUser-specified constants

cost

avgP

k,c

cost

cost

nT



Convergence and Stability for Fast-SA․ Classical SA

TimberWolf SAFast-SA, k=1 (no greedy local search)Fast-SA, k=7

․ Ran the circuit n100 for 10 times.

․ Fast-SA has better convergence speed than TimberWolf SA and classical SA.

Classical SA

1718192021222324252627

0 40 80 120 160 200Runtime (sec)

Area TimberWolf SA

1718192021222324252627

0 40 80 120 160 200Runtime (sec)

Area

Fast-SA, k = 1

171819

2021222324

252627

0 40 80 120 160 200Runtime (sec)

Area Fast-SA, k = 7

1718192021222324252627

0 40 80 120 160 200Runtime (sec)

Area

Classical SA TimberWolf SA

Fast SA(no greedy local search)

Fast SA






Fixed-Outline Constraints․ Two user-specified parameters:

Γ: maximum white-space fraction, and R*: desired aspect ratio (height/width)

․ The outline (height H* and width W*) is defined by:

․ Use the same formulation as Adya et al. (ICCD-2001).

*/)1(**)1(* RAWARH

Γ=0.15H*

W*

R*=2H*

W*

R*=1 Γ=0.50



Cost Function for Fixed-Outline Floorplanning

․ Cost for a floorplan F

A Chip area Area weight

W Wirelength Wirelength weight

R* Desired aspect ratioR Current floorplan aspect ratio

2)*)(1()( RRWAF

Chip area Wirelength Aspect ratio penalty



Adaptive Simulated Annealing․ Best aspect ratio of the floorplan in the fixed

outline is not the same as that of the outline. ․ Shall decrease the weight of aspect ratio penalty

to concentrate on the floorplan wirelenth/area optimization.

An adaptive method to control the weights in the cost function is used according to n most recent floorplans found.

The more feasible floorplans, the less aspect ratio penalty.

(a) (b)Decrease aspect ratio penalty



Exp: Fixed-Outline Floorplanning (1/2)․ Success rate vs. aspect ratio on circuit n100

0

20

40

60

80

100

1 1.5 2 2.5 3 3.5 4Aspect Ratio

Succ

ess r

ate

(%)

Parquet-2OursGFA

0

20

40

60

80

100

1 1.5 2 2.5 3 3.5 4Aspect Ratio

Succ

ess

rate

(%)

Parquet-2OursGFA

n100, Γ=10% Parquet-2: SP (TVLSI-2003)

GFA: NPE (ASPDAC-

2004)

Ours: B*-tree

Avg. success rate 16.6% 30.3% 99.7%Avg. dead space 7.32% 6.26% 5.79%Avg. dead space

ratio1.26 1.08 1.00

Avg. runtime (sec) 40.2 44.5 27.6Avg. runtime ratio 1.46 1.61 1.00

Γ=15%

Γ=10%

․On a Pentium 4 1.6GHz PC



Exp: Fixed-Outline Floorplanning (2/2)․ Wirelength optimization under the fixed-outline

constraint.․ Obtain 20% less wirelength on average, reduce 55%

runtime on average, compared to Parquet.Circuit Aspect

Ratio R*Parquet-2.1: SP Ours: B*-treeWire (mm)

Time (sec)

Wire (mm)

Time (sec)

ami33

1 64.6 23 46.3 162 65.9 24 48.9 113 80.9 23 67.7 154 72.7 24 61.4 14

Average 71.0 24 56.1 14

ami49

1 753 25 752 172 792 25 739 183 964 25 858 184 989 25 787 20

Average 875 25 784 18Comparison 1.20 1.55 1.00 1.00․On a Pentium 4 1.6GHz PC



Fixed-Outline Floorplanning Results

Circuit: n100

Circuit: ami49



Outline․ Introduction․ Fast simulated annealing scheme․ Fixed-outline floorplanning․ Bus-driven floorplanning (BDF)․ Conclusion



BDF Problem Formulation․ Given n rectangular macro blocks B = { bi | i = 1, …, n }

and m buses U = { ui | i = 1, …, m }, each bus ui has a width ti and goes through a set of blocks Bi.

Decide the positions of macro blocks and buses, and bus ui goes through all of its blocks.

Minimize the chip/bus area. No overlap between any two blocks or between any two

horizontal (vertical) buses.

•A feasible horizontal bus u = < H, t, { A, B, C } >.

• ymax = yc + hc

• ymin = yb • ymax - ymin ≥ t



B*-trees Properties for Bus Constraints (1/4)

․ Left child The lowest, adjacent block on the right (xj = xi + wi)

Property 1: In a B*-tree, the nodes in a left-skewed sub-tree may satisfy a horizontal bus constraint.

b0

b7

b8

b9b1 b2

b3

b6b5

b4

n0

n7

n8

n9

n1

n2

n3

n4

n5

n6




Property 2: Inserting dummy blocks of appropriate heights, we can guarantee a horizontal bus with blocks whose corresponding B*-tree nodes are in a left-skewed sub-tree

b1

b3

b4b2

x

b1

b3

b4b2

x

y

D2

D4

dummy blocks

(a) (b)




․ The height of the dummy block Di:

․ An example of inserting dummy blocks to satisfy a horizontal bus.

b0 b1

b3

b2b4

n2

n0

n4

n1n3

b5

n5

(a) (b)

b6

D5 D6

n6

D5

D6

y

x




․ Right child The first block above, with the same x-coordinate (xj =

xi).Property 3: In a B*-tree, the nodes in a right-

skewed sub-tree can guarantee the feasibility of a vertical bus.

b0 b1

b3

b2

b4

n2

n0

n4

n1 n3

b5

n5

(a) (b)

x

y



Infeasible Twisted-Bus Structure․ Consider two buses simultaneously, we cannot

always fix the horizontal bus constraint by inserting dummy blocks.

․ Should discard such a tree configuration.

u1 = {b0, b3}u2 = {b2, b6}

b0 b1

b3

b5 b2n2

n0

n4

n1

n3

b6n5

(a) (b)

b4

n6

x

y



b0 b1

b3 b4

b2

b0 b1

b3b4

b2

D2

(a) (b)

n2

n0

n4

n1

n3

(c) (d)

D2

n0

n4

n1

n3

n2

y

y

Bus-Overlapping․ Use dummy blocks to avoid bus-overlapping

while considering multiple buses.

u1 = {b0, b4}u2 = {b2, b3}

u1 = {b0, b4}u2 = {b2, b3}



Our BDF Algorithm (1/2)․ Use simulated annealing to search for a desired

solution. Cost of a floorplan F, buses U:

A chip area B bus area M number of unassigned

buses

MBAUF ),(



Our BDF Algorithm (2/2)Initialize floorplan

Perturb and pack

“Twisted-bus structure” exists?

Report the best floorplan

Compute floorplan cost (quality)

Simulated annealing iterations

Adjust heights of dummy blocks

Pack and decide bus location

yesno

Cooling down



Soft Macro Block Adjustment․ Key: Line up with adjacent blocks

Each soft block has four candidates for the block dimensions.

․ Advantage: fast and reasonably effective․ Similar idea by Chi et al., Chung Yuan Journal,

2003.

b2b1b2

b0

b4

b3

b5

L3 R3

T3

B3 b0 b1

b4

b3

b5

(a) (b)

xx

y y

R3



Exp: Bus-Driven Floorplanning

Block type Hard Macro Blocks Soft Macro Blocks

Circuits Block#

Bus#

SP: Xiang et al. (ICCAD 2003) B*-tree: Ours

SP: Xiang et al.

(ICCAD 2003)B*-tree: Ours

Time(sec)

Deadspace

Time(sec)

Deadspace

Time(sec)

Deadspace

Time(sec)

Deadspace

apte 9 5 11 4.11% 8 1.59% 12 0.72% 3 0.02%

xerox 10 6 12 3.88% 5 3.85% 13 0.95% 6 0.10%

hp 11 14 28 5.02% 20 4.47% 28 0.62% 11 0.03%

ami33-1 33 8 61 6.02% 19 5.69% 62 0.94% 35 0.33%

ami33-2 33 18 81 6.10% 22 3.87% 86 1.27% 35 0.73%

ami49-1 49 9 98 5.42% 28 5.34% 101 0.85% 65 0.51%

ami49-2 49 12 278 6.09% 43 5.45% 281 0.84% 90 0.67%

ami49-3 49 15 265 7.40% 66 4.74% 268 1.09% 109 0.92%

Average 104 5.51% 26 4.38% 106 0.91% 47 0.41%*SP: Hua Xiang, Xiaoping Tang, and Martin D.F. Wong, “Bus-driven floorplanning”, ICCAD 2003. The platform of SP is Intel Xeon 2.4GHz.

․ MCNC benchmark on Pentium 4 2.8GHz. Obtain 20% (55%) less dead space on average for hard (soft) macro blocks.



BDF Result

․ MCNC ami49-3 with soft block adjustment.

․ It has 49 macro blocks and 15 buses.






Conclusion․ Have proposed algorithms for the modern

floorplanning problems with fixed-outline constraints and bus-constraints based on the new Fast-SA scheme.

․ Have shown Fast-SA leads to faster and stabler convergence to desired floorplan solutions.

․ Have shown the efficiency and effectiveness of our floorplanning algorithms for fixed-outline/bus-driven floorplanning.



Thank you for your attention!

B*-tree 2005 will be available soon athttp://eda.ee.ntu.edu.tw/research.htmB*-tree 1.0 (year 2000) + new perturbations + Fast-SA

http://eda.ee.ntu.edu.tw/research.htm


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Modern Floorplanning Based on Fast Simulated Annealing

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