A physics-based model for Charge-
Trapping memory simulation
Andrea Padovani and Luca Larcher
DISMIDISMI
Università di Modena e Reggio Emilia
Purpose
• Charge-trapping devices like TANOS are a
promising candidates to replace Floating Gate
memoriesmemories
• Understanding the physical mechanisms
governing device operation is fundamental for
performance and reliability optimization
• This requires accurate simulation models
• We present results obtained with a physical
model accounting for both charge trapping in model accounting for both charge trapping in
alumina and temperature effects
2
Outline
• Introduction
• Physical Model
• Model Results• Model Results
– Program and Erase operations
– Charge Separation Experiments
– Charge Trapping into Alumina
– Effects of Temperature
• Toward a SPICE-like model of the TANOS cell• Toward a SPICE-like model of the TANOS cell
• Conclusions
3
Introduction
Poly-Si
SONOS
TaN
TANOS
gate
• Better retention (thicker tunnel SiO )
SiO2
Si3N4SiO2Si
Al2O3
Si3N4SiO2
Si
blocking oxide
trapping layer
tunnel oxide
• Better retention (thicker tunnel SiO2)
• Improved program/erase speed (high-k)
• Improved erase VT saturation level (metal gate)
4C. H. Lee et al., IEDM Tech. Dig., 2003, p. 613
Physical Model
• Charge trapping and
transport across the
stack is described by
a set of differential
����,� ����+�,� ����,� = ��� ����+�,� = ��
���_��,� �����,� a set of differential
equations solved by
discretizing space and
time (indexes i and j)
−+= +−
L
nn
q
TkFnqJ
jiFjiFBjijiFjiCB
,1,
1,,,µ
reg. 1 reg. i reg. N … …
SiO2 Al2O3
���_��,� �����,�
���_��,�
L
5
Lq
( )jiTRAPjiEMjiCBjiCB
jj
jiFjiFJJJJ
tt
nnqL,,,1,
1
1,, −+−=−
−+
−
−
( )jiEMjiTRAP
jj
jiTjiTJJ
tt
nnqL,,
1
1,, −=−
−
−
−
JTUN
JTRAP
Physical Mechanisms: Program
JTRAP = q⋅⋅⋅⋅ nF⋅⋅⋅⋅L⋅⋅⋅⋅ RCJEM = q⋅⋅⋅⋅ nT⋅⋅⋅⋅L ⋅⋅⋅⋅RE
TaN
gate
Si N SiO Al O
JTRAP
JEM
• JTUN includes tunneling and TAT contributions
• JTRAP is calculated using Shockley-Read-Hall theory
• JEM includes thermal and trap-to-band tunneling emission
Si3N4 SiO2 Al2O3
6
Physical Mechanisms: Erase
TaN
gate
JGATE
gate
Al2O3
Si3N4
JTUN
JTRAP
JEMJEM
• JTUN is the hole current injected from the substrate
• JGATE is the electron current injected from the gate
7
Si3N4
SiO2
Solution Algorithm
• Iterative methods commonly
used to solve the equation system
• We developed a novel algorithm
allowing deriving a closed form
Initial charge
distribution
Calculation of potential allowing deriving a closed form
solution of the above system
( ) jijijiCBjijiF Jn ,,,,, αγβ −=
Calculation of potential
profile and electric fields
Calculation of the tunneling
current across the SiO2, JTUN
Calculation of free and
trapped charge densities
Calculation of the ∆V shift
=+
Samples
• Model used to reproduce program, erase and retention
of TANOS devices manufactured by different
technologies (A, B, C)
Sample tOX [nm] tNI [nm] tAL [nm]
A1 3 5 11.5
A2 4 5 11.5
A3 4 8.7 11.5
A4 4.5 7 12
B1 4 6 12
B2 5 6 12
TANOS
highest tN/tAL ratio
9
B2 5 6 12
C1 4.5 6 15
C2 4.5 4 15
C3 4.5 6 10
C4 1 - 5
C5 1 - 10
C6 1 - 15
TAOS
lowest tN/tAL ratio
Program
• TAT through SiO2 is fundamental to achieve high
accuracy at low VG and high times (low fields)
8
2
4
6
8
∆∆ ∆∆V
T[V
]
Vg=10V
Vg=12V
Vg=14V
0.1
1
10
1E-06 1E-03 1E+00
∆∆ ∆∆V
T[V
]
time [s]
sample C1
tOX/tN/tAL = 4.5/6/15
10A. Padovani et al., IEEE EDL 30, p.882, Aug. 2009
0
2
1.E-10 1.E-07 1.E-04 1.E-01
time [s]
Vg=14V
Vg=16V
Vg=18V
simulations
• Simulations accurately reproduce erase transients
• Holes significantly contribute to TANOS erase at high |VG|
Erase
4
sample B1
tOX/tN/tAL = 4/6/12
-1
0
1
2
3
4
∆∆ ∆∆V
T[V
]
Vg=-10V
Vg=-12V
Vg=-14V
11
-3
-2
-1
1E-06 1E-04 1E-02 1E+00
time [s]
Vg=-14V
Vg=-16V
Vg=-18V
Charge Separation
• Simulations accurately reproduce both electron and
hole currents measured during charge separation
experiments
tOX/tN/tAL = 4/6/12
12L. Vandelli et al., to be presented at IRPS 2010, 2-5 May, Anaheim (CA).
sample B1
Trapping into Alumina
• Early saturation observed in simulations when trapping in
alumina is neglected on the sample having a low tN/tAL ratio
• Large amount of electron charge trapped into Al2O3 defects
2
3
4
5
6
7
∆∆ ∆∆V
T[V
]
Vg=10V
Vg=12V
Vg=14V
Vg=16V
Vg=18V
sample C2 tOX/tN/tAL = 4.5/4/15
1E+18
1E+19
1E+20
Ele
ctro
n D
en
sity
[cm
-3]
increasing
time
13A. Padovani et al., to be presented at VLSI-TSA 2010, 26-28 April, Taiwan
0
1
2
1E-07 1E-05 1E-03 1E-01 1E+01
time [s] tN/tAL = 0.27
1E+17
0 2 4 6 8 10 12 14 16 18
Ele
ctro
n D
en
sity
[cm
depth from SiO2/SiN interface [nm]
Si3N4 Al2O3
Trapping into Alumina -2
• Electron charge trapped in the alumina layer during program
can account for up to 25% of the total ∆∆∆∆VT shift
• Electron trapping in Al2O3 is negligible for a high tN/tAL ratio• Electron trapping in Al2O3 is negligible for a high tN/tAL ratio
10%
15%
20%
25%
30%
ma
xim
um
∆∆ ∆∆V
T,A
L/∆∆ ∆∆
VT
C1
C2
C3
A3
tN/tAL = 0.27
tN/tAL = 0.4
tN/tAL = 0.6
14
0%
5%
10%
6 8 10 12 14 16
ma
xim
um
VG/EOT [MV/cm]
tN/tAL = 0.6
tN/tAL = 0.76
Trapping into Alumina -3
• Hole trapping in alumina during erase is negligible
• 30% of the electron trapped into Al2O3 during program are
still there at the end of the subsequent erase operation
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
∆∆ ∆∆V
T[V
] Vg=-11VVg=-13.5V
Vg=-16V
-2
-1
0
1
2
3
4
5
∆∆ ∆∆V
T[V
] Vg=-12VVg=-14V
Vg=-16V
Vg=-18V
15
-4.5
-4.0
-3.5
-3.0
1.E-05 1.E-03 1.E-01 1.E+01 1.E+03
time [s]
-5
-4
-3
-2
1E-06 1E-04 1E-02 1E+00
time [s]
tOX/tN/tAL = 4.5/4/15 solid: w/ Al2O3dashed: w/o Al2O3
sample C2
• Accelerated retention tests exhibit a double slope: clear
signature of charge trapping in alumina
Trapping into Alumina -4
0.2
sample C1
tOX/tN/tAL = 4.5/6/15
-0.6
-0.4
-0.2
0.0
0.2
∆∆ ∆∆V
FB
[V]
Vg=0V
Vg=3V
Vg=6V
region I region II
16
-1.0
-0.8
1E-01 1E+01 1E+03 1E+05
time [s]
Vg=6V
solid lines: w/ Al2O3 trapping
dashed lines: w/o Al2O3 trapping
Temperature Effects
• Program and erase operations exhibit a strong
temperature dependence, which is not explained by the
temperature dependence of charge trapping and
emission mechanismsemission mechanisms
2
3
4
5
6
∆∆ ∆∆V
T[V
]
225K
300K
high T
low T
∆∆ ∆∆V
T[V
]
time[s]
high T
low T
high T
low T
10-7 10-5 10-3 10-1
10
1
0.1
-3.0
-1.5
0.0
∆∆ ∆∆V
T[V
]
225K
300K
high T
low T VG = -18V
17
0
1
2
time[s]
300K
375K
425K
simulations
VG = 14V
10-8 10-6 10-4 10-2 100-6.0
-4.5
time[s]
300K
375K
425K
simulations
10-6 10-4 10-2 100
sample A4
tOX/tN/tAL = 4.5/7/12
A. Padovani et al., to be published on APL
Temperature Effects -2
• Explanation: κκκκAL increases with temperature (∼∼∼∼25% over 125K)
• Voltage redistribution across the stack (VG≈≈≈≈VOX+VN+VAL) leading to an increase of FOXleading to an increase of FOX
-6
-4
-2
0
2
4
En
erg
y [
eV
]
T = 300K
T = 425K
FOX increase
FAL reduction
Ca
pa
cita
nce
[F/
cm2]
simulations
6⋅10-7
5⋅10-7
4⋅10-7
3⋅10-7
κκ κκ AL
Temperature [K]
A4C1C6
CAL = εεεεAL/tAL
18
-10
-8
-6
-2 0 2 4 6 8 10 12 14 16 18 20 22 24
En
erg
y [
eV
]VG = 9V
Distance from Si/SiO2 interface [nm]
A. Arreghini et al., ULIS Tech. Dig., p.101, 2010.
A. Padovani et al., to be published on APL
-3 -2 -1 0 1 2 3 4 5
Ca
pa
cita
nce
[F/
cm
Gate Voltage [V]
simulations
425K
300K
2⋅10-7
1⋅10-7
• Charge centroid findings can be used to develop
simple TANOS SPICE-like models
Toward a Compact TANOS model
G
CAL=εεεεAL/tAL
CN=εεεεOX/XCN
TaN
Al2O3
Si3N4XCN
VN
19
IP/E
S D
B
Si
SiO2
Conclusions
• We developed a physical model to simulate P/E
operations and reliability of TANOS devices
• The model exploits a new algorithm for the closed • The model exploits a new algorithm for the closed
form solution of the equation system describing
charge trapping and transport across the TANOS
stack
• The model has been used to investigate the effects
of temperature and charge trapping into alumina on
TANOS operations and reliabilityTANOS operations and reliability
• This allows extracting important guidelines for
stack optimizations
• The model allows deriving the basic
approximations to develop SPICE-like compact
models20