TECHNIQUES FOR NONLINEAR CIRCUIT SIMULATION MOS analogue circuit simulation with SPICE A. Vladimirescu J.-J. Charlot Indexing terms: Analogue circuit simulation, CMOS, MOSFET, SPICE Abstract: The paper describes implementation details and imperfections of the SPICE MOSFET models which, together with MOS circuit design techniques, can contribute to inaccurate simula- tion results and convergence failure. The impact of model parameters on MOS level 2 and 3 drain- source conductance and gate-drain trans- conductance is analysed, and discontinuities are revealed. A typical CMOS differential amplifier is used to relate design techniques to possible con- vergence failures. Solutions for convergence are described, based on model parameter/physical effect selection, options specification, initialisation techniques and algorithmic choices. Design tech- niques and simultation difficulties are related to SPICE models to convey the right approach for modelling and simulating analogue MOS designs. 1 Introduction Designers of CMOS or BiCMOS analogue circuits face more difficulties than their bipolar counterparts when they simulate their circuits with SPICE2, SPICE3 and commercial derivatives of the programs. Accuracy prob- lems in modelling MOS analogue circuits have already been documented in the past [l, 21. The widespread use of SPICE MOSFET models level 2 and 3 [3,4] requires a better knowledge of the imperfections, and the best ways to avoid them. The continued wide use of these models is due to their universal availability and compat- ibility in all SPICE versions. Model imperfections can lead to numerical oscillations between two regions during the nonlinear solution process. In such situations, altering the model can lead to an initial solution. The significance of including or delet- ing physical effects in a model, through the parameters which are specified, is described in Section 2. Character- istics of the gate-drain transconductance g,,, and the drain-source conductance gda are traced for different sets of model parameters and for different models. Some circuit configurations used in CMOS designs, such as cascode current sources and gain stages, intro- duce high impedance nodes; such nodes contribute very low conductances in the circuit matrix used in the SPICE solution [SI, leading to numerical instability. For 0 IEE 1994 Paper 1247G (ElO), first rcceived 10th December 1993 and in revised form 5th April 1994 A. Vladimirescu is with Cadence Dcsign Systems 555 River Oaks Pkwy, San low, CA 95134, USA J.-J. Charlot is with b l c Nationale Superieure de Telecommunica- tions, 46, rue Barrsult, 75634 Paris, France IEE Proc.-Circuits Devices Syst., Vol. 141, No. 4, August 1994 maximum compliance with low voltage supplies, CMOS stages are often biased close to the limit between linear, saturation and cut-off regions. Such biasing scheme has the added advantage of maximising the gain. A differen- tial amplifier is used in Section 3 to exemplify the impact that design requirements may have on simulation. The amplifier bias point is related to the conductance charac- teristics derived in Section 2. Additional details of MOSFET analysis impiementa- tion in SPICE such as initialisation are given in Section 4. A user of circuit simulation can improve the rate of success of SPICE runs by following a number of steps [SI also described in this Section. Convergence difficulties can be exemplified by a CMOS differential amplifier, and the techniques to overcome such problems are presented in Section 4. Commercial SPICE programs may have corrected or improved some of the issues presented in this paper. A number of new models (e.g. the BSIMl [SI, BSIMZ [7] and BSIM3 [SI models), have been added to present-day SPICE simulators to better match small size device char- acteristics; some reduce discontinuities at the transition between different regions of operation by better matching measured data, but do not eliminate them completely. New models are being proposed [9, lo] using a unique formulation to avoid discontinuities; this approach holds the most promise. 2 SPICE MOSFET model specifics MOSFET circuits have been observed to have more con- vergence problems than bipolar circuits owing to a number of differences between the two device types. First, the physical structure of the two devices is differ- ent. The gate terminal of a MOSFET is insulated (i.e. it is an open circuit in DC). The self-conductance of the gate is therefore zero in DC, which may lead to an ill-conditioned circuit conductance matrix, and, subse- quently, to a SPICE failure to find a solution, because SPICE builds and solves the node voltage equations of a circuit. By contrast to the MOSFET behaviour, there is always current flowing in or out of the base terminal of a bipolar transistor (EUT), independent of the region of operation and analysis mode. Secondly, the implementation of MOSFET analysis in SPICE differs from BJT analysis, a factor which also The authors would like to acknowledge Dr. D. Senderowicz for many useful suggestions and a critical reading of the paper as well as contrib- uting remarks from Dr. M.-C. Jeng and J. Berwick. 265
Abstract: The paper describes implementation details and imperfections of the SPICE MOSFET models which, together with MOS circuit design techniques, can contribute to inaccurate simula- tion results and convergence failure. The impact of model parameters on MOS level 2 and 3 drain- source conductance and gate-drain trans- conductance is analysed, and discontinuities are revealed. A typical CMOS differential amplifier is used to relate design techniques to possible con- vergence failures. Solutions for convergence are described, based on model parameter/physical effect selection, options specification, initialisation techniques and algorithmic choices. Design tech- niques and simultation difficulties are related to SPICE models to convey the right approach for modelling and simulating analogue MOS designs.
1 Introduction
Designers of CMOS or BiCMOS analogue circuits face more difficulties than their bipolar counterparts when they simulate their circuits with SPICE2, SPICE3 and commercial derivatives of the programs. Accuracy prob- lems in modelling MOS analogue circuits have already been documented in the past [l, 21. The widespread use of SPICE MOSFET models level 2 and 3 [3,4] requires a better knowledge of the imperfections, and the best ways to avoid them. The continued wide use of these models is due to their universal availability and compat- ibility in all SPICE versions.
Model imperfections can lead to numerical oscillations between two regions during the nonlinear solution process. In such situations, altering the model can lead to an initial solution. The significance of including or delet- ing physical effects in a model, through the parameters which are specified, is described in Section 2. Character- istics of the gate-drain transconductance g,,, and the drain-source conductance gda are traced for different sets of model parameters and for different models.
Some circuit configurations used in CMOS designs, such as cascode current sources and gain stages, intro- duce high impedance nodes; such nodes contribute very low conductances in the circuit matrix used in the SPICE solution [SI, leading to numerical instability. For
0 IEE 1994 Paper 1247G (ElO), first rcceived 10th December 1993 and in revised form 5th April 1994 A. Vladimirescu is with Cadence Dcsign Systems 555 River Oaks Pkwy, San low, CA 95134, USA J.-J. Charlot is with b l c Nationale Superieure de Telecommunica- tions, 46, rue Barrsult, 75634 Paris, France
IEE Proc.-Circuits Devices Syst., Vol. 141, No. 4, August 1994
maximum compliance with low voltage supplies, CMOS stages are often biased close to the limit between linear, saturation and cut-off regions. Such biasing scheme has the added advantage of maximising the gain. A differen- tial amplifier is used in Section 3 to exemplify the impact that design requirements may have on simulation. The amplifier bias point is related to the conductance charac- teristics derived in Section 2.
Additional details of MOSFET analysis impiementa- tion in SPICE such as initialisation are given in Section 4. A user of circuit simulation can improve the rate of success of SPICE runs by following a number of steps [SI also described in this Section. Convergence difficulties can be exemplified by a CMOS differential amplifier, and the techniques to overcome such problems are presented in Section 4.
Commercial SPICE programs may have corrected or improved some of the issues presented in this paper. A number of new models (e.g. the BSIMl [SI, BSIMZ [7] and BSIM3 [SI models), have been added to present-day SPICE simulators to better match small size device char- acteristics; some reduce discontinuities at the transition between different regions of operation by better matching measured data, but do not eliminate them completely. New models are being proposed [9, lo] using a unique formulation to avoid discontinuities; this approach holds the most promise.
2 SPICE MOSFET model specifics
MOSFET circuits have been observed to have more con- vergence problems than bipolar circuits owing to a number of differences between the two device types.
First, the physical structure of the two devices is differ- ent. The gate terminal of a MOSFET is insulated (i.e. it is an open circuit in DC). The self-conductance of the gate is therefore zero in DC, which may lead to an ill-conditioned circuit conductance matrix, and, subse- quently, to a SPICE failure to find a solution, because SPICE builds and solves the node voltage equations of a circuit. By contrast to the MOSFET behaviour, there is always current flowing in or out of the base terminal of a bipolar transistor (EUT), independent of the region of operation and analysis mode.
Secondly, the implementation of MOSFET analysis in SPICE differs from BJT analysis, a factor which also
The authors would like to acknowledge Dr. D. Senderowicz for many useful suggestions and a critical reading of the paper as well as contrib- uting remarks from Dr. M.-C. Jeng and J. Berwick.
265
affects convergence. More detail on implementation is provided in Section 4.
Thirdly, the generality of analytical models used in SPICE to describe the two devices is not the same. While the Ebers-Moll or Gummel-Poon [ 4 ] formulation for the BJT transistor applies to all regions of operation, the MOSFET models combine different equations to describe distinct regions of operation and various second-order effects. The different formulations have varying levels of continuity for the equivalent conduc- tance at the transition points. The continuity of the con- ductance, which is the first derivative of the I,, =f (VDs , V,,, VBs) function, is important for the convergence of the iterative process, and for the accuracy of small-signal analysis.
The first three levels of MOSFET models 1 to 3, intro- duce different physical effects in the behaviour descrip- tion depending on model parameters. Italic capital names are used for the model and other SPICE parameters throughout this paper. The shortcomings of MOSFET models can be understood best by looking at the under- lying equations; the drain-source current of a LEVEL = 2 model is defined by the following equations
IDS = b{ ( vGS - 'BIN - -)'DS 'DS
2
- +y,[(PHI + V,, - VBs)3'2 - (PHI - VBs)3/2]}
(1)
where the transconductance and mobility factors, B and ps, are defined by
In the above equations, W and L are the geometric width and length of the device and UO, UCRIT and U E X P are the mobility and the critical field degradation parameters. Current flows only when VGs > V,,, otherwise I , = 0. The built-in voltage including small size effects is
VBIN = VFB + PHI + DELTA - vBS) (4) 4COX w
The substrate bias adjusted and zero bias threshold volt- ages are, respectively
VTH = + 7s J ( P H I - V k ) (5)
(6) V T O = VFB + PHI - G A M M A J ( P H I )
where ys is the bulk threshold parameter G A M M A adjusted for small-size effects. All italicised capital names in the above equations represent SPICE model param- eter names, see appropriate user guides [l 1, 121.
In the evaluation of I , the geometric channel length L is adjusted for the lateral diffusion, LD, and for channel shortening in saturation
Le, = L - 2LD (7) L . LAMBDA . VDs
.f(VDsAT) if LAMBDA is not specified *.={ if LAMBDA is specified (8)
266
The latter effect produces a finite drain-source conduc- tance gds when the device is saturated. Onset of satura- tion can be explained either by the inversion layer pinching off at the drain or the carriers reaching a maximum velocity [13]. The pinch-off saturation voltage is defined by
+ PHI - VBs)]"'} rGS II (9)
AL = xd{ vDS - vDSAT + d 1 + ('DS -4vDSATy] }1 '2
4
(10)
For values V,, > VDSAT the saturation voltage is substi- tuted in eqn. 1 for V,,. Any variation in I , for V,, > V,,,, , is due to AL, eqn. 10.
The presence of specific parameters result in given physical behaviours being modelled, e.g. the presence of NFS, the fast surface state density, triggers a sub- threshold current to flow at values of gate-source voltage VGs, which are less than the threshold voltage V,,. Sub- threshold current modelling can cure problems related to device current convergence by avoiding the sudden onset of I, conduction at the threshold voltage. This discon- tinuous physical behaviour predicted by the above model is an important departure from bipolar device model operation where the current varies continuously starting from the junction reverse current.
When NFS is nonzero, a diffusion current, the sub- threshold current, is modelled by the following equation
where
C,, = 4 . NFS
d c d = - = -7s - J(PHI - VBs) a aQB V,S [ dV,,
-- ay' vBS &'HI - VBs) + DELTA *]Cox 4c0, w
The newly defined threshold voltage VON, is the gate- source voltage where the diffusion component of I,, according to eqn. 11 equals the drift component for strong inversion defined by eqn. 1.
The I,, characteristic as a function of V,, at V,, = 0.1 V is shown in Fig. 1 for a LEVEL = 2 model with NFS as parameter; in the absence of the NFS parameters or, equivalently, when its value is zero no current flows below the strong inversion threshold VT, . For increasing
I E E Proc.-Circuits Devices Syst., Vol. 141, No. 4, August I994
values of NFS, higher levels of subthreshold currents can be noticed. The transition from subthreshold conduction to strong inversion, from one analytical formulation to the next, is not smooth as seen in Fig. 1. This leads to a
10
1
U?- 100 2
10
1
100
=z
P
P n
n
n
P
2000 rn 4OOOm 6000 rn 8000 m
Vds=O 1 V
I
10 1 2
vgs. v Log I,, =/(Vas) for LEVEL = 2 with and without subthresh- Fig. 1
old conduction (NFS)
discontinuity close to threshold V,, in the gm character- istic which can be seen clearly in Fig. 2. The three charac- teristics are for NFS = 0, 10” and 5 x 10’’ cm-2 and V,, = 0.1 V. The upper curve is obtained for the strong inversion model described by eqns. 1-10 with pinch-off saturation (no V M A X ) and no subthreshold conduction (no NFS).
r
600m 700rn 800m 900m
vgs. v g, = f(Va,! for L E V E L 2 at low VGs, V,,, with and without Fig. 2
subthreshold conduction (NFS) and velocity limited saturation ( V M A X )
Conductance discontinuities are also encountered at the transition from saturation into linear region. The type of saturation mechanism, channel pinch-off or veloc- ity limited saturation is selected depending whether V M A X , the maximum drift velocity of carriers, is speci- fied. The velocity saturation based model derives V,,,, and AL from the following equations
(13)
(14)
IDSAT - V M A X x W x Qcban(L) = 0
QrhOn = C ~ S V G S - VBIN - VVDSAT
- YAPHI - b S + vDS,4T)”21
X: V M A X + 2Ps
Two g, characteristics are shown in Fig. 3 for larger values of V,, at VDs = 1 V to point out the behaviour at
IEE Proc.-Circuits Devices Sysf., Vol. 141, No. 4, August 1994
the transition from saturation to linear. The first g, curve corresponds to a model with subthreshold conduction and velocity limited saturation while the second curve
7 m A
2 m t Y l r n
Vds =1V
I
3 4 1 2
vgs, v Fig. 3 conduction (NFS) and velocity limited satdration ( V M A X )
g , = f(VGs) for LEVEL = 2 with and without subthreshold
corresponds to a model with no weak inversion conduc- tion, NFS is not specified, and channel pinch-off satura- tion, V M A X is not specified.
Similar discontinuities of the transconductance gnt can be observed in Fig. 4 and 5 for the LEVEL = 3 model; the two plots correspond to V,, = 0.1 V and 1 V, respec- tively. Discontinuities can be observed at the same transition points, subthreshold to strong inversion and saturation to linear. The same parameters as in LEVEL = 2 (i.e. NFS and V M A X , control which physi- cal effects are incorporated in the behaviour).
nfs = 5ell without nfS, kappa
Vds =O 1
600 m 700 m 800 m 900 m vgs. v
g. = f (VaS) for LEVEL = 3 at low Vas, V,, with and without Fig. 4 subthreshold conduction (NFS) and uelacity limited saturation ( V M A X )
I
vgs. v Fig. 5 conduction (NFS) and wlocity limited saturation ( V M A X )
g, = f(V,) for LEVEL = 3 with and without subthreshold
261
Another important characteristic of a MOS transistor is the gds conductance which is represented as a function of V,, at VGs = 1 V in Fig. 6 for a LEVEL = 2 model. The importance of correctly modelling these two conduc- tances of a MOSFET becomes apparent in the following Section.
The impact of the above discontinuities on simulation becomes apparent in the process of obtaining the charac- teristics shown in Fig. 2 to 5. The conductance plots are generated using a transient analysis with a piecewise linear source ramping VGs from zero to the desired value over an equal time interval in seconds, and a derivation circuit to obtain the conductance. The result with the SPICE2/SPICE3 default options are numerical oscil- lations as shown in Fig. 7. Discontinuities in circuit vari- ables often cause an oscillatory response when the trapezoidal integration method is used, the default in most SPICE programs, owing to the stability properties of this method which depend on the integration step [5 , 141. The smooth characteristic is the result of applying the Gear method, options METHOD = GEAR, MAXORD = 2, and reducing the local truncation error through the RELTOL option parameter which is reduced to from the default The Gear integration method is the default in PSpice [l5]. More detail on the impact of simulation options is provided in Section 5. Note that recent versions of SPICE3 allow a user to save the internally computed value of device parameters, such as a conductance, for displaying it in Nutmeg [12].
The above plots have been obtained for the following set of MOSFET parameters:
see Fig. 9. By comparison, the LEVEL = 2 model dis- plays a discontinuity at this point owing to the transition from AL = X,, the zero-bias depletion width at the
Vds:lV
2 3 L
vgs. v Fig. 7 Effect ofdiscontinuities on g , = f ( V J with d e f i l t options and T R A P integration
drain, to either eqn. 10 or 15. The behaviour predicted by the Unicell model for both conductances is according to requirements and data presented in several papers [2, lo]
3
A number of guidelines are used in the design of CMOS circuits in order to maximise performance. Consider the
Analogue CMOS design techniques and simulation
* * N-CHANNEL TRANSISTOR .MODEL N NMOS LEVEL=2 + U0=600 VTO=O.I TPG=1 TOX=25E-9 NSUB=5E+16 UCRIT=2E+4 UEXP=O.l + XJ=lE-10 LDdOOE-9 PB=0.8 J S = l O O U RSH=10 NFS=200E+9 VMAX=60E+3 NEFF=2.5 DELTA=3 + CJ=4OOU MJ=0.3 CJSW=2N M J S W d CGSO=O.ZN CGDO 0.2N CGBO=0.3N
*
The conductance characteristic predicted by a model based on a unique current expression for all regions such as the Unicel model [9] are plotted with those for LEVEL = 2 in Figs. 8 and 9. A smooth transition can be observed in the plot of g,, Fig. 8, from subthreshold to strong inversion, and, at the peak, from saturation to linear. By comparison the LEVEL = 2 curve shows a dis-
Unicel model predicts the correct behaviour for gh as well when the transistor goes from linear into saturation,
2 (16) (I, = 6 =
tinct drop at the transition from saturation to linear. The B O Y V G S - VTH)
1OOm 2CQm 3M)m 400m
Vds. V
gb = f(V') for LEVEL = 2 with and without subthreshold
vgs. v Fig. 8 + U O ~ ~ I , ~
g , = J(V,) for Unicell model compared to LEVEL = 2 Fig. 6 conduction (NFS) and velocity limited saturation ( V M A X ) + ~ c s 2 . ~
where I. (LAMBDA) is the channel length modulation factor measured in V-' for a LEVEL = 1 model, see eqn. 8, and go is the drain source conductance of the load transistor. The above relation is based on the simple quadratic LEVEL = 1 model
0 for V,, < V,,
(V,, - V,&1 + LAMBDA x VDs)
for 0 < V,, - V,, d VDs
[ for o i v,, < v,, - v,,
These design considerations imply operation around the discontinuities displayed in Figs. 2 and 4. Another design consideration for amplifiers with cascode active loads is to bias the input transistors at the edge of saturation for maximum output swing. This implies operation close to the discontinuity revealed in Figs 2, 3, 4, 5 and 6. These requirements lead to biasing the transistor at low V,,,
An example for the above design techiques is the CMOS differential amplifier shown in Fig. 10. The oper- ating point information and the small-signal transfer function characteristics of this CMOS differential pair are printed in Fig. 11. It can be noticed that transistors M, and M, are biased 100mV above the threshold, which means very close to the transition from subthreshold to strong inversion. The small-signal gain computed by SPICE in this bias point is 75 which is close to the gain derived from small-signal analysis [16]
(18)
vGS '
9m1 a, = ~
Bo2 + Qo4
If the bias on the gates of the differential pair transistors M, and M, is lowered to 0.8 V (i.e. effective V,, of only 40mV), the gain can be improved considerably, to 195
M,-M, . The state of this circuit is defined by connecting the appropriate bias transistors M , , - M , , to the gates of
20m > U VI U 0
. 1 0 m
O m 0 01 0 2 03 0 4 0 5
Yds. V
Fig. 9 -8- uniall,gds
mos2,gds
g, =/(V,,)/or Unicell model compared to LEVEL = 2
@P lo
according tothe results in Fig. 12. All transistors have a
parameters listed in Section 2 have been used for the NMOS device and the following parameters have been
channel length of 1.2 pm and width of 120 pm; the model
used for the PMOS device:
Fig. 10 CMOS dflmenrial mpl$m
load transistors M,, M, and M,, M,, differential pair transistor M,, and, the gate of transistor M, , respec- L tively. Transistors M,-M, have W = 120pm and
* Operation of these transistors as close to model discon- tinuity locations can cause unpleasant surprises in the simulation of larger circuits.
Most CMOS amplifier designs use cascode active loads as shown in Fig. 13 for maximising the gain. This circuit configuration presents additional challenges in simulation due to the very high impedance at the output nodes.
The CMOS differential amplifier with cascode loads [I71 shown in Fig. 13 exemplifies the convergence prob- lems mentioned above. This circuit is a differential ampli- fier in a unity feedback loop; the conversion from double to single-ended output is achieved by PMOS transistors
L = 1.2 pm and transistors Ml,-M,, have the same W and channel lengths which are multiples of 1.2pm for proper bias.
The first challenge comes with the DC solution. Based on knowledge of electric networks, one can see the difii- culty associated with solving the nodal equations of this circuits owing to a number of very high impedance nodes; nodes 3 and 4 have very high impedance defined by the cascode connection, and, in addition, transistors are biased very close to the threshold voltage on one hand, and at the limit between saturation and linear region, on the other hand. The DC operating point infor- mation for this circuit is listed in Fig. 14. This approach
V(4)pl NP INPUT RESISTANCE AT VlNP OUTPUT RESISTANCE AT V(4)
JOB CONCLUDED TOTAL JOB TIME 0.52
= 7.558D+01 =1.000D+20 = 6.886D+04
Fig. 11 DC bias point of CMOS circuit for q, = 0.98 V and V,_ = I V
to biasing is common in many analogue CMOS circuits owing to the design requirements presented above.
The following Section is dedicated to exploring approaches for overcoming convergence failures and uses as an example the CMOS circuit in Fig. 13.
4 Simulation specifics and convergence guidelines f o r MOSFET circuits
The nonlinear nature of semiconductor device current- voltage characteristics leads to a set of simultaneous non- linear circuit equations. An iterative loop based on the Newton-Raphson algorithm is used in all SPICE pro- grams to solve the circuit equations. The iterative solu- tion process continues until all node voltages and currents converge, or, equivalently, until the solutions of two consecutive iterations are the same. At each iter- ation, the nonlinear characteristics are linearised in a trial operating point; the initial guess of this operating point, the initialisation of a device, has an important impact on the rate of convergence and on whether the solution converges at all. A user can control the solution process through a set of options parameters [SI. The options available to a user to enhance the success rate of a simulation are developed below.
In addition to physical and model differences between bipolar transistors and MOSFETs, there are differences in the way SPICE processes the two types of devices. Thus, operating points in which the program initialises
the two types of devices differ, and so does the selection procedure of new operating points at each iteration. In the first iteration, an important difference between BJTs and MOSFETs is that, by default, the fomer are initial- ised conducting whereas, generally, MOSFETs are ini- tialised cut off. MOSFETs are initialised with V,, = VTO and the difficulty with MOSFETs is that the actual threshold voltage V,,, is usually increased by backgate bias to a higher value than the zero-bias threshold voltage VTO. Only MOSFET devices with subthreshold current, defined by model parameter N F S , are initially in the conduction state. This is one example where con- vergence can be improved by changing model param- eters.
The default initialisation of transistors has a different impact on convergence depending on the operation of the circuit. A smaller number of iterations has been noticed for analogue (linear) bipolar circuits as compared to digital (logic) bipolar circuits owing to the fact that BJTs are initialised as conducting in SPICE. The explanation can be found in the mode of operation of analogue cir- cuits which have the majority of the transistors turned on in contrast to digital circuits which have an important percentage of the devices turned off. Experiments in the SPICE code which initialised all MOSFETs in the con- duction state have proven to speed up the convergence of analogue circuits. A user can gain access to initilisation through the device initial conditions, IC = ub0, uBso, ubsO, which are activated only in transient analysis in conjunc-
270 I E E Proc.-Circuits Devices Syst., Vol. 141, No. 4, August 1994
M1 M2 MS M3 M4 MREF2 MODEL N N N P P N ID 1.04E-05 1.36E-05 2.41E-05 -1.04E-05 -1.36E-05 5.00-05 VGS 0.762 0.772 0.822 -0.782 -0.782 0.822 VDS 4.190 2.380 0.028 -0.782 -2.592 0.822 VBS -0.028 -0.028 0.000 0.000 0.000 0.000 VTH 0.756 0.756 0.744 -0.735 -0.735 0.744 VDSAT 0.033 0.39 0.077 -0.060 -0.059 0.075 GM 4.14E-04 4.60E-04 2.16E-04 2.52E-04 3.32E-04 8.44E-04 GDS 3.99E-07 6.48E-07 8.85E-04 2.10E-06 1.95E-06 3.57E-06 GMB 2.12E-04 2.34E-04 1.13E-04 8.42E-05 l . l lE -04 4.32E-04 CBD 5.75E-13 7.19E-13 1.42E-12 6.48E-13 4.43E-13 1.01E-12 CBS 1.41E-12 1.41E-12 1.44E-12 9.10E-13 9.09E-13 1.44E-12 CGSOVL O.OOE+OO O.OOE+OO 0.00E+00 0.00E+00 0.00E+00 0.00E+00 CGDOVL O.OOE+OO O.OOE+OO 0.00E+00 O.OOE+OO 0.00E+00 0.00E+00 CGBOVL O.OOE+OO O.OOE+OO 0.00E+00 O.OOE+OO O.OOE+OO 0.00E+00 CGS 1.1 1 E-13 1 .ll E-13 9.24E-14 1 . l l E-13 1.1 1 E-13 1.1 1 E-13 CG D O.OOE+OO O.OOE+OO 7.13E-14 O.OOE+OO O.OOE+OO O.OOE+OO CG 8 O.OOE+OO O.OOE+OO 0.00E+00 O.OOE+OO O.OOE+OO O.OOE+OO
*t*t SMALL-SIGNAL CHARACTERISTICS
V(4)/VINP INPUT RESISTANCE AT VlNP OUTPUT RESISTANCE AT V(4)
JOB CONCLUDED TOTAL JOB TIME 0.47
Fig. 12 DC bias point of CMOS circuit for y+ = 0.79 V and = 0.8 V
= 1.975D+02 = 1.000D+20 = 4.1 26D+05
p. Fig. 13 CMOS differential amplijier with cascode loads
tion with the UIC, use initial conditions, option. The OFF state can also be specified for individual devices.
The importance of initialisation and device specifies for the convergence of MOS analogue circuits, especially those with high-impedance nodes often present in cascode loads, can be exemplified by the CMOS differen- tial amplifier in Fig. 13.
The attempt to find the DC operating point of the circuit in Fig. 13 as it is, fails in SPICE2 but succeeds in newer SPICE versions such as PSpice and SPICE3, after built-in convergence algorithms are exercised. Most of the newest generation SPICE simulators [12, 15, 18, 191
I E E Proc.-Circuits Devices Syst., Vol. 141, No. 4 , August 1994
have built-in convergence enhancing algorithms, based on continuation methods that are invoked automatically when a simulation fails. The three commonly used con- tinuation methods are source ramping, conductance ramping and transient ramping. PSpice uses only the first method while SPICE3 the first two methods; in both programs these algorithms are invoked automatically. SPICE2 can perform source ramping only when specifi- cally requested by the user.
Addition of the option ITM = 40 to the SPICE2 input which invokes the source ramping algorithm does not help for this circuit. It is important to note that
271
SPICE2 encounters problems in the solution of the circuit matrix; the messages P I V O T CHANGE ON THE FLYand *ERROR*: M A X I W M E N T R Y . . . ISLESS THAN P I V T O L can be found in the output file.
When source or conductance ramping fail for this type of difficult circuits, running a transient analysis while ramping the supplies from 0 to the DC value, or leaving them unchanged, may lead to a solution, If the supplies are ramped for part of the time interval, it is advised to preserve the DC value for the rest of the tiq, domain analysis to allow the circuit to settle. A time domain analysis of an MOS circuit has the additional advantage of a well conditioned matrix because charge storage ele- ments provide a finite conductance at the gates of MOSFETs. Note that a DC solution should be avoided by using the UIC keyword on the .TRAN line.
Several options can be modified for this circuit to obtain a solution in SPICE2; based on the observation of the condition of the circuit matrix, a first approach is to tighten the pivot selection criterion [SI by increasing the
value of PIVREL to lo-*. Secondly, due to the possible operation near threshold of some transistors, the absolute current tolerance ABSTOL can be raised to 1 PA.
These two options contribute to a successful time domain solution in SPICE2. An average value of the last time points is chosen to initialise the node voltages with a .NODESET statement. The DC operating point is obtained easily for this circuit when the node voltages are initialised.
The solution listed in Fig. 14 verifies that the bias point of the transistors in this circuit is very close to the boundary between subthreshold conduction, linear and saturation regions. The location of the bias point is the main cause for the convergence difficulty. Consider the input transistors of the differential pair, MI and M , ; VS. is set 25mV from the saturation voltage, and V,, is 250 mV above threshold.
An alternate way to find a solution for this circuit, and for amplifiers in general, is to cut the feedback loop and find a DC solution of the open loop amplifier. Then, the
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node voltages obtained from the open loop circuit can be used in a .NODESET statement to initialise the closed loop amplifier. The open loop solution for this circuit proves nontrivial.
The complexity of a model has an impact on con- vergence. An alternate approach to overcome model imperfections and convergence failure is to simplify the model down to the basic quadratic L E V E L = 1, defined by eqn. 17. This model is described by a single function which is continuous along with the first derivative. When changing models, a user should adjust the parameters such that the I-V characteristics predicted by the new model are close to the characteristics of the original model. This approach alone, or combined with a higher value of the ABSTOL option parameter, to overcome the sudden onset of current at the threshold voltage, can lead to a solution. The results of this solution can then be applied to initialise a simulation, using more complex models.
The DC bias point for the CMOS amplifier has been obtained only through transient ramping after attempt- ing DC solutions with different options parameters. For each circuit, there may be a different approach that leads to a solution when even built-in convergence algorithms fail; when the simulator fails to find a solution, it is useful to follow a set of guidelines outlined below.
First, in the case of a DC failure it is advised to under- take the following steps:
(i) Check the circuit for correct connectivity, NODE option, for component values, LIST option, and, for model parameters, MODEL option.
(ii) Increase ITLZ to 300 or 500. (iii) Set ITM from 20 to 100 in SPICE2 for source
ramping; the I T L 2 parameter may be changed in PSpice if the automatic source ramping fails.
(iv) Initialise as many nodes as known. (v) Add or delete modelled physical effects by
specifying or omitting different key model parameters. (vi) Relax convergence tolerances R E L T O L and
ABSTOL for obtaining a first solution; this solution can then be used for initialisation. ABSTOL can be raised in any case for MOSFET circuits to 10 nA or 100 nA.
(vii) Increase the minimum pn junction conductance option G M I N .
(viii) Add a large resistor to ground to very high impedance nodes if this does not change the behaviour of the circuit ; high-impedance nodes can cause a singular matrix error. This measure may not be. necessary if the SPICE program that is used has built-in conductance ramping.
(ix) Use a transient solution to arrive at the DC oper- ating point; it is important to have charge storage ele- ments in the circuit.
(x) For feedback circuits, cut the loop to achieve a first solution.
(xi) Large circuits should be partitioned in smaller building blocks and the results used to initialise the original circuit.
A more difficult convergence case is the failure of a tran- sient analysis with the message INTERNAL TIME STEP TOO SMALL IN TRANSIENT ANALYSIS. The following actions can be taken in this situation:
(i) Check circuit for charge storage and model param- eters that can cause unreasonable values; such a param- eter is FC, the coeficient for junction capacitance approximation under forward bias [SI. Also, avoid very
I E E Prof.-Circuits Deuices Syst., Vol. 141, No. 4, August 1994
wide value ranges, more than six orders of magnitude, for charge storage and other elements.
(ii) Increase I T U to 40; this is the number of iter- ations taken at each new time step before it is rejected.
(iii) Relax T E L T O L , ABSTOL. (iv) Use a different integration method such as second-
or third-order Gear; this option may not be available in all simulators.
(v) Reduce the maximum compute time step which can be specified on the .TRAN line.
(vi) Reduce R E L T O L ; this is contrary to point (iii) above, but may have the desired effect owing to the dif- ferent impact that this parameter can have [SI:
(a) defines the relative voltage and current tolerance for convergence
(b) controls whether the evaluation of a device is performed or bypassed, and
(c) sets the limit on the truncation error and there- fore defines the size of the internal time step; this effect may require to limit the maximum time step when RELTOL is relaxed.
During the nonlinear solution process, the partial deriv- atives of the device current must be computed and added to the circuit conductance matrix each iteration; this operation which is referred to as device linearisation is a time-consuming process and may not be necessary if the terminal voltages of the device do not change from one iteration to the next. In this case, the device does not need to be reevaluated, and the partial derivatives, linear- ised conductances, from the previous iteration can be used; this operation is called bypass.
When all else fails, there is always another resort: to use another SPICE simulator if it is available.
5 Conclusions
This paper has described some of the challenges facing analogue MOS circuit designers in simulation: the short- comings of SPICE MOS models, and the specific design constraints placed on biasing MOSFETs. The added accuracy achieved from modelling second-order physical effects may sometimes have a negative impact on simula- tion convergence. While better models are available in some commercial SPICE programs, it is important for designers to understand the limitations of the models they are using, and the need to characterise the behav- iour not only in terms of current but also conductances. A thorough characterisation of a device model for spe- cific parameters is important because the presence or extent of conductance discontinuities depends on model parameters. The standard SPICE2 MOSFET models are probably still the widest used owing to their universal availability and therefore, it is important for designers to know how to avoid some pitfalls described above.
Two common CMOS circuits have been presented to exemplify why convergence difficulties may arise. In spite of imperfections in the model, a correct solution can be found by following a number of convergence guidelines enumerated in the last part of this paper. It is also impor- tant to note that, while the result of a small-signal analysis may be in error if a transistor is biased very close to a model discontinuity, a large-signal analysis will predict the accurate performance of the circuit. A time domain analysis for finding the DC solution is also closer to the real world where a circuit reaches the DC bias point after the transitory behaviour initiated by connect- ing the circuit to a power supply. Therefore, a transient
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analysis should always be performed to find the DC bias point when the DC analysis fails and the SPICE program does not have built-in transient ramping.
On a final note, convergence problems in SPICE may often be indicative of a poor or marginal circuit design; experienced designers [17] note that SPICE convergence is not a problem, and that reliable designs that are going to perform according to specifications over process varia- tions, and component value tolerances converge in simu- lations.
6 References
1 TSIVIDIS, Y., and MASEITI, G.: ‘Problems in precision modelling of the MOS transistor in analogue applications’, IEEE Trans., 1984, CAD-3, pp. 72-79
2 TSIVIDIS, Y., and SUYAMA, K.: ‘MOSFET modelling for ana- logue circuit CAD: problems and prospects’. IEEE I993 custom integrated circuits conference proceedings, 1993
3 VLADIMIRESCU, A., and LIU, S.: ‘The simulation of MOS inte- grated circuits using SPICET. Memorandum UCB/ERL M80/7, University of California, Berkeley, March 1981
4 ANTOGNETTI, P., and MASSOBRIO, G.: ‘Semiconductor device modelling with SPICE (McGraw-Hill, New York, 1993,2nd edn.)
5 VLADIMIRESCU, A.: ‘The SPICE book’ (J. Wiley, New York, 1994)
6 SHEU, B.J., SCHARFETTER, D.L., and KO, P.K.: ‘SPICE2 imple- mentation of BSIM model’. ERL memo ERL M85/42, University of California, Berkeley, 1985
7 JENG, M.C.: ‘Design and modelling of deep-submicrometre MOSFETs’. ERL memorandum ERL M90/90, University of Cali- fornia, Berkeley, 1990
8 HUANG, J.H., LIU, Z.H., JENG, M.C., KO, P.K., and HU, C.: ‘A robust physical and predictive model for deepsubmicron MOS circuit simulation’. IEEE 1993 custom integrated circuits conference proceedings, 1993
9 CHARLOT, J.J.: ‘The unicel MOSFET model for analogue circuit simulation’, to be published
10 VELGHE, R.M.D.A., KLAASSEN, D.B.M., and KLAASSEN, F.M.: ‘Compact MOS modelling for analogue circuit simulation’. International electron-device meeting proceedings, 1993
11 VLADIMIRESCU, A., ZHANG, K., NEWTON, AX., PED- ERSON, D.O., and SANGIOVANNI-VINCENTELLI, A.L.: ‘SPICE version 2G user’s guide’. Department of EECS, University of California, Berkeley, 1981
12 JOHNSON, B., QUARLES, T., NEWTON, A.R., PEDERSON, D.O., and SANGIOVANNI-VINCENTELLI, A.L.: ‘SPICE3 version 3F user’s manual’. Department of EECS, University of Cali- fornia, Berkeley, 1992
13 MULLER, R.S., and KAMINS, T.1.: ‘Device electronics for inte- grated circuits’ (J. Wiley, New York, 1977)
