MOS DEVICES1

8/2/2019 MOS DEVICES1

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MOS Devices

Device Physics:

To design of an Integrated Circuit, one of two extreme approaches can be

taken:

- begin with quantum mechanics and understand solid-state physics, semi-

conductor device physics, device modeling and finally the design of circuits.

-treat each semiconductor device as a black box whose behavior is described

in terms of its terminal voltages and currents and design circuits with littleattention to the internal operation of the device.

What is MOS device?

-An MOS (Metal Oxide Semiconductor) structure is created by super imposingseveral layers of conducting and insulating materials to form a sandwich like

structure.


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MOS structures are manufactured using a series of chemical processingsteps.

-Oxidation of the silicon

-The diffusion of impurities into the silicon to give it certain conduction

characteristics.

-Deposition and etching of aluminium or other metals to provideinterconnection in the same way that a printed wiring board is constructed.

CMOS technology provides two types of transistor-

- n-type transistor (NMOS)

- p-type transistor (PMOS)Transistor operation based on electric field so the devices are also calledMetal Oxide Semiconductor Field Effect Transistor (MOSFET).


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MOS- Structure

n+ n+

S G D

p-substrate

Polysilicon

SiO2

G

D

S

G

D

S

NMOS NMOS- Symbol

p+ p+

S G D

n-substrate

PMOS PMOS-symbol

GG

S S

D D


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NMOS transistor is built with a p-type body and has regions of n-type

semiconductor adjacent to the gate called source and drain. Similarly,

A PMOS transistor is built with a n-type body and has regions of p-type

semiconductor adjacent to the gate called source and drain

- Each transistor consists of a stack of the conducting gate.

MOS- Structurecontd

- An insulating layer of SiO2.

- A silicon wafer also called the substrate.

Two types of Transistor :

Enhancement Mode Transistor

Depletion Mode Transistor


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n+

n+

S G D

p-substrate

Polysilicon

SiO2

NMOS- Enhancement Mode

Enhancement Mode Transistor

-Polysilicon gate is deposited on a layer of insulation over the region between source

and drain.

-Basic enhancement mode device in which the channel is not established and the

device is in non-conducting condition, VD=VS=Vgs=0.-A suitable positive voltage with respect to the source is applied to the gate, then the

electric field established between the gate and the substrate gives rise to a charge

inversion region in the substrate under the gate insulation.

-A conducting path or channel is formed between source and drain.


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Depletion Mode Transistor

n+ n+

S G D

p-substrate

Polysilicon

SiO2

Implant

NMOS- Depletion Mode

- A suitable impurities in the region between source and drain during manufacture

and prior to depositing the insulation and gate. Under this circumstance, source and

drain are connected by a conducting channel.

-The channel may be established under the condition Vgs=0.

-Now the channel may be closed by applying a suitable negative voltage to the gate.


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MOS Transistor Theory

MOS transistor is a majority-carrier device in which the current in a conducting

channel between the source and drain is controlled by a voltage applied to the gate.

In an NMOS transistor, the majority carriers are electrons.

In a PMOS transistor the majority carriers are holes.

The behavior of MOS transistor-

,

drain.

Top layer of the structure is a good

conductor, metal/poly-silicon.

Middle layer of the structure is a very thin

insulating film of SiO2 called gate oxide.

The bottom layer is the p-type doped body.

Gate- metal/polysilicon

SiO2

p-substrate


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Accumulation Mode

Gate- metal/polysilicon

p-substrate

SiO2

+-

Vg


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Depletion Mode

+-

0


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+-

Inversion Mode

Vg>Vt

Inversion Region

Depletion Region

-When a higher positive voltage exceeding a critical threshold voltage Vt is applied,

attracting more positive charge to the gate.

-The holes are repelled further and a small number of free electrons in the body areattracted to the region beneath the gate.

-This conductive layer of electrons in the p-type body is called the inversion layer.


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Vgs=0

n+ n+

+-

+-

S

G

D

Vgd

Cut-off: No Channel

MOS Operation

Cut-off mode

Ids =0

-The gate to source voltage Vgs is less than the threshold voltage.- No channel is formed between source and drain, so almost zero current flow

from drain to source.

-This mode of operation is called cutoff region.


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Linear:

Vgs>Vt

n+ n+

+-

+-

S

G

D

Vgd=Vgs

Vds=0

Linear mode

Channel FormedIds increase with Vds

Vgs>Vt +-

+-

S

G

D

Vgd>Vgs>Vt

n+ n+

0


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-The gate voltage is greater than the threshold voltage

-An inversion region of electrons called the channel connects the source

and drain, creating a conductive path.

-The number of carriers and conductivity increases with the gate voltage.

-The potential difference between drain and source is Vds=V s-V d.

Linear mode of Operation

-If Vds=0 i.e. Vgs=Vgd, there is no electric field tending to push current from

drain to source.

-When a small positive potential Vds is applied to the drain, current Ids flows

through the channel from drain to source.

-This mode of operation in termed linear, resistive or non-saturated region;

the current is increases with both the drain and gate voltage.


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Vgs>Vt +-

+-

S

G

D

VgdVgs- Vt

Ids

Saturation mode

-If Vdsbecomes sufficiently large that Vgd


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Threshold Voltage

The input potential Vgs at which the surface just becomes inverted iscalled the threshold voltage V

t.

What affects the Threshold Voltage?

u s ra e op ng

Oxides thickness

Source-to-substrate voltage bias

Gate material

Surface charge density


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Metal Oxide (Si) Semiconductor (MOS) structure

Gate

voltage

vG

The surface charge in the semiconductor ( QS ) is controlledby means of the gate voltage ( vG)

Metal (n+poly-Si gate)

Gate oxide SiO2Thickness = tox

p- su strate

constant = ox

= electric potential across the semiconductor

)(vVv GsoxG +=

)(v

Gs

Vox = electric potential across the oxide


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tox

pSivGGate

voltage

The surface charge in the semiconductor ( QS ) is controlledby means of the gate voltage ( v

G

);

No perturbation far from the interface (equilibrium) !!

capacitance/cm2 of the oxide: Cox = ox/ tox

( ) ( )Gsox

sGs

ox

mGsoxG vC

Q

vC

Q

)(vVv +=+=+=

Qm: charge/cm2 in metal = -Qs: charge/cm

2 in semiconductor.

Charge in the metal QM= QS charge in the semiconductor


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Ideal MOS capacitor

No current can flow:

0=+=

dx

dn

qDdx

d

nqJ nnn nn q

kTD =

with

dnkTdnD

dn ==

dnkTd =

dxqdxdx nq

Integrating: =00 n

nssn

dn

q

kTd

=

kT

qnn ss

exp0

and similarly for holes:

=

kT

qpp ss

exp0

Different charge carrier concentrations at the surface can be

obtained by varying the surface potential ...


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Accumulation: vG < 0

Hole accumulation at theSi/SiO2 interface

vG

QM


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Depletion: 0 < vG < VTn

Depletion of holes at theSi/SiO2 interface

Fs 20


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Poisson equation for fully depleted SCR

=

==

d

d

s

A

s

xxdx

d

xxqN

dx

d

;0

0;

2

2

2

2

0)( ==dx

d

Boundary conditions:

Two integrations:

=

=

d

dd

s

A

xxx

xxxxqN

x

;0)(

0;)(2

)(2

2

2d

s

A

s xqN

=

s

A

s

dqN

x 2

=

At the interface: sx == ;0

sAsdAb qNxqNQ 2==


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Strong inversion: vG > VTn

An electron layer (inversion channel) is formed at the Si/SiO2interface QM(positive)

Inversion channel

pSi substrate

vG ( ) ( ) ( ) ( ) ( )

Fs 2

( )TnGoxi VvCQ =

Qb=-qNAwm

Qm

x

(x)

wm

depletion

Qi iFbsc Q)(QQ+=

2

Semiconductor charge/cm2:

For vG > VTn the electron

surface concentration is

not negligible any more.


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tox

pSiVG

( )Gs

ox

bG V

C

QV +=From:

The strong inversion threshold voltage of the ideal MOS

capacitor can be derived:

( ) ( ) Foxox

FAsF

ox

FbTn

/tqN

CQV 22222 +=+

=

It depends on the oxide thickness tox and on the substrate

doping concentration NA


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MOSFET Input Characteristics

The input characteristics relates drain current response to the input gate-source

driving voltage.

Since the gate terminal is electrically isolated from the remaining terminals, thegate current is essentially zero, so that the gate current is not part of thecharacteristics.

Figure 3-9 shows measured input characteristics for an nMOS and pMOS transistor

with a small 0.1V potential across their drain to source terminals.

NMOSPMOS


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The transistors are in their non-saturated bias states.

As VGS increases for the nMOS transistor in Figure, the threshold voltage isreached where drain current elevates.

For VGSbetween 0 V and 0.7 V, ID is nearly zero indicating that theequivalent resistance between the drain and source terminals is extremelyhigh.

Once VGSreaches 0.7 V, the current increases rapidly with VGS indicatingthat the equivalent resistance at the draindecreases with increasing gate-source voltage.

Therefore, the threshold voltage of the nMOS transistor is about Vtn

0.7 V.When a transistor turns on the current moves through a load.


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NMOS transistor Output Characteristics

MOS transistor output characteristics plot ID

versus VDS

for several values of

VGS.

Two conduction states are distinguished when the device is ON: the saturated

state and the non-saturated state. The saturated curve is the flat portion and

defines the saturation region.


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When the transistor is OFF (VGS< Vtn), then ID is zero for any VDSvalue.

For VGS> VDS+ Vtn, the transistor is in the non-saturation regionand thecurve is a half parabola.

For VGS< VDS+ Vtn, the NMOS device is conducting and ID is independent ofVDS.

The boundary of the saturation/non-saturation bias states is a point seen for

region with the quadratic curve of the nonsaturated region.

This intersection point occurs at the channel pinchoff voltage called VDSAT.

VDSAT is defined as the minimum drain-source voltage that is required to keep

the transistor in saturation for a given VGS .

In the non-saturated state, the drain current initially increases almost linearly

from the origin before bending in a parabolic response. Thus the name ohmic or

linear for the non-saturated region.


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CMOS Current (IDS) Equation

Consider an NMOS device,

We know,

when VGSVT , and if a constant VGS is applied then theresulting IDS versus VDS curve can be split into two regions.

- at resistive region when VDSVT

- Saturation region when VDS VGS-VT ; VGS>VT

For resistive region:

The voltage across the insulator at the source is VGS and at the drain is VGD.Although the voltage across the insulator is not constant, a voltage excess ofVT exists at all points across the oxide, causing


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The saturated and non-saturated states intersect at VDSAT where either equationdescribes the current and voltage relations. We can solve for this important bias

condition where the saturated and nonsaturated states intersect (VDSAT).


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The midpoint at zero slope defines the useful upper region of Equation for

resistive region and also defines the boundary between the saturated and

non-saturated bias states.

We can define the boundary bias condition by differentiating the equationwith respect to V

DS, setting the expression to zero, and then solving for the

conditions.

Terms cancel giving the important bias condition at the transition between

saturation and nonsaturation states as

VGS=VDS+VT

VDS=VGS-VT


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The equation can be extended to define the NMOS saturated bias

For saturation bias condition

VDS

>VGS

-VT

or, VGS


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PMOS Transistor Output Characteristics

PMOS transistor analysis is similar to the NMOS transistor with a major exception;

-Care must be taken with the polarities of the drain current and node voltage

-PMOS transistor majority carrier is the hole that emanates from the source into thechannel

Date post:	05-Apr-2018
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