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Mos Fetch 7 Intro

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Introduction to Metal-Oxide- Semiconductor Field Effect Transistors (MOSFETs) Chapter 7, Anderson and Anderson
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Page 1: Mos Fetch 7 Intro

Introduction toMetal-Oxide-

SemiconductorField Effect Transistors

(MOSFETs)

Chapter 7, Anderson and Anderson

Page 2: Mos Fetch 7 Intro

MOSFET• History• Structure• Future• Review• Threshold Voltage• I-V Characteristics• Modifications to I-V:

– Depletion layer correction (Sup. 3)– Mobility, Vsat– Short Channel Effects– Channel Length Modulation– Channel Quantum Effects

• MOSFET Scaling and Current Topics (Literature + Sup. 3)• Subthreshold Behavior• Damage and Temperature (Sup. 3)• Spice (Sup. 3)• HFET, MESFET, JFET, DRAM, CCD (Some in Sup. 3)

Page 3: Mos Fetch 7 Intro

MOSFET History (Very Short!)• First Patents:

– 1935• Variable Capacitor Proposed:

– 1959• Silicon MOS:

– 1960• Clean PMOS, NMOS:

– Late 1960s, big growth!• CCDs:

– 1970s, Bell Labs• Switch to CMOS:

– 1980s

Page 4: Mos Fetch 7 Intro

Structure: n-channel MOSFET(NMOS)

pn+n+

metal

LW

sourceS

gate: metal or heavily doped poly-Si G drain

Dbody

B

oxide

IG=0

ID=ISIS

x

y

(bulk or substrate)

Page 5: Mos Fetch 7 Intro

MOSFET Future (One Part of)

• International Technology Roadmap for Semiconductors, 2008 update.

• Look at size, manufacturing technique.

Page 6: Mos Fetch 7 Intro
Page 7: Mos Fetch 7 Intro
Page 8: Mos Fetch 7 Intro

From Intel

Page 9: Mos Fetch 7 Intro

Structure: n-channel MOSFET(NMOS)

pn+n+

metal

LW

sourceS

gate: metal or heavily doped poly-Si G drain

Dbody

B

oxide

IG=0

ID=ISIS

x

y

(bulk or substrate)

Page 10: Mos Fetch 7 Intro
Page 11: Mos Fetch 7 Intro

MOSFET ScalingECE G201

Page 12: Mos Fetch 7 Intro

Fin (30nm)

Gate

BOX

prevents “top” gate

Page 13: Mos Fetch 7 Intro

Circuit Symbol (NMOS)enhancement-type: no channel at zero gate voltage

G

D

S

B (IB=0, should be reverse biased)

ID= IS

IS

IG= 0

G-GateD-DrainS-SourceB-Substrate or Body

Page 14: Mos Fetch 7 Intro
Page 15: Mos Fetch 7 Intro

Structure: n-channel MOSFET(NMOS)

pn+n+

metal

LW

sourceS

gate: metal or heavily doped poly-Si G drain

Dbody

B

oxide

IG=0

ID=ISIS

x

y

(bulk or substrate)

Page 16: Mos Fetch 7 Intro

Energy bands

(“flat band” condition; not equilibrium) (equilibrium)

Page 17: Mos Fetch 7 Intro

Flatbands! For this choice of materials, VGS<0 n+pn+ structure ID ~ 0

pn+n+

n++

LW

sourceS

gateG drain

Dbody

B

oxide

+-

VD=Vs

Page 18: Mos Fetch 7 Intro

Flatbands < VGS < VT (Includes VGS=0 here). n+-depletion-n+ structure ID ~ 0

pn+n+

n++

LW

sourceS

gateG drain

Dbody

B

oxide

+-

+++

VD=Vs

Page 19: Mos Fetch 7 Intro

VGS > VT n+-n-n+ structure inversion

pn+n+

n++

LW

sourceS

gateG drain

Dbody

B

oxide

+-

+++++++++

- - - - -

VD=Vs

Page 20: Mos Fetch 7 Intro

VGS>VT

Channel Charge (Qch)

Qch

Depletion regioncharge (QB) is dueto uncovered acceptor ions

Page 21: Mos Fetch 7 Intro

pn+n+

n++

L W

Ec(y) with VDS=0

(x)

Page 22: Mos Fetch 7 Intro

Increasing VGS decreases EB

EB

y0 L

EF ~ EC

Page 23: Mos Fetch 7 Intro

Triode Region A voltage-controlled resistor @small VDS

G

pn+n+

metal

S DB

oxide

+-

++++++

- - - -

VGS1>Vt

pn+n+

metal

S DB

oxide

+-

++++++

+++

- - - - - -

VGS2>VGS1

pn+n+

metal

S DB

oxide

+-

++++++

+++

- - - - - - - - -

VGS3>VGS2+++

ID

VDS

0.1 v

increasingVGS

Increasing VGS puts more charge in the channel, allowing more drain current to flow

cut-off

Page 24: Mos Fetch 7 Intro

Saturation Regionoccurs at large VDS

pn+n+

metal

sourceS

gateG drain

Dbody

B

oxide

+-

+++++++++

VDS large

As the drain voltage increases, the difference in voltage between the drain and the gate becomes smaller. At some point, the difference is too small to maintain the channel near the drain pinch-off

Page 25: Mos Fetch 7 Intro

Saturation Regionoccurs at large VDS

pn+n+

metal

sourceS

gateG drain

Dbody

B

oxide

+-

+++++++++

VDS large

The saturation region is when the MOSFET experiences pinch-off.

Pinch-off occurs when VG - VD is less than VT.

Page 26: Mos Fetch 7 Intro

Saturation Regionoccurs at large VDS

pn+n+

metal

sourceS

gateG drain

Dbody

B

oxide

+-

+++++++++

VD>>Vs

VGS - VDS < VT or VGD <

VDS > VGS - VT

VT

Page 27: Mos Fetch 7 Intro

Saturation Regiononce pinch-off occurs, there is no further increase in

drain currentID

VDS

0.1 v

increasingVGS

triode

saturation

VDS>VGS-VT

VDS<VGS-VT

Page 28: Mos Fetch 7 Intro

Band diagram of triode and saturation

Page 29: Mos Fetch 7 Intro

Simplified MOSFET I-V EquationsCut-off: VGS< VT

ID = IS = 0Triode: VGS>VT and VDS < VGS-VT

ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS

2]Saturation: VGS>VT and VDS > VGS-VT

ID = 1/2kn’(W/L)(VGS-VT)2

where kn’= (electron mobility)x(gate capacitance)

= n(ox/tox) …electron velocity = nE

and VT depends on the doping concentration and gate material used (…more details later)

Page 30: Mos Fetch 7 Intro

Energy bands

(“flat band” condition; not equilibrium) (equilibrium)

Page 31: Mos Fetch 7 Intro
Page 32: Mos Fetch 7 Intro

VGS>VT

Channel Charge (Qch)

Qch

Depletion regioncharge (QB) is dueto uncovered acceptor ions

Page 33: Mos Fetch 7 Intro
Page 34: Mos Fetch 7 Intro
Page 35: Mos Fetch 7 Intro

Threshold Voltage Definition

VGS = VT when the carrier concentration in the channel is equal to the carrier concentration in the bulk silicon.

Mathematically, this occurs when s=2f ,

where s is called the surface potential


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