© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 1
Rochester Institute of Technology
Microelectronic Engineering
ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING
MOS Inverters
Dr. Lynn FullerWebpage: http://people.rit.edu/lffeee
Microelectronic EngineeringRochester Institute of Technology
82 Lomb Memorial DriveRochester, NY 14623-5604
Email: [email protected] webpage: http://www.rit.edu/kgcoe/microelectronic/
4-3-2017 MOS-Inverters.ppt
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 2
Rochester Institute of Technology
Microelectronic Engineering
OUTLINE
IntroductionVoltage Transfer Curve (VTC)Noise MarginInverter Current vs. VinPMOS InverterNMOS InverterCMOS InverterPseudo CMOS ReferencesHomework
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 3
Rochester Institute of Technology
Microelectronic Engineering
INTRODUCTION
There are many ways to make an inverter. In this document we will investigate various MOS inverters, their voltage transfer curve, current, noise margin, speed etc. The inverter is the simplest logic gate to analyze and can give useful results for the comparison of different inverter designs and fabrication technologies.
SYMBOL TRUTH TABLE
VIN VOUT VOUTVIN
0 1
1 0
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
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Rochester Institute of Technology
Microelectronic Engineering
INVERTER TYPES - VOUT VS VIN (VTC)
VIN
CMOS
+V
VO
SWITCH
VIN
+V
NMOS
ENHANCEMENT
LOAD
+V
VIN
VO
-V+V
+V0
0
+V0
0+V0
0
-V0
0
+V0
0
+V+V +V
VO
RESISTOR
LOAD
VIN
+V
VO
R
NMOS
V++
ENHANCEMENT
LOAD
+VV++
VIN
VO
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 5
Rochester Institute of Technology
Microelectronic Engineering
MORE INVERTER TYPES - VOUT VS VIN (VTC)
PMOS
ENHANCEMENT
LOAD
-V
VIN
VO
-V
-V0
0
+V0
0
+V
NMOS
ION IMPLANT
DEPLETION
LOAD
+V
VIN
VO
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 6
Rochester Institute of Technology
Microelectronic Engineering
VOLTAGE TRANSFER CURVE NMOS-RESISTOR LOAD
VIN VOUT
+V0
0
+VDD
ViL
Voh
VoL
Vih
VOUT
VIN
Idd
NML, noise margin low, D0 =ViL-VoLNMH, noise margin high, D1 =VoH-ViH
Slope = Gain
VinvRESISTOR LOAD
VIN
+VDD
VOUT
R
NMOS-M1
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
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Rochester Institute of Technology
Microelectronic Engineering
CALCULATION OF VTC
RESISTOR LOAD
VIN
+VDD
VOUT
R
NMOS-M1
First figure out if the transistor is sub-threshold or off, Vgs < Vth and Vgd < Vth non-saturation, Vgs > Vth and Vgd > Vth saturation region, Vgs > Vth and Vgd < Vth
Note: Vin = Vgs, Vout = Vds, therefore Vgd = Vin-VoutVth might be +1volt
+V00
+V
Vth
VOUT
VIN
M1
Off
M1
Saturation
M1
Linear
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
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Rochester Institute of Technology
Microelectronic Engineering
ID = µW Cox’ (Vg-Vt-Vd/2)Vd
L
CALCULATION OF VTC
Next calculate Vout = VDD – ID R using the correct equation for ID for the transistor depending on region of operation
+V00
+V
Vth
VOUT
VIN
M1
Off
M1
Saturation
M1
Linear
RESISTOR LOAD
VIN
+VDD
VOUT
R
NMOS-M1
ID
ID = µW Cox’ (Vg-Vt)2
2L
SaturationLinear (Non-Saturation)
Cox’ = Cox/Area = or/Xox
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 9
Rochester Institute of Technology
Microelectronic Engineering
CALCULATION OF VTC
M1 in Saturation Vout = VDD – R ID =
Cox’ = Cox/Area = or/Xox
o = 8.85e-14 F/cm
r=3.9 for oxide
Xox = gate oxide thickness
W= width of MOSFET
L=Length of MOSFET
Vt = Threshold Voltage
V - R µW Cox’ (Vin-Vt)2
2L
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 10
Rochester Institute of Technology
Microelectronic Engineering
CALCULATION OF VTC
M1 in Non-Saturation Vout = VDD –ID R
Vout = VDD –ID R = VDD - R µW Cox’ (Vg-Vt-Vd/2)Vd
LKx
Vo = VDD - R Kx(Vin-Vt-Vo/2)Vo
Vo = VDD - R Kx(Vin-Vt)Vo- RKxVo2/2
0 = VDD - R Kx(Vin-Vt - 1)Vo- RKxVo2/2
a x2 + bx + c = 0
x = -b +/- b2-4ac
quadratic formula
2a
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
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Rochester Institute of Technology
Microelectronic Engineering
CALCULATION OF VTC
M1 in Non-Saturation Vout = b +/- b2 -2VDD/KxR
b=(Vin – Vt + 1/KxR) 2a
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 12
Rochester Institute of Technology
Microelectronic Engineering
CALCULATION OF VTC
Note: Equations only valid in specific regions
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 13
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE – RESISTOR LOAD INVERTER - VTC
Vout1 Id
Vout vs Vin – Voltage Transfer Curve (VTC)
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 14
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE - INVERTER VTC – FOR DIFFERENT RL
R=1K
5K10k
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 15
Rochester Institute of Technology
Microelectronic Engineering
CADENCE PARAMETER SWEEPS
Select Parameters: from the “special” library and put on schematic. Then double click it. Select New Property. Give a Name and starting Value in Add New Property dialog box shown below.
Apply.
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 16
Rochester Institute of Technology
Microelectronic Engineering
CADENCE PARAMETER SWEEPS
Return to schematic and change the value of the resistor to {Rval} Including curly brackets
Where this is the new property name given in the attribute editor
The primary sweep is for V1, zero to 5 volts in small steps.
Parameter sweep can be a list of values as shown.
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 17
Rochester Institute of Technology
Microelectronic Engineering
CADENCE PARAMETER SWEEPS
V_V1
0V 1.0V 2.0V 3.0V 4.0V 5.0V
V(output)
0V
1.0V
2.0V
3.0V
4.0V
5.0V
R=1K
10K50K
Vin
V(output)
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 18
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE PARAMETER SWEEP
RL= 10K
50K
100K
Add the step command to the schematic
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 19
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE PARAMETER SWEEPS
Sweep SPICE parameter
VT0= 0.5, 1.0, 2.0
Sweep FET attribute
W= 5u, 20u, 40u
Sweep SPICE parameter
TOX= 10n, 20n, 30n
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 20
Rochester Institute of Technology
Microelectronic Engineering
CALCULATION OF NOISE MARGINS
Approach
Take derivative find where it is equal to -1
Typically D(V(out)) is -1 at two points
find VIL and VIH
VOH and VOL
Find point where Vin = Vout (switching voltage)
Find I
Find Voltage Gain
Find Power
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 21
Rochester Institute of Technology
Microelectronic Engineering
SPICE CALCULATIONS FOR NOISE MARGINS
1
2
VIL = 3.31
VIH = 6.95
VOH = 8.09
VOL = 3.37
D0 = VIL – VOL
=3.31-3.73= -0.42
D1=VOH-VIH=
=8.09-6.95=1.14
Max Gain = -1.32
RL = 1K
-1
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 22
Rochester Institute of Technology
Microelectronic Engineering
SPICE CALCULATIONS FOR NOISE MARGINS
1
2
VIL = 1.0
VIH = 2.91
VOH = 10.0
VOL = 0.91
D0 = VIL – VOL
=1.0-0.91= 0.08
D1=VOH-VIH=
=10-2.91=7.09
Max Gain = -7.2
RL = 10K
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 23
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE WITH MEASURE COMMANDS
NML
NMH
10K
50K100K
View
Error Log
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 24
Rochester Institute of Technology
Microelectronic Engineering
PSPICE WITH MEASURE COMMANDS
1K
10K
50K
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 25
Rochester Institute of Technology
Microelectronic Engineering
PSPICE WITH MEASURE COMMANDS
Run SPICE
Select Trace > evaluate measurement
Size for square grid
Use snipping tool
NML, noise margin low, D0 =ViL-VoL=3.68– 1.80 = 1.88
NMH, noise margin high, D1=VoH-ViH=4.52-2.07 = 2.45
ViL = 3.68ViH = 1.80VoL = 2.07VoH= 4.52
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 26
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD
NMOSENHANCEMENTLOAD
+V
VIN
VO
M2
M1
M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but an NMOS transistor with gate connected to the drain is smaller in size and also limits current. See the I-V characteristics. In the first quadrant the transistor approximates the resistor. However, Vout high is below VDD by the threshold voltage of M1
+V00
+V
Vt
VOUT
VIN
M2
Linear
M2
Off
M2 & M1
Saturation
+
V
-
V
I I
1/R
Vt
Vt
M1
ID = µW Cox’ (Vg-Vt)2
2LSaturation
Cox’ = Cox/Area = or/Xox
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 27
Rochester Institute of Technology
Microelectronic Engineering
DERIVATION OF GAIN EXPRESSION
+VDD
VIN
VO
M2
M1
Assume Vout = Vin and both transistors are in saturation for the steep part of the VTC. The current in M1 is equal to the current in M2 is equal. Also assume Vt is the same for both transistors.
W2/L2
W1/L1Gain =
I2 = I1µW2 Cox’/2L2 (VG-Vt)
2 = µW1 Cox’/2L1 (VG-Vt)2
W2 /L2 (VG-Vt)2 = W1/L1 (VG-Vt)
2
But, VG2 is VIN and VG1 = VO +Vt
(W2 /L2) (VIN-Vt)2 = (W1/L1) (VO +Vt -Vt)
2
Gain = d VO/d VIN
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 28
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD
Note: increasing L of the load is equivalent to increasing R
of a resistor load, Vout high is Vdd – VtM1 , Gain is shown.
G=2.2
G=5.5
G=9.5
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 29
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD AND V++ GATE BIAS
NMOS
ENHANCEMENT
LOAD V++ GATE BIAS
+V
VIN
VO
V++
M2
M1
M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but an NMOS transistor is smaller.
M1 is always on because the gate voltage is above the supply voltage. (Vgs is always above the threshold voltage. Vout max is the supply voltage.
The threshold voltage of M1 depends on source to substrate voltage for M1.
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 30
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD AND V++ GATE BIAS
G=2.2
G=5.5
G=9.5
Note: increasing L of the load is equivalent to increasing R
of a resistor load, Vout high is Vdd, Gain is shown.
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 31
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER – NMOS DEPLETION LOAD
VO
+V
VIN
NMOS
DEPLETION
LOAD
+
V
-
V
I I
1/R
Vt
Vt
M2 is the switch and M1 is the load. The load limits the current when M2 is on. In the first quadrant the transistor approximates the resistor. M1 is always on because its threshold voltage is set to zero or slightly negative by ion implant. Note: transistor M1 symbol has solid line between D and S.
M2
M1W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 32
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER – NMOS DEPLETION LOAD
* From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology
.MODEL RITSUBN7D NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=-1.0 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
Need a new SPICE model for the Depletion
mode NMOS. New model name and negative VTH0.
Using ion implant the VTH0 can be made negative.
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 33
Rochester Institute of Technology
Microelectronic Engineering
VTC NMOS INVERTER – NMOS DEPLETION LOAD
G=2.2
G=5.5
G=9.5
Note: increasing L of the load is equivalent to increasing R
of a resistor load, Vout high is Vdd, Gain is shown.
DD
D
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 34
Rochester Institute of Technology
Microelectronic Engineering
VTC PMOS INVERTER- PMOS ENHANCEMENT LOAD
PMOS
ENHANCEMENT
LOAD
-V
VIN
VO
M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but a PMOS transistor with gate connected to the drain is smaller in size and also limits current. See the I-V characteristics. In the first quadrant the transistor approximates the resistor. However, Vout high is below VDD by the threshold voltage of M1
M2
M1+
V
-
-V
-I I
1/R
Vt
Vt
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 35
Rochester Institute of Technology
Microelectronic Engineering
VTC PMOS INVERTER- PMOS ENHANCEMENT LOAD
-10 Volts is Logic High
0 Volts is Logic Low
Gain = 2
Note: Supply and input V is negative
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 36
Rochester Institute of Technology
Microelectronic Engineering
GAIN OF 2 INVERTER
Ld = 2l (20 µm)
Lu = 4 l (40 µm)Wu= 2l (20 µm)
Wd= 4l (40 µm)
(80 µm)
(50 µm)
Vout
Vdd
Gnd
Vin
W/L switch
W/L loadGain =
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 37
Rochester Institute of Technology
Microelectronic Engineering
INVERTER LAYOUT
L = 40µm
W = 20µm
L = 20µm
W = 50µm
W/L switch
W/L loadGain = = 2.34
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 38
Rochester Institute of Technology
Microelectronic Engineering
GAIN OF 3 INVERTER TEST RESULTS
Actual
Gain = -2.64
W is smaller than
drawn because of
lateral diffusion ~2u
Theoretical
Gain = - 3
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 39
Rochester Institute of Technology
Microelectronic Engineering
CMOS - CALCULATION OF VTC
First figure out if the transistor is
sub-threshold or off, Vgs < Vth and Vgd < Vth
non-saturation, Vgs > Vth and Vgd > Vth
saturation region, Vgs > Vth and Vgd < Vth
Note: Vin = Vgs, Vout = Vds, therefore Vgd = Vin-Vout
Vth might be +1volt
VIN
CMOS
+V
VO
NMOS
PMOS
+V0
0
+V
Vthn
VOUT
VIN
nmos
off
pmos
off
nmos & pmos
saturation
pmos sat
nmos linear
nmos sat
pmos linear
V-Vthp
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 40
Rochester Institute of Technology
Microelectronic Engineering
CMOS INVERTER
VIN VOUT
VIN
CMOS
+V
VO
Idd
+V0
0
+V
ViL
Voh
VoL
Vih
Imax
VOUT
VIN
Idd
Slope = Gain
Vinv
NML, noise margin low, D0 =ViL-VoLNMH, noise margin high, D1 =VoH-ViH
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 41
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE – CMOS INVERTER
NML, noise margin low, D0 =ViL-VoL = 2.2-0.5 = 1.7
NMH, noise margin high, D1 =VoH-ViH = 4.5-2.5 = 2.0
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 42
Rochester Institute of Technology
Microelectronic Engineering
LTSPICE WITH MEASURE COMMANDS
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 43
Rochester Institute of Technology
Microelectronic Engineering
PSPICE CMOS VTC WITH MEASURE COMMANDS
Run SPICE
Select Trace >
evaluate measurement
Size for square grid
Use snipping tool
NML, noise margin low, D0 =ViL-VoL=2.66–0.40= 2.26
NMH, noise margin high, D1=VoH-ViH=4.64-2.01 = 2.63
ViL = 2.66ViH = 2.01VoL = 0.395VoH= 4.64
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 44
Rochester Institute of Technology
Microelectronic Engineering
COMPARISON OF 10u, 1u AND 100n CMOS INVERTERS
RITALDN3/RITALDP3L=10u W=880uL=10u W=880u
RITSUBN7/RITSUBP7Ln=1u Wn=2uLp=1u Wp=2u
EECMOSN/EECMOSPLn=180n Wp=200nLn=180n Wp=200n
VDD = 5 volts VDD = 3.3 volts VDD = 2.5 volts
Imax=100uA
Gain=-33
Imax=21uA
Gain=-6
Imax=5.4mA
Gain=-90
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 45
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO – CMOS
There are situations where we want a large number of inputs. Rather than have CMOS where there will be many transistors in series (which will not work) we can use a single PMOS/NMOS transistor that is always on.
VA
CMOS
4 Input NOR
+V
VO
VB VC VD
VA
Pseudo CMOS
4 Input NOR
+V
VO
Idd
VB VC VD
VA
VB
VC
VD
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 46
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO – CMOS
There are situations where we want a large number of inputs. Rather than have CMOS where there will be many transistors in series (which will not work) we can use a single PMOS/NMOS transistor that is always on.
VIN
CMOS
+V
VO
Idd
VIN
Pseudo CMOS
Inverter
+V
VO
Idd
Pseudo CMOS
4 Input NAND
+V
VO
Idd
VA VB VC VD
+V
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 47
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO – CMOS INVERTER
No advantages over CMOS inverter
D0=1.0 , D1=3.0
W/L switch
W/L loadGain = 2/2
2/10 = 2.2=
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 48
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO – CMOS NOR
Note: noise margin ~ D0=1.3 , D1=2.8max current drive 50uAstatic current not zero for Vout=lowgate delay ?
W/L switch
W/L loadGain = 8/2
2/8 = 4=
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 49
Rochester Institute of Technology
Microelectronic Engineering
CMOS NOR-4
Note: noise margin ~ D0=1.2 , D1=3.2max current drive 50uAstatic current is zero gate delay ?
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 50
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO CMOS NAND
Sweep M7, M2 and M6 together
W/L switch
W/L loadGain = 6/2
2/6 = 3=
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 51
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO CMOS NAND
Sweep M7 only, M2 and M6 off
W/L switch
W/L loadGain = 2/2
2/6 = 1.7=
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 52
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO CMOS NAND
Sweep M7, M2 and M6 together
W/L switch
W/L loadGain = 6/2
2/2 = 1.7=
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 53
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO CMOS NAND
Sweep M7 only, M2 and M6 off
Does not work L of M1 needs to be larger or W of all PMOS wider (Gain too low)
W/L switch
W/L loadGain = 2/2
2/2 = 1.0=
switches
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 54
Rochester Institute of Technology
Microelectronic Engineering
PSEUDO CMOS NAND
This is how to check truth table
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Gain = 5.5
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 55
Rochester Institute of Technology
Microelectronic Engineering
REFERNCES
1. Hodges Jackson and Saleh, Analysis and Design of Digital Integrated Circuits, Chapter 4.
2. Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter 13.
3. Dr. Fuller’s Lecture Notes, http://people.rit.edu/lffeee
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 56
Rochester Institute of Technology
Microelectronic Engineering
HOMEWORK – MOS INVERTERS
1. Using SPICE obtain the VTC for a CMOS inverter with gate lengths of ~1um. Let the width of both transistors be 2um Determine the noise margins. Determine the maximum current and voltage gain. (Use the SPICE models given below) Make appropriate assumptions.
2. Repeat problem 1 for gate L and W of ~200nm.3. Given the layout shown below of a CMOS inverter find L, W,
AD, AS, PD, PS.4. The schematic below is for a tristate inverter. This device
should be able to make the output high or low when the enable (EN) is high. When the enable is low the inverter is effectively disconnected from the load (high impedance, Z). Use SPICE to show that this circuit operates as intended.
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 57
Rochester Institute of Technology
Microelectronic Engineering
INVERTER LAYOUT
Vin Vout
Vin
CMOS
+V
Vout
Idd
TRUTH TABLE
VOUTVIN
0 1
1 0
PMOS
NMOS
W = 40 µm
Lpoly = 2.0µm
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 58
Rochester Institute of Technology
Microelectronic Engineering
HOMEWORK – MOS INVERTERS
VIN
+V
VOEN
C
EN
Tristate Inverter
VOVIN
0 0 High Z
0 1 High Z
1 0 1
1 1 0
EN
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 59
Rochester Institute of Technology
Microelectronic Engineering
SPICE MODELS FOR CD4007 MOSFETS
*SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 8-7-2015*LOCATION DR.FULLER'S WEBPAGE - http://people.rit.edu/lffeee/CMOS.htm**Used in Electronics II for CD4007 inverter chip*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1.MODEL RIT4007N7 NMOS (LEVEL=7+VERSION=3.1 CAPMOD=2 MOBMOD=1+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)**Used in Electronics II for CD4007 inverter chip*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54.MODEL RIT4007P7 PMOS (LEVEL=7+VERSION=3.1 CAPMOD=2 MOBMOD=1+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pCLM=5+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 60
Rochester Institute of Technology
Microelectronic Engineering
SPICE MODELS FOR MOSFETS
* From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology
.MODEL RITSUBN7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology
.MODEL RITSUBP7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8
+VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
© April 3, 2017 Dr. Lynn Fuller
MOS Inverters
Page 61
Rochester Institute of Technology
Microelectronic Engineering
SPICE MODELS FOR MOSFETS
*4-4-2013 LTSPICE uses Level=8
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSN NMOS (LEVEL=8
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*4-4-2013 LTSPICE uses Level=8
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSP PMOS (LEVEL=8
+TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*