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MOS Transistors Models Andreas G. Andreou Pedro Julian Electrical and Computer Engineering Johns Hopkins University http://andreoulab.net
MOS Transistors Models
Andreas G. Andreou Pedro Julian Electrical and Computer Engineering Johns Hopkins University http://andreoulab.net
The MOS transistor – Levels of Abstraction-
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PHYSICAL MATHEMATICAL
Current – Voltage Characteristics
55nm SST Flash Cell
Vds
Ids
Symbol
NMOS PMOS
D
D S
S G G
B B
Model Equations
If VGS < 0IDS = 0
If VDS >VGS −VTO
IDS =WL
⎛⎝⎜
⎞⎠⎟UO2
⎛⎝⎜
⎞⎠⎟ε0εrTOX
VGS −VT( )2
If VDS <VGS −VTO
IDS =WL
⎛⎝⎜
⎞⎠⎟UO ε0εr
TOXVGS −VT( )VDS − VDS
2
2⎛⎝⎜
⎞⎠⎟
VT = VTO + γ φ −VBS − φ( )
SEM photograph Layout
S D
G
B
Model Current-Voltage Characteristics
What is a model?
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1. An intuitive and conceptual abstraction of a complex physical process 2. A mathematical abstraction of a complex physical process that is capable of predicting experimental observations.
What is a MODEL?
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1. An intuitive and conceptual abstraction of a complex physical process 2. A mathematical abstraction of a complex physical process that is capable of predicting experimental observations.
MOS fluidic analogy: a conceptual model (I)
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MOS Capacitor
MOS Transistor
From Mead and Conway
MOS Transistor Varia Bias
NMOS as a switch/resistor: a conceptual model (II)
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not a good one
PMOS as a switch/resistor: a conceptual model (III)
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not a good zero
What are the physical values for 0 and 1
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MOS switch model relation to I-V characteristics (I)
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With digital input on gate the device is either ON or OFF
180nm technology Vds
Ids
180nm technology Vds
Ids
MOS switch model relation to I-V characteristics (II)
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With digital input on gate the device is either ON or OFF Approximate ON with the blue line
RON ~ 3.3 V / 0.55 mA = 6K
What is a MODEL?
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1. An intuitive and conceptual abstraction of a complex physical process 2. A mathematical abstraction of a complex physical process that is capable of predicting experimental observations.
Conduction –ohmic- vs saturation
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Device operation characterized by the form of the current as a function of the bias voltage between the DRAIN and the source terminals (Vds)
Conduction (also known as Ohmic)
Saturation
Above threshold vs sub-threshold behaviour
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Device operation characterized by the form of the current as a function of the bias voltage between the gate and the source terminals (Vgs)
Weak Inversion (also known as Subthreshold)
MOS transistor mathematical model
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Mathematical model –above threshold-
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If VGS < 0IDS = 0
If VDS >VGS −VTO
IDS =WL
⎛⎝⎜
⎞⎠⎟UO2
⎛⎝⎜
⎞⎠⎟ε0εrTOX
VGS −VT( )2
If VDS <VGS −VTO
IDS =WL
⎛⎝⎜
⎞⎠⎟UO ε0εr
TOXVGS −VT( )VDS − VDS
2
2⎛⎝⎜
⎞⎠⎟
VT = VTO + γ φ −VBS − φ( )
Model parameters
Saturation
Ohmic
Above threshold vs sub-threshold behaviour
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Device operation characterized by the form of the current as a function of the bias voltage between the gate and the source terminals (Vgs)
Weak Inversion (also known as Subthreshold)
Mathematical model –subthreshold-
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ID ≡ IDS = S In0 expκ nVGBVt
⎛
⎝⎜⎞
⎠⎟exp
−VSBVt
⎛
⎝⎜⎞
⎠⎟− exp
−VDBVt
⎛
⎝⎜⎞
⎠⎟⎡
⎣⎢⎢
⎤
⎦⎥⎥
ID ≡ ISD = S I p0 exp−κ pVGBVt
⎛
⎝⎜
⎞
⎠⎟ exp
VSBVt
⎛
⎝⎜⎞
⎠⎟− exp
VDBVt
⎛
⎝⎜⎞
⎠⎟⎡
⎣⎢⎢
⎤
⎦⎥⎥
tkTVq
≡ S ≡WL
1 ox
ox dep
CC C
κη
≡ ≡+
I p0 = 0.5×10−18 A
In0 = 0.9×10−18 A
κ = 0.7Vt = 0.26Volts
Parameters:
Operating current for an NMOS
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EE271 Lecture 2SM 29
Operating Region for an nMOS Pulling Low
• Operates on one of two curves
• on
– Looks like a current source initially (high Vds)
– Looks like a resistor later (low Vds)
• off
– Open circuit always
IV Curve of ON device
vdd Ids
Vds
Operating current for a PMOS
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EE271 Lecture 2SM 30
Output current for an pMOS Pulling High
IV Curve of ON device
vss
Vds
• Same behavior as NMOS• Open circuit when
off
• Current source or resistor when on
Ids
Computer Aided Design Tools
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MICROWIND Tool Design Flow
Contact: Sales : [email protected] Support : [email protected]
SPICE Simulator (3rd Party)
Schematic Modeling Analog & digital Library models
Digital Simulation SPICE Extraction
DSCH 3
Tape out to FAB. CIF
Functional Simulation
Floorplanning
Place & Route
Programming File
.bit or .jed
IO Cards Traffic Light Controller, Key Pad, Display (LCD, 7 segs)
Synthesis
ModelSim / other
ProTHUMB Advance post layout
simulator
Analysis DRC, ERC
Delay Analyzer Crosstalk Analyzer 2D Cross section
3D Analyzer
Layout Conversion SPICE, CIF
Constraints
Technology rule files
MICROWIND 3
Verilog Extraction
Verilog File
nanoLambda Layout Editor
Verilog Compiler
Place & Route
Layout Extraction
FPGA / CPLD Boards
FPGA Tools
MICROWIND Tool
3rd Party Tools
LTSpice WindSpice
http://www.microwind.net
