MOSFET DC Models - SCU...MOSFET DC Models S. Saha HO #17: ELEN 251 - MOS DC Models Page 1 • In...

MOSFET DC Models

HO #17: ELEN 251 - MOS DC Models Page 1S. Saha

• In this set of notes we will

– summarize MOSFET Vth model discussed earlier

– obtain BSIM MOSFET Vth model

– describe Vth model parameters used in BSIM

– develop piece-wise compact MOSFET IDS models:♦ basic equations

♦ BSIM equations

– describe IDS model parameters used in BSIM

– develop substrate current Isub models to characterize device degradation due to high field effects.

BSIM Vth Model


We know that for uniformly doped substrate, Nsub, the long channel threshold voltage is:

A unified expression for Vth used to model the non-uniform vertical channel doping profile is:

where K1 and K2 model the vertically non-uniform doping effect on Vth.

tcoefficieneffect body 2

0 @ where 0

==

=≡

ox

subSi

BSthTH

CNqε

VVV

γ

( )φφγ sBSsTHth VVV −−+= 0 (1)

( ) BSsBSsTHth VKVKVV 210 −−−+= φφ (2)

BSIM Vth Model


We derived Vth model due to non-uniform vertical and lateral doping profile as:

( ) φφφ sLX

BSsBSsTHth LNKVKVKVV ⎟⎟

⎠

⎞⎜⎜⎝

⎛−++−−−+= 111210

(3) where

– VTH0 is a model parameter extracted from the measure IDSvs. VGS data at VBS = 0

– K1 and K2 models the effect of non-uniform vertical channel doping profile on Vth and are fitting parameter extracted from the measured data

– NLX models the non-uniform lateral profile on Vth and is a fitting parameter extracted from the measured data.

Modeling SCE due to DIBL


By solving Poisson Eq along the channel, Vth shift due to DIBL can be shown as:

∆Vth = θth(L)[2(Vbi - φs) + VDS] (4)

Vbi = built-in voltage of the S/D junctions given by:

where NDS = source-drain doping concentration NCH = channel doping concentration

Eq (4) shows that ∆Vth depends linearly with VDS. And,Vthdecreases as VDS increases due to DIBL.

⎟⎟⎠

⎞⎜⎜⎝

⎛= 2ln

i

DSCHbi n

NNq

kTV (5)

Modeling SCE due to DIBL


η = fitting parameter accounts for the approximations used to obtain lt.

In order to account for non-uniform vertical channel doping concentration, (15) is modified so that from (13):

( )CH

BSsSidep

ox

depOXSit

t

lL

lL

th

qNVX

XTl

leeL tt

−==

+=−−

φεηε

ε

θ

2 with

:bygiven length sticcharacteri a is where2)( Now, 2 (15)

( )

( ) DSBSTABTAlL

Dl

LD

sbil

LD

lL

D

VTdth

VVEEee

VeeDV

t

effSUB

t

effSUB

t

effVT

t

effVT

+++

−+=∆

−−

−−

02

20

)2(

)2(

00

11

φ

(16)

Narrow Width Effect - An Empirical Model


Vth shift due to narrow width effect can be shown as:

To model both narrow width and reverse narrow width effects, the model is expressed in terms of fitting parameters: K3, K3B, and W0 to get:

where W'eff = effective channel width. Introducing SCE in narrow devices, we add to (18):

seff

OXthW W

TV φ∝∆ (17)

seff

OXBSBthW WW

TVKKV φ0

33 )(+

+=∆ (18)

( )sbil

LWD

lLW

D

WVTWLth VeeDV tw

effeffWVT

tw

effeffWVT

φ−+=∆′

−′

−

)2(11 2

0 (19)

Complete Vth Model


(30)

( )

φφ

φφ

seff

OXbsBs

eff

LX

bssbssTHth

WTVKK

LNK

VKVKVV

′++⎟

⎟⎠

⎞⎜⎜⎝

⎛−++

−−−+=

)(11 331

210

1

2 3

( ) ( ) DSBSTABTAl

LD

lL

D

sbil

LD

lL

D

VT VVEEeeVeeD t

effSUB

t

effSUB

t

effVT

t

effVT

++−−+−−−−−

022

0 )2()2( 011

φ

4

( )sbil

LWD

lLW

D

WVT VeeD tw

effeffWVT

tw

effeffWVT

φ−+−′

−′

−

)2(11 2

0

Small L, W effect

“1” ⇒ vertical non-uniform channel doping effect “2” ⇒ lateral non-uniform channel doping effect “3” ⇒ narrow width effect “4” ⇒ SCE due to DIBL

Vth Model Parameters


TOX gate oxide thickness TOXM nominal TOX at which parameters are extracted XJ junction depth NCH channel doping concentration NSUB substrate doping concentration VTH0 threshold voltage @ Vbs = 0 for large L VFB Flat band voltage K1 first-order body effect coefficient K2 second-order body effect coefficient K3 narrow width coefficient K3B body effect coefficient of K3

Vth Model Parameters


W0 narrow width parameter NLX lateral non-uniform doping coefficient DVT0W first coefficient of narrow width effect on Vth at

small L DVT1W second coefficient of narrow width effect on

Vth at small L DVT2W body-bias coefficient of narrow width effect

on Vth at small L DVT0 first coefficient of SCE on Vth

DVT1 second coefficient of SCE on Vth

DVT2 body-bias coefficient of SCE on Vth

VBM maximum applied body bias in Vth calculation

Piece-Wise IDS Model: Inversion Layer Conductance


n

VG

Lx

W

P

xI

Let us apply a large potential at the gate of an MOS capacitor to cause inversion, i.e. VG > Vth.

The conductance, 1/RI of the inversion layer is:

dxxnx

qL

WR

g InI

I

I

)(1

0∫== µ (1)

Where, nI(x) = e- density in the inversion layer xI = depth of the inversion layer µn = e- mobility in the inversion layer

Inversion Layer Conductance


The inversion layer mobility, referred to as the surface mobility, µs ≈ 1/2 of bulk mobility. Now, the inversion layer charge per unit area is given by:

Assuming µs = constant, we get from (1) and (2):

The inversion layer resistance of an elemental length dyis:

Eq. (4) can be used to derive drain current for MOSFETs under appropriate biasing conditions.

dxxnx

qQ II

I

)(0∫−= (2)

QLWg IsI µ= (3)(− ⇒ e−)

QWdy

dRIs

I µ= (4)

Strong Inversion Region


n+ n+S D

G

P

Let us consider the following MOSFET structure. The gate bias VG provides the control of surface carrier densities.

If VG > Vth, an inversion layer exists. ∴ a conducting channel exists from D → S and current ID will flow. Vth is determined by the properties of the structure and is given by:

For VG < Vth, the structure consists of two diodes back to back and only leakage current flows (≈ Io of PN junctions); i.e., ID ~ 0.

CNq

C

QV

ox

FSiSUBF

ox

fMSth

)2(22

φεφφ ++−= (5)

Strong Inversion Region


Note:• The depletion region is wider around the drain because of

the applied drain voltage VD.• The potential along the channel varies from VD at y = L to 0

at y = 0 between the drain and source.• The channel charge QI and the bulk charge Qb will in

general be f(y) because of the influence of VD, i.e. potential varies along the L only ⇒ Gradual channel approximation.

+VD+VG

P

ID

QI(y) Qb(y)n+ n+

Inversionlayer

Depletionregion

y

x

0=y Ly =

Drain Current Model


From (4), the voltage drop across an elemental length dyin the MOSFET channel is:

Now, at any point in silicon the induced charge due to VGis: Qs(y) = QI(y) + QB(y) (7)

Again, VG = VFB − Qs/COX + φs (8)

Here VFB includes φMS and Qf. Combining (7) and (8): QI(y) = −{VG − VFB − φs(y)}COX − QB(y) (9)

Since the surface is inverted, φs ≅ 2φB (≡ 2φF) plus any reverse bias between the channel and substrate (due to VD or VBS). ∴φs(y) = V(y) + 2φB (10)

)(yQWdyIdRIdV

In

DID µ

== (6)

Drain Current Model


Also, we know from MOS capacitor analysis that the bulk or depletion charge at any point y in the channel is:

Note that as we move from S → D, V(y)↑ due to IR drop in the channel.∴ Xdep↑ as we move toward the drain and

Qb↑ as we move toward the drain.

Substituting (10) and (11) into (9), we get the expression for inversion charge:

]2)([2)()( BSUBSidepSUBb yVNqyXqNyQ φε +−=−= (11)

]2)([2

}2)({)(

BSUBSi

OXBFBGI

yVNq

CyVVVyQ

φε

φ

++

−−−−=

(12)

Basic Drain Current Model


Substituting (12) in (6), we get:

If we assume Qb(y) = constant, i.e. neglect the influence of channel voltage on Qb, then:

In (13) Vth includes the effects of φB, φMS, and Qb(y = 0).

Integrating within the limits:

( )dVyVNqCyVVVWdyI BSUBSioxBFBGsD ]2)([2}2)({ φεφµ +−−−−−=

(13)[ ]dVyVVVCW

dVC

yVNqyVVVCWdyI

thGoxs

OX

BSUBSiBFBGoxsD

)(

]2)([22)(

−−−=

⎟⎟⎠

⎞⎜⎜⎝

⎛ +−−−−−=

µ

φεφµ

⇒⎭⎬⎫

⎩⎨⎧

==

⎭⎬⎫

==

DVVLy

toVy

00

DD

thGoxsD VVVVCL

WI ]2

[ −−= µ (14)

Basic Drain Current Model: Linear Region


Eq. (14) is the Level 1 MOSFET IDS model. If we define, κ ≡ µsCox = process transconductance β ≡ µsCox(W/L) = κ(W/L) = gain factor of the device

If VD < 0.1 V, we can simplify (15) to:

(16) shows that current varies linearly with VD. This is defined as the linear region of operation. From (16), the effective resistance between the source and drain is:

(15)DD

thGD VVVVI ]2

[ −−= β

(16)( ) DthGD VVVI −≅ β

(17)( )thGD

Dch VVI

VR−

≅=β

1


• ID Vs. VD from (15) with different VG show ID↓ for higher VD. While the measured ID saturates at higher VD. This discrepancy is due to the breakdown of gradual channel approximation near the drain–end of the channel at high VD.

• Eq. (15) is valid only as long as an inversion layer exists all the way from S → D.

Basic Drain Current Model: Linear Region

• The maximum value of ID vs. VD plots occurs at:VD = VG − Vth ≡ VDSAT = drain saturation voltage (18)

• For VD > VDSAT, a channel will not exist all the way to the drain.


Basic Drain Current Model: Saturation


Basic Drain Current Model: Saturation• When VD > VDSAT,

– e- travelling in the inversion layer are injected into the pinch-off region near the drain-end.

+VD > VDSAT+VG

P

n+

Inversion layerends (pinch off)

Depletionregion

n+

length ofpinch =Dl

VD

ID 6

5

4321

VG - Vth

LinearRegion Saturation

Region

– The high ε-field in the pinch-off region pulls e- into the drain.

– further increase of VD do not change ID (to a first order).

∴ ID ≅ constant for VD > VDSAT

– The boundary between the linear and the saturation regions is described by: VG − Vth = VDSAT.



Substituting (18) in (16), we can show that the saturation drain current is given by:

⇒ square law theory of MOSFET devices.

At VD > VDSAT, channel is pinched-off and the effective channel length is given by: Leff = L − ld = L(1 - ld/L)

Typically, ld << L, then from (20):

( )2

2 thGOXnDSAT VVCL

WI −≅ µ (19)

( ) ( )⎟⎠⎞

⎜⎝⎛ −

=−−

≅∴

Ll

IVVClL

WId

DSATthGOXn

dD

122µ (20)

⎟⎠⎞

⎜⎝⎛ +≅

LlII d

DSATD 1 (21)



Since ld depends on (VD - VDSAT), we can write:

Here, λ = channel length modulation (CLM) parameter.

)(11 DSATDd VVLl

−+≡+ λ (22)

( ))(1 DSATDDSATD VVII −+≅∴ λ (23)

From (23), ID = 0 at (VD−VDSAT) = −1/λ.

∴ λ can be extracted from the VD-intercept of ID vs. VD plots at ID = 0 as shown in Fig.

VG5

VG4

VG3

VG2

VG1

1/λ VD

ID VG5 > VG4 > VG3 > VG2 > VG1

0CLMtodue ageEarly volt1

=≡ CLMAVλ

Basic Drain Current Model: Summary


• Current Eq:

• Model Parameters:– VTO = threshold voltage at VB = 0– KP = process transconductance– GAMMA = body factor– LAMBDA = channel length modulation factor– PHI = 2|φB| = bulk Fermi-potential.

(24)

( ) ( ).12

]2

[

0

2DthG

DD

thG

VVV

VVVV

λβ

β

+−

−−

VG ≤ Vth (cut-off region)

VG ≥ Vth, VD ≤ VDSAT (linear region)

VG ≥ Vth, VD ≥ VDSAT (saturation region)

=DI

Basic Drain Current Model: Summary


• Assumptions: – gradual channel approximation (GCA) is valid– majority carrier current is negligibly (such as hole current for

nMOSFETs is neglected)– recombination and generation are negligible– current flows in the y-direction (along the length of the

channel) only– carrier mobility µs in the inversion layer is constant in the y-

direction– current flow is due to drift only (no diffusion current)– bulk charge Qb is constant at any point in the y-direction.

The accuracy of The basic model is poor even for long channel devices.

Bulk Charge Effect


In reality, Qb varies along the channel form the source at y = 0 to drain at y = L because of the applied bias VD. Then from (11) with back bias VBS we have:

For the simplicity of computation, we simplify (25) by Taylor series expansion and by neglecting higher order terms, we get:

)(2

]2)([2)()(

yVVC

VyVNqyXqNyQ

BSBox

BSBSUBSidepSUBb

++−=

++−=−=

φγ

φε

(25)

( ))(2)(2)( yVVyVVVCyQ BSBBFBGoxI ++−−−−−=∴ φγφ (26)

( )( )

( )( )

[ ])(.2)(2

5.02

...2

)(212)(

yVVCyVV

VC

VyVVCyQ

BSBoxBSB

BSBox

BSBBSBoxb

δφγφ

φγ

φφγ

++=⎥⎥⎦

⎤

⎢⎢⎣

⎡

+++≅

⎥⎥⎦

⎤

⎢⎢⎣

⎡−

+++=

(27)

Bulk Charge Effect


BF V+≅

φδ

25.0 where

,(27) and (26) From( )( )

{ }( )( )( )

( ))()(122

)(.22)(

)(22)(

)(2)()(

yVVVCyVVVVC

yVVyVVVC

yVVyVVVC

yQyVVVCyQ

thGox

BSBFFBGox

BSFBFBGox

BSFBFBGox

bBFBGoxI

αδγφγφ

δφγφ

φγφ

φ

−−−=

+−+−−−−=

++−−−−−=

++−−−−−=

+−−−−=

(28)

BSB V++≅≡

φγα

25.01factor chargebulk where (29)

models. advanced develop to(28) use willWe DSI

MOSFET IDS Model with Bulk Charge Effect


• Qb variation along the channel offers more accurate IDmodeling in the linear and saturation region.

• The simplified MOSFET drain current model using the bulk-charge factor α as a fitting parameter is given by:

(30)( ) ( ).1

2

]2

[

0

2DthG

DD

thG

VVV

VVVV

λαβ

αβ

+−

−−

VG ≤ Vth (cut-off region)

VG ≥ Vth, VD ≤ VDSAT (linear region)

VG ≥ Vth, VD ≥ VDSAT (saturation region)=DI

(31)( ) α/Where thGDSAT VVV −=

BSB V++=

φγα

25.01 (29)

High-Field Effects in IDS


• Surface mobility µs = constant assumed in MOSFET current expressions is not true under high VG and VD.

• As the vertical field Ex and lateral field Ey increase with increasing VG and VD, respectively, carriers suffer increased scattering. ∴ µs = f(Ex, Ey)

• For the simplicity of ID calculation an effective mobilitydefined as the average mobility of carriers is used:

(32)∫∫=invinv XX

seff dxyxndxyxnyx00

),(),(),(µµ

dVQL

WIDSV

IeffD ∫=∴0

µ (33)

Effect of High Vertical Electric Fields


In reality, µs is highly reduced by large vertical e-fields. The vertical e-field pulls the inversion layer e- towards the surface causing: VD

+VG

P

n+n+S

yx

Ex1 more surface scattering2 coulomb scattering due to

interaction of e- with oxide charges (Qf, Nit).

Since e-field varies vertically through the inversion layer, the average field in the inversion layer is: Eeff = (Ex1 + Ex2)/2 (34)

where Ex1 = vertical e-field at the Si-SiO2 interface Ex2 = vertical e-field at the channel-depletion layer interface.

From Gauss’ Law: Ex1 − Ex2 = Qinv/Ksεo and Ex2 = QB /Ksεo (35)

∴ From (34) & (35) we can show: Eeff = [(0.5Qinv + QB)]/Ksεo (36)

Universal Mobility Behavior


• In general, Eeff = [(QB + ηQinv)]/Ksεo

where for <100> Si η = 1/2 for electrons η = 1/3 for holes.

• Measured µeff vs. Eeffplots at low VD show:– a universal behavior

independent of doping concentration at high vertical fields.

– dependence on: 1) doping concentration and 2) interface charge at low vertical fields.

universal behavior



The experimentally observed mobility behavior is due to the relative contributions of different scattering mechanisms set by the strength of vertical e-fields:1 Coulomb

scattering by ionized impurities and oxide charges.

2 Phonon scattering

3 Surface roughness scattering at the Si-SiO2interface.



• Surface roughness scattering↑ as carrier confinement close to the interface↑ at high vertical e-fields. ∴ µeff↓ as Eeff↑.

• The experimentally observed universal behavior occurs because phonon scattering is weakly dependent on vertical e-fields.

• Deviations from the universal behavior occur in heavily doped substrates at low fields due to:– dominant ionized impurity scattering at low inversion charge

densities. ∴ µeff = f(Nch).– coulomb scattering by

♦ ionized impurities in the depletion region♦ oxide charges.

• Phonon scattering has the strongest temperature dependence on µeff .

Effective Mobility due to High VG


Substituting for Qb from Vth Eqn and QI in (36), we get:

The dependence of µeff on VG is described by an empirical relation:

Where µo = the maximum extracted value of low-field mobility at a

given doping concentration ≡ low-field surface mobility. ν ≅ 0.25 for electrons and ν ≅ 0.15 for holes. Ec ≅ 2.7x104 V/cm = critical e-field above which µo↓.

OX

thGSeff T

VVE6

+= (37)

(38)νµµ

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

0

0

1EEeff

eff

Mobility Degradation due to VG


By Taylor’s series expansion of (38) and introducing VBSdependence, the vertical field mobility degradation model can be shown as:

where Ua and Ub are the model parameters extracted from ID- VG characteristics.

The VBS dependence is included by model parameters Uc:

20

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛ ++⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++

=

OX

thGSb

OX

thGSa

eff

TVVU

TVVU

µµ (39)

( )2

0

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛ ++⎟⎟

⎠

⎞⎜⎜⎝

⎛ +++

=

OX

thGSb

OX

thGSBSca

eff

TVVU

TVVVUU

µµ (40)

Effect of High Lateral Electric Fields


Additional complication arises because of the high lateral e-fields.

We see that for e- in silicon vd saturates near E ~ 104

V/cm and vd = µE does not hold.

Since average e-field for short channel devices > 104

V/cm.

∴small geometry MOSFET devices will operate at vd = vsat ≅ 107 cm/sec.

Since µ ≠ constant, we must account for high lateral e-field effects in the expression for ID derived from simple theory.

Mobility Degradation due to VD


• The velocity saturation of inversion carriers due to increased lateral field Ey causes:– current saturation sooner than predicted by VDSAT = VG – Vth

– lower IDSAT than predicted by simple theory.

• The drift velocity due to high field effect is given by:

Where EC ≡ vsat/µeff = critical lateral field for velocity saturation β = 2 for electrons; β = 1 for holes.

• For simplicity of numerical solution, β = 1 is used.

( )[ ] c

Cy

yeffd EE

EE

Ev >

+= for,

11 ββ

µ

satyeff

yeffd vE

Ev

µµ

+=∴

1 (41)

Mobility Degradation due to VG and VD


• The effective mobility due to the combine effect of VG and VD is given by:

Where − θC ≡ 1/LEC

– L = channel length of MOSFETs.

• Thus, µeff is modeled by the parameter set:– {(µ0, θ, θb, vsat (EC)}.

– the model parameters are obtained by curve fitting the experimental data to the model equation.

( ) DcBbthGeff VVVV θθθ

µµ++−+

=1

0 (42)

IDS Model in Strong Inversion


vsat

v

EcE

µo

Assume a piecewise linear model, i.e., vd saturates abruptly at E = Ec:

( )

( )csat

c

c

effd

EEv

EE

EEE

v

≥=

≤+

=

,1

,

µ

(43)

Where E = lateral e-field and Ec = critical e-field at which carriers are velocity saturated, i.e. v = vsat.

Now, the current at any point y in the channel is given by: ID = I(y) = WCox[VG − Vth − αV(y)]v(y) (44)

Where V(y) = potential difference between the drain and channel at y. v(y) = carrier velocity at any point y in the channel.



Substituting (43) in (44) we get:

Integrating (45) from y = 0 to y = L with corresponding V(y) = 0 to V(y) = VD, we get in the linear region (VDS ≤VDSAT) current:

[ ] dyydV

EIyVVVCW

IyE

c

DthGoxeff

D )(

)()( −=

−−−=

αµ (45)

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎠⎞

⎜⎝⎛ −−

=

LEVL

VVVVCWI

c

DS

DSDSthGoeff

D

1

21 αµ

(46)



Let us define, VDSAT ≡ the drain saturation voltage due to vsat, i.e. at E = Ec.

Using this condition in (45), we get in the saturation region (VDS ≥ VDSAT):

Including channel length modulation (CLM):

where VACLM = channel length modulation parameter

( )2

cDSATthGoxeffD

EVVVCWI

αµ −−= (47)

(48)( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛ −+−−=

ACLM

DSATDSDSATthG

coxeffD V

VVVVVECW

I 12

αµ



Since ID given by (46) and (47) must be continuous @ VDS= VDSAT, therefore, equating (46) = (47):

Note that from (43), vsat = µeffEc/2. Thus, the drain current models in strong inversion:

(49)( )

( )thGC

thGCDSAT VVLE

VVLEV−+

−=

α

DSATDSthGSDSDSthG

c

DS

oeffD VVVVVVVV

LEVL

CWI <>⎟

⎠⎞

⎜⎝⎛ −−

⎟⎟⎠

⎞⎜⎜⎝

⎛+

= ,for ,21

1α

µ

( ) DSATDSthGSA

DSATDSDSATthGsatoxD VVVV

VVVVVVvWCI >>⎟⎟

⎠

⎞⎜⎜⎝

⎛ −+−−= ,for ,1α

(50)

3. Sub-threshold Region Model


Simple long channel device equations assume: IDS = 0 for VGS< Vth. In reality, IDS ≠ 0 and varies exponentially with VGS in a manner similar to a bipolar transistor.

IDS

VGSVth

In order to develop a theory of sub-threshold conduction, let us consider MOS band diagram with applied source (S) and gate (G) bias measured with respect to the substrate (Sub), that is:– VSSub

– VGSub.

Ev

EF

Gate SiO2 p-Si

Eiφs

VGS

Ec

φB

VSSubVGSub

φs−VSSub− φF

Sub-threshold Region Model


In the sub-threshold (weak inversion) region, we know:

1 as EF is pulled above Ei, the number of minority carrier e−

at the surface increases exponentially with EF − Ei

2 when φs = 2φB, strong inversion (nsurf = pbulk) is achieved and we obtain Vth.

Ec

EiEF

EvφB

φs

3 For φs < 2φF, the dominant charges present near the surface are ionized acceptor atoms, i.e. nsurf << NA

−.♦ Thus, there is no ε-field laterally along the surface since

Poisson’s equation is the same everywhere.♦ Thus, any current flow must be due to diffusion only.



n+

P

n+- - - - - - -- - - - - - - - - - - - -

- - - - - --- - -- -

y →

NA−- - - - -

So few e- that εx = 0

dydnAqDID −=∴ (51)

4 The e- gradient along the channel (dn/dy) must be constant in order to maintain constant current.

∴ ID = −AqD[{n(0) − n(L)}/L] . . . (52)

Now, we can now use carrier statistics to calculate n(0) and n(L). Referring band diagram on page 41:

Where φs is the surface potential with respect to the substrate. Also, note that φs = constant along the channel [ε(y) = 0].

( )

( )kT

Vq

i

kTVq

iBDSubs

BSSubs

enLn

ennφφ

φφ

−−

−−

=

=

)(

)0( (53)

(54)



Since the charge in the substrate is assumed uniform (Nsub), then from Poisson’s equation:

∴ φ varies parabolically and E varies linearly with distance. Since the e- concentration falls off as e−qφ/kT away from the

surface, essentially, all of the minority carrier e- are contained in a region in which the potential drops by kT/q.∴ The depth of the inversion layer, Xinv = ∆φ/Es.

where ∆φ = kT/q, and Es is the ε-field at the surface. Again, from Gauss’ Law:

dxdEqN

dxd

s

A −==ε

φ2

2

(55)

sSUBsbss qNQE φεε 2=−= (56)

sSUB

s

sSUBs

s

inv qNqkT

qNq

kTX

φε

φε

ε

22==∴ (57)



Using (53), (54) and (57) in (52), we get:

Here A = WXinv. Using VDSub = VDS + VSSub,

To make use of this equation, we need to know how φsvaries with the externally applied potential VG.

( ) ( )

sA

skTVq

kTVq

iD qNqkTeeDn

LWqI

FDSubsFSSubs

φεφφφφ

2⎭⎬⎫

⎩⎨⎧

−=−−−−

(58)

( )

⎭⎬⎫

⎩⎨⎧

−⎭⎬⎫

⎩⎨⎧

=−

−−kT

qVkT

Vq

sSUB

siD

DSFSSubs

eeqN

kTDnL

WI 12

φφ

φε

(59)

ox

sSUBssFBGSub C

NqVV

φεφ

2++= (60)



Generally, it is more common to use the source potential as the reference so that: VGSub = VGS + VSSub

φs = ψs + VSSub

The depletion layer capacitance is: Therefore, from (62):

( )

⎭⎬⎫

⎩⎨⎧

−⎭⎬⎫

⎩⎨⎧

=∴−

−kT

qVkT

q

sSUB

siD

DSFs

eeqN

kTDnL

WI 12

φψ

φε

(61)

( )ox

SSubsSUBssFBGS C

VNqVV

+++=

ψεψ

2 (62)

( )SSubs

SUBsD V

NqC+

=ψ

ε2

(63)

( ) nCC

VNq

CddV

ox

D

SSubs

As

oxs

GS ≡+=+

+= 12

11ψ

εψ

(64)



In order to eliminate ψs from (61) we expand VGS in a series about the point ψs = 1.5φF (weak inversion corresponds to φF≤ ψs ≤ 2φF).

Where and is obtained from (62).

Combining (64) with (61) to eliminate ψs in the exponential and using (63) to eliminate the square root of ψs in (61), we obtain:

FsGSGS VV

φψ 5.1*

=≡

( )FsGSGS nVVFs

φψφψ

5.15.1

−+≅∴= (64)

( )

⎭⎬⎫

⎩⎨⎧

−⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎟⎟⎠

⎞⎜⎜⎝

⎛=

−⎥⎥⎦

⎤

⎢⎢⎣

⎡−

−

kTqV

kTq

nkTVVq

iDD

DSFGSGS

eenCq

kTL

WI 122 * φ

µ (65)



Thus, the sub-threshold current is given by:

From (47) we note that:• ID depends on VDS only for small VDS, i.e. VDS ≤ 3kT/q, since

exp[−qVDS/kT) → 0 for larger VDS.

• ID depends exponentially on VGS but with an “ideality factor” n > 1. Thus, the slope is poorer than a BJT but approaches to that of a BJT in the limit n → 1.

• NSUB and VSSub enter through CD.

( )

⎭⎬⎫

⎩⎨⎧

−⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎟⎟⎠

⎞⎜⎜⎝

⎛=

−⎥⎥⎦

⎤

⎢⎢⎣

⎡−

−

kTqV

kTq

nkTVVq

iDD

DSFGSGS

eenCq

kTL

WI 122 * φ

µ (66)

Sub-threshold Slope (S-factor)


In order to change ID by one decade, we get from (47):

1.E-12

1.E-111.E-10

1.E-091.E-08

1.E-07

1.E-061.E-05

1.E-04

0.0 0.2 0.4 0.6 0.8 1.0

VGS (V)

IDS

(A)

( )ndecade

mVCC

qkTSlope

o

D

60

110ln

≅

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

(@ room T)

Vth

⎟⎟⎠

⎞⎜⎜⎝

⎛+≅∴

⎟⎟⎠

⎞⎜⎜⎝

⎛+==⇒=

∂

CC

decadeImVS

CC

qkTn

qkTS

nkTVq

o

D

o

DGS

160

110ln)(10ln10ln

(@ room T) . . . (67)

Sub-threshold Model - Final Note


• In weak inversion or subthreshold region, MOS devices have exponential characteristics but are less “efficient” than BJTs because n > 1.

• Subthreshold slope S does not scale and is ≈ constant. Therefore, Vth can not be scaled as required by the ideal scaling laws.

• VDS affects Vth as well as subthreshold currents.

• In order to optimize S, the desirable parameters are:

– thin oxide

– low NA

– high VSub.



The sub-threshold current Eq. used in BSIM model is:

where Voff = offset voltage is a model parameter.

Thus, the piece-wise drain current models for different regions of MOSFET operations:

(68)( )

thGSoffthGDS

onDS VVnkT

VVVqnkTqVII <⎟⎟

⎠

⎞⎜⎜⎝

⎛ −−⎟⎠⎞

⎜⎝⎛ −−= for ,exp)exp(1

DSATDSthGSDSDSthG

c

DS

oxeff VVVVVVVV

LEVL

CW<>⎟

⎠⎞

⎜⎝⎛ −−

⎟⎟⎠

⎞⎜⎜⎝

⎛+

,for ,21

1α

µ

( ) DSATDSthGSA

DSATDSDSATthGsatox VVVV

VVVVVVvWC >>⎟⎟

⎠

⎞⎜⎜⎝

⎛ −+−− ,for ,1α

( )thGS

offthGDSon VV

nkTVVVq

kTqVI <⎟⎟

⎠

⎞⎜⎜⎝

⎛ −−⎟⎠⎞

⎜⎝⎛ −− for,exp)exp(1

=DI

MOS Threshold Voltage, Vth Extraction


Vth is obtained by linear extrapolation from the maximum slope to Ids = 0 of Ids - Vgs plot.

We know,

Define, Vth ≡ Vgs @ Ids = 0 and Vds = 50 mV

dsds

thgsds VVVVI ⎟⎠⎞

⎜⎝⎛ −−=

2β

2

02

dsgsth

dsds

thgsds

VVV

VVVVI

−=⇒

=⎟⎠⎞

⎜⎝⎛ −−=∴ β ID

VG

VD = 50 mV

2ds

gsthVVV −=

Substrate Bias Dependence of Vth


Vds = 0.05VTox = 1.5nm



Substrate bias dependence of Vth for uniformly doped substrate is given by:

γ is obtained from:

( )φφγ FSubFthth VVV 220 −±±=

factorbody2

where

≡=C

KNq

ox

ossub εγ

γ

Fφγ 2BSF V+φ2

0thth VV −

FBSFthth VVsVV φφ 22.)( 0 −+−

φγγ

2interceptslope

where

=−

=

y



Substrate bias dependence of Vth for non-uniformly doped substrate is given by the plots:

where γ1(k1) = body effect due to channel concentration

γ2(k2) = body effect due to substrate concentration.

Vth is given by:

FBSFthth VVsVV φφ 22.)( 0 −+−

)( 11 kγ

Fφγ 2BSF V+φ2

0thth VV −)( 22 kγ

( ) ( )φφγφφγ FSubFFSubFthth VVVV 2222 210 −−+−−+=

Drain Induced Barrier Lowering (DIBL)


• DIBL is defined as the shift in Vth due to Vds, especially, in short channel devices. DIBL is defined as:1) ∆Vth ≡ Vth(Vds-low) − Vth(Vds = Vdd)

2)

• DIBL is calculated from:– log(Ids) Vs. Vgs plots at

Vds-low = 50 mV Vds = Vdd.

Example: From Figure we get, ∆Vth ≅ (0.32 - 0.24) V

= 80 mV

)()()(

lowdsdd

dddsthlowdsth

ds

th

VVVVVVV

VV

−

−

−=−

≡∂∂

Sub-threshold Slope (S)


• S is the inverse of log(Ids) Vs. Vgs plot at Vds-low and is given by:

• To extract S:– extract:

Ids1 = Ids(Vth)Ids2 = 2 dec. below

Ids1

– Calculate slopeS = 1/slope.

( )⎥⎦⎤

⎢⎣

⎡⋅≡

)log(3.2

ds

gs

IddV

S

Ion and Ioff


• Ion and Ioff can be extracted from Ids − Vgs plot at Vds = Vdd.

• Ion ≡ Idsat atVds = Vgs = Vdd

• Ioff ≡ Ids atVds = Vdd

Vgs = 0

• Example: From Fig.,– Ion ≅ 440 µA/µm– Ioff ≅ 3 nA/µm

Home Work 7: Due June 2, 2005


VGS (V) VDS (V) VBS (V) ID (mA)2 5 0 405 5 0 5365 5 -5 3605 8 0 6445 5 -3 420

1) For a silicon MOSFET, considering bulk charge effect in current ID calculate (a) VTO, (b) LAMBDA, (c) GAMMA, and (d) BETAfrom the measured data shown in table.

2) If Eeff = [0.5Qinv + QB]/εsi, where Qinv and QB are the inversion charge and bulk/depletion charge under the gate, respectively and εsi is the dielectric constant of silicon. The dependence of surface mobility, µs on process parameters such as TOX , Nsub etc. and terminal voltages is lumped in Eeff. Assume VGS > Vth and small VDS:

(a) Show that Eeff ≅ (VGS + Vth)/6TOX.(b) If the effective mobility is modeled by: µeff = µ0/[1 + Eeff/E0)]η, where µs = µ0 @ VGS = 0

and E0 and η are parameters determined from the measured data. Use the expression for Eeff in part (a) to show that:

Where Ua and Ub are the model parameters that are determined experimentally.

20

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛ ++⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++

=

OX

thGSb

OX

thGSa

eff

TVVU

TVVU

µµ

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