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Page 1 of 33
University of North Carolina at Charlotte
Department of Electrical and Computer Engineering
Laboratory Experimentation Report
Name: Ethan Miller Date: July 31, 2014
Course Number: ECGR 3155 Section: L01
Experiment Titles: [8] MOSFET, [9] MOSFET Amplifier Configuration, [10] MOSFET
Amplifier Input/output
Lab Partner: None Experiment Numbers: 8, 9, 10
Objectives:
Experiment 8:
The intention of this experiment was to examine the basic regions of operation of
a single stage MOSFET transistor.
Experiment 9:
The purpose of this experiment was to examine the three different configurations
of a single stage MOSFET amplifier: common source, common gate and common drain
often called source follower to determine the midband voltage gain.
Experiment 10:
The purpose of this experiment was to examine the input, output impedances and
the midband voltage gain of a single stage MOSFET amplifier.
Equipment List:
Items Asset #
MB-106 Breadboard 00000001
CD4007UBE 00000002
Decade Resister Box 00000003
Agilent 33509B Function Generator 00000004
Agilent Infinii Vision 2000-X Oscilloscope 00000005
E3612A Power Supply 00000006
Agilent 34461A 6 ½ Digital Multimeter 00000007
Cadence Design System (P-Spice) 00000008
15KΩ, 22KΩ, 10KΩ, 16KΩ 00000009
1uF 00000010
Page 2 of 33
Relevant Theory/Background Information:
Experiment 8:
The MOSFET device is a four terminal device with connections called the drain,
gate, and the body, a symbol of a MOSFET is shown in Figure 1. The MOSFET body has
to be connected to ground in most situations to ensure the region of operation. Most
MOSFET chips have the body internally connected to ground but for diagrams in P-Spice
the body is always connected to ground or to the source terminal.
To understand how a MOSFET operates, two external DC power supplies are
connected and are called gate to source voltage and drain to source voltage, shown in
Figure 2. The drain to source voltage or known as VDS can cause a drain to source current
known as IDS. This path of the IDS current can be controlled by VGS. For example a high
VGS can cause effortless flow of IDS. This current of IDS acts like a channel, or like a
capacitor. The capacitor is form between the gate voltage and the channel region of the
MOSFET and the oxide layer acting as the dielectric. A positive gate voltage causes a
positive charge to collect on the topmost plate of the capacitor. The negative charge on
the lowermost of the capacitor is formed by electrons induced into the channel. Thus an
electric field develops in an upright direction. This field controls the amount of charge in
the channel, determines the channel conductivity and the current will flow through the
channel when a VDS is applied. Hence MOSFET means metal-oxide-semiconductor field-
effect transistor.
Figure 1: MOSFET Diagrams
To ensure that parallel plate capacitor is operating in the saturation region the
voltage across the oxide must exceed the threshold voltage. The threshold voltage is the
value of VGS at which the number of electrons accrues in the channel region to form a
conducting channel. The additional amount of VGS over the threshold voltage is called the
over drive voltage. This voltage is magnitude that determines the charge in the channel.
Figure 2: MOSFET Operation Circuit
A MOSFET has three different regions of operation called ohmic/triode,
saturation and pinched off point. For a MOSFET to operate as an amplifier the MOSFET
has to be in the saturation region. Saturation of MOSFET occurs when VDS is greater than
or equal to the overdrive voltage.
NMOSFET PMOSFET
000
VDS
VGS
Page 3 of 33
In this region VDS has no effect on the channel shape and charge of the drain
MOSFET. As soon as the VDS saturation was equal to the overdrive voltage, the current
through the drain is constant. Thus the constant current must saturate the MOSFET. The
saturation region only exists where the MOSFET operation curve when VDS increases
and the curve begins to flatten. The current flowing through the device in the saturation
region of operation is given in Equation 1. In the saturation region the MOSFET can be
connected to act similar to a diode shown in Figure 3.
(Eqn.1)
Triode region or known as the ohmic region occurs when VDS is less than or equal
to the overdrive voltage. In this region VDS has an effect on the channel of the drain
current at which the electrons flow through. In the creation of the MOSFET operation
curve the slope is proportional to the overdrive voltage, but as the curve starts to bend the
channel resistance was increasing proportional to VDS. The ohmic region only exists
where VDS is very small and the curve is linear. The current flowing through this device
in the triode/ohmic region is given by Equation 2. The two physical parameters of W/L
and are known as the transconductance. Also note that the ohmic region can be
used for a voltage controlled resister, where the drain to source resistance can be found
by Equation 3.
(Eqn.2)
(Eqn.3)
At the point when VDS saturation was equal to the overdrive voltage the channel
at the drain ends gives to a rise called pinch-off point. Here in this region of the MOSFET
found the value of the threshold voltage.
Figure 3: Diode Connected MOSFET
00
VDS=VGS
Page 4 of 33
Experiment 9:
There are three basic configurations and are generally defined as common source,
common gate, and common drain. Each one of this configurations exhibit different
characteristics for a more desirable design. Shown in Table 1 is the comparison between
the different MOSFET amplifiers. Normally, the common gate and the common source
have a lower frequency bandwidth than the common drain. This was found by the effects
caused by the internal capacitance and how the external capacitance is configured in the
amplifier. Another caused for the loss of bandwidth is the Miller Effect. The Miller effect
is a technique for replacing the bridge capacitance of the transistor by an input equivalent
capacitance.
Common-Source Common-Gate Common-Drain
Input Impedance High ( ) Low High
Output Impedance High Very High Low
Current Gain High ( ) Low ( ) High
Voltage Gain Medium High Low
Power Gain Very High Low Medium
Phase Gain 180 0 0
Table 1: MOSFET Comparison
Experiment 10:
In the prior experiments the DC biasing and AC amplification of a MOSFET have
been examine. This MOSFET experiment trial will build upon the previous experiments
as well be introduced to input and output impedances of a MOSFET amplifier. The
amplifier selected for this experiment is the common source shown in Figure 9.
Procedure for suitably biasing the MOSFET amplifier and setting up AC amplification
will be investigated as well as, techniques for measuring the input and output
impedances.
The input impedance of an amplifier is difficult measure, in the midband gain the
impedances is predominantly resistive. The input resistance/impedance is defined as the
ratio of input voltage divided by the input current. Input impedances are calculated from
the small signal circuit/AC Equivalent circuit by looking into the input with all current
source replaced as open circuit and voltages source as short circuits.
The importance of input impedances shows how low input impedances reflect on
the overall circuit as well as high input impedances. Low input impedances generally
have a poor low-frequency response and large power requirement. For example the
LM741 op-amp has high input impedance which results in a good low-frequency
response and low input power consumption. As well as output impedance play a role in
the circuit. Output impedance is restive in the midband gain and generally a complex
measure. To calculate the output impedance the load is removed and the impedance is
found by looking back into the small signal circuit/AC Equivalent circuit. Once again it is
essential all current sources with an open circuit and voltage sources with a short circuit.
The importance of the output impedance is the offer of power to an amplifier. The
idyllic output impedance is zero; an amplifier with low output impedance preserve a
larger output current without a major reduction of the output voltage.
Page 5 of 33
Experimental Data/Analysis:
Experiment 8:
Shown in Figure 4 was constructed to have a VGS at 2V, 1.9V and 2.4V. By
changing the VDS voltage the current IDS was changed. With VDS held at 5V the value of
the threshold voltage was found to be 1V, .81V and .71V when VDS saturation was
equaled to the overdrive voltage. Shown in Table 2 and Figure 7 shows the MOSFET
operation curve when VGS was held at a certain voltage and VDS was changing in
increments of .25V.
Saturation of MOSFET occurred when VDS was greater than or equal to the
overdrive voltage. In this region VDS had no effect on the channel shape and charge of the
drain current. As soon as the VDS saturation was equal to the overdrive voltage the
current through the drain was constant. Thus the constant current must saturate the
MOSFET.
Triode region or known as the ohmic region occurred when VDS was less than or
equal to the overdrive voltage. In this region VDS has an effect on the channel of the drain
at which the electrons flow through. In the creation of the MOSFET operation curve the
slope was proportional to the overdrive voltage, but as the curve started to bend the
channel resistance was increasingly proportional to VDS.
At the point when VDS saturation was equal to the overdrive voltage the channel
at the drain ends and gave a rise to a term called channel pinch-off. Here in this region of
the MOSFET the threshold voltage was found and was estimated to about 1V, .81V and
.71V. In this region current maintained to flow through the pinch off point in the channel
and the electrons that reached the drain ended up in the drain terminal which were
accelerated through the depletion region Also note that any increase in VDS that was
above VDS saturation, appeared as a voltage drop across the depletion region.
Figure 4: MOSFET Operation Circuit
Figure 5: MOSFET Resistance Circuit
nnMOS
0
00
VDS
VGS
Amps
nnMOS
00
VGS
Resistance
Page 6 of 33
Figure 6: MOSFET Diode Circuit
VGS
(V)
VDS
(V)
IDS
(µA)
VGS
(V)
VDS
(V)
IDS
(µA)
VGS
(V)
VDS
(V)
IDS
(µA)
2 0 0.0804 1.9 0 0.079 2.4 0 0.107
2 0.25 249.7 1.9 0.25 216.7 2.4 0.25 366.7
2 0.5 356.3 1.9 0.5 290.05 2.4 0.5 613.8
2 0.75 378.23 1.9 0.75 302.3 2.4 0.75 735.5
2 1 383.2 1.9 1 305.8 2.4 1 773.4
2 1.25 386.9 1.9 1.25 308.9 2.4 1.25 786.1
2 1.5 389.1 1.9 1.5 309.6 2.4 1.5 792.6
2 1.75 390.5 1.9 1.75 310.8 2.4 1.75 797.2
2 2 392.1 1.9 2 311.8 2.4 2 800.9
2 2.25 393.4 1.9 2.25 312.9 2.4 2.25 803.8
2 2.5 394.5 1.9 2.5 313.7 2.4 2.5 806.5
2 2.75 395.5 1.9 2.75 314.9 2.4 2.75 808.6
2 3 396.4 1.9 3 315.3 2.4 3 810.7
2 3.25 397.4 1.9 3.25 315.9 2.4 3.25 812.8
2 3.5 398.1 1.9 3.5 316.4 2.4 3.5 814.6
2 3.75 399 1.9 3.75 317.2 2.4 3.75 816.3
2 4 399.8 1.9 4 317.8 2.4 4 817.9
2 4.25 400.6 1.9 4.25 318.4 2.4 4.25 819.3
2 4.5 401.2 1.9 4.5 319.1 2.4 4.5 820.6
2 4.75 401.9 1.9 4.75 319.5 2.4 4.75 822.4
2 5 402.5 1.9 5 320.1 2.4 5 823.8
Table 2: MOSFET Operation
nnMOS
0
R
VDD
5Vdc
0
Volts
Page 7 of 33
Figure 7: CD4007UBE MOSFET Operation
VGS (V) Resistance (Ω) Calculated Resistance (Ω) Percent Error (%)
0 infinite infinite 0
1.5 1518.5 4962.77 69.40216855
1.9 839.52 2166.84 61.2560226
2 731.58 1899.33 61.48220688
2.4 506.701 1271.45 60.14778403
2.5 473.34 1174.39 59.69482029
3 455.887 849.97 46.36434227
4 286.379 547.49 47.69237794
5 225.791 403.79 44.08207236
Table 3: Ohmic Resistance of MOSFET
0
100
200
300
400
500
600
700
800
900
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5
Dra
in S
orc
e C
urre
nt
(µA
)
Drain Source Voltage (V)
CD4007UBE MOSFET Operation
VGS=2V
VGS=1.9V
VGS=2.4V
Saturation Region Vds > =Vov
Triode/ohmic
region
Vds ≤ Vov
Vds-sat = Vov
CD40007UBE MOSFET Operation
ECGR 3155-Systems and
Electronic Lab
Experiment # 8 MOSFET
Ethan Miller
Page 8 of 33
VDD
(V)
Resistance
Ω
IDS (A) VDS
(V)
Calculated VDS
(V)
Percent Error
(%)
5 33000 0.00010422
4
1.5606 2.004 22.1257485
5 15130 0.00021373
6
1.76618 2.234 20.94091316
5 11731 0.00026877 1.84706 2.327 20.62483885
5 9500 0.00032402
9
1.92172 2.410 20.26058091
Table 4: MOSFET Diode Voltages of Drain to Source
Shown in Figure 5 was constructed for the demonstration for the ohmic resistance as the
MOSFET operation curve was form. Table 3 showed these different resistances in the ohmic
region. When VDS was less than or equal to the threshold voltage the ohimc resistance was found
to be infinite or rather large. As the VDS was greater than or equal to the threshold voltage the
ohimc resistance decreased proportional to the increase in VDS. When VDS was kept small or
relatively close to 0V, the MOSFET behaved as a linear resistance, thus the value of gate voltage
was controlled. The MOSFET could be used for a voltage controlled resistance, and some
examples are audio and video frequency. It is necessary to create a voltage controlled resister
from MOSFET because a requirement of current for an input resistance of an electronic device.
Percentage Errors were calculated and were found to be around 40 to 60 percent error
between the measured and calculated values. This high percent error could have been caused by
the fact of the MOSFET had a different threshold voltage and transconductance parameter than
what was calculated by.
Shown in Figure 6 was constructed for the demonstration of a diode connection
MOSFET. Table 4 shows these different values of VDS, as the drain voltage was kept constant at
a nominal value of 5V. When there was a higher current flowing from drain to source, a higher
resistance was needed. The output voltage of VDS was increasingly proportional to the current
and resistance. Since the gate voltage was connected to the drain terminal the MOSFET was
always in the saturation region because VDS was greater than the threshold voltage. As VDS was
less than or equal to the overdrive voltage the MOSFET entered the triode region. This only
happened when VGS was less than the threshold voltage. As a result when the gate terminal was
connected to the drain terminal the MOSFET acted like a switch, hence a diode connected
MOSFET. A MOSFET would be connected like a diode to ensure a level of protection for a
standard diode in a circuit. The drain to source terminal of the MOSFET protected the output
from damage when the MOSFET is used as a switch in relays, switch motors and any inductive
circuits. VDD would be important voltage to set for a design to ensure the voltage at VDS is at
certain level to drive the proceeding circuit.
Page 9 of 33
Laboratory Computation
Percent Error
MOSFET in Triode/Ohmic Region
For
MOSFET in Saturation Region
Page 10 of 33
For
Pre-Lab
Page 11 of 33
Experiment 9:
A MOSFET amplifier was constructed and biased to ensure the amplifier was in
the saturation region for a specification of IDS = 400µA, VS = 4V, VD = 9V, VGS = 2.3V,
VT = 1.19V, and the transconductance (KN) value was 650 µA/V2. The resister values
were calculated and are shown in Equations 4, 5 and 6. Also shown under the laboratory
computation section are the calculated DC voltages for the MOSFET amplifier circuit.
The MOSFET had a saturation region requirement which was found to have a VDS
saturation greater than or equal to the overdrive voltage. The calculated VDS saturation
was found to be 1.11V which was much less than VDS. Shown in Figure 8 was the P-
Spice DC biasing for the MOSFET amplifier circuit. From the P-Spice simulation the DC
voltages and IDS current was found to be relatively close to the calculated values. Also
note the capacitors were open during the DC calculation analysis to ensure the AC
analysis was not affected by the DC analysis. During the simulation the AC signal went
through the capacitors and a DC signal was blocked. Capacitors were blocked because of
the complex quantity a capacitor had. The resistance of a capacitor equation was
and
when a DC signal was sent though the capacitor no frequency was measured. Hence
capacitors block DC signals and the resistance was infinite.
Figure 8: P-Spice DC Biasing Amplifier Circuit
Three different MOSFET amplifier configurations were constructed during the lab. The
following were the configurations common source, common gate and common drain. Show in
Table 5 was the measured DC voltages for each configuration. Also note that the phase angle
was measured and the observed value was found to be 90 degrees from the output AC signal to
the input AC signal. The DC voltages measured in the lab had the same value between the
different configurations.
Page 12 of 33
This was expected because each configuration needed to be biased in the same way to
ensure a comparison between the midband voltage gains and the MOSFET needed to be in the
saturation region. Each of these configurations was calculated to find the overall midband
voltage gain. This midband voltage gain was calculated from the small signal/AC equivalent
circuit. Gains for each of the configurations are shown in Equations 8, 9 and 10. In order to
calculate the midband voltage gain, gm (parameter which relates ids (AC current) and vgs (gate to
source AC voltage) in the MOSFET) was first calculated. Gm was found by calculating the
partial derivative of the total current through the MOSFET shown in Equation 7. The first term
in the equation was distinguished as the DC current of the MOSFET. The second term in the
equation was signified as the current which was directly proportional to the input signal vgs. The
third term in the equation was a current element which was proportional to the square of the
input signal vgs. This term was unwanted because it symbolized a nonlinear distortion. In order to
decrease this distortion, the input signal needed to be kept small so that vgs was much less than
the 2 times the overdrive voltage. When this was satisfied, the equation neglected the last term.
Thus resulting in the partial derivative of gm was KN (transconductance parameter) times the
overdrive voltage.
Configuration VD VG VS Phase (degrees)
Common Source 8.374 6.367 4.349 90
Common Gate 8.380 6.367 4.349 90
Common Drain 8.380 6.367 4.349 90
Table 5: Laboratory DC Voltages
Shown in Figures 9 and 10 were the constructed amplifier circuits for common source
and common gate. P-Spice was used to give a theoretical midband voltage gain measurement for
realistic lab values. Shown in Figures 11 and 12 were the P-Spice midband voltage gain and the
low and high cutoff frequencies. P-Spice measured the midband voltage gain at 4.3474 peak to
peak volts for the common source and 4.372 peak to peak volts for the common gate amplifiers.
These two configurations had very similar midband voltage gains as well as low and high cutoff
frequencies from the hand calculations and P-Spice simulations. The common source and
common gate midband voltage gain was measured by dividing the output voltage by the input
voltage. During the midband voltage gain of the P-Spice and laboratory graphs all of the internal
and external capacitors were acting as an open circuit and the dependent source of gm Vbs acted
like short (for current short source a short is an open circuit), shown in Figures 14 and 15 (High
frequency MOSFET amplifier circuit). Theses capacitors acted like a short because of the
amount of frequency at which the voltage gain was at. As descried earlier, the resistance
capacitor equation is
, the higher omega was, the smaller the resistance of the capacitor was.
In this case the resistance value was close to 0 ohms. Laboratory resulted for both the common
source and common gate MOSFET amplifiers were found to be around 5V.
Page 13 of 33
The common gate was found to be similar to the common source amplifier because of the
configuration the circuit and, since the input voltage was placed at the source terminal the input
voltage was equaled to negative quantity of VGS.
Figure 9: CD4007 MOSFET Common Source Amplifier Circuit
Figure 10: CD4007 MOSFET Common Gate Amplifier Circuit
RD
15K
R1
22K
R2
16KRS
10K
nnMOS
CG
1uF
VIN1Vac
VDD
15Vdc
0
RL
10K
CD
1uF
CS
1uF
RD
15K
R1
22K
R2
16KRS
10K
nnMOS
CG
1uF
VIN1Vac
VDD
15Vdc
0
RL
10K
CD
1uF
CS
1uF
Page 14 of 33
Figure 11: P-Spice CD4007 MOSFET Common Source Amplifier Voltage Gain
Shown in Figure 17 was the constructed amplifier circuit for common drain. P-Spice was
used to give a theoretical midband voltage gain measurement for realistic lab values. Shown in
Figure 18 was the P-Spice midband voltage gain and the low and high cutoff frequencies. P-
Spice measured the midband voltage gain at 784 millivolts peak to peak. P-Spice only showed
the low cutoff frequency because of the external capacitors, as the frequency got larger there was
no known high cutoff frequency shown. Reasons for this mistake can have caused a different
midband voltage gain, different IDS current through the MOSFET and the model for this
MOSFET could have been changed in the program called cadence design system (P-Spice). This
amplifier configuration was close to the midband voltage gain as well as low cutoff frequency
from the hand calculations and P-Spice simulation. The common drain midband voltage gain was
measured by dividing the output voltage by the input voltage. The laboratory resulted in 820
millivolts peak to peak for the midband voltage gain for this amplifier shown in Figure 19 and
Table 9. [1]
Page 15 of 33
Figure 12: P-Spice CD4007 MOSFET Common Gate Amplifier Voltage Gain
From all of these different configurations a table was generated to show the main
differences, shown in Table 8. This table shows the bandwidth, midband voltage gain, low and
cutoff frequencies. From observing the resulted values from the table, it seemed that the common
source and common gate can possibly be used for the same purpose in a design. As a result these
two amplifiers had similar resulted values. The only main differences between these two
amplifiers could be found in the input and output impedance, power gain, and the current gain,
which can be a major design specification in order to achieve a certain value at the output to a
preceding circuit. On the other hand the common drain was found to have a very low midband
voltage gain and a high bandwidth (passband). This specific amplifier would most probable be
used for a input stage to a multistage amplifier. In general an amplifier is used in a multistage to
achieve high midband voltage gains and to achieve a certain input and output stage. A common
drain usually has high input impedance and low output impedance. This design is great for a
input and output stage for a multistage amplifier since the current [2]cannot be affected for the
preceding circuit. If the current was to be affected the resulted voltage point in a simple voltage
divider or a power circuit can change. Resulting in changing these values could possible result in
a short in the circuit, the device would not function correctly and in the worst case scenario the
circuit can start to catch on fire due to the movement of electrons inside the wire. [3]
Page 16 of 33
Figure 13: Laboratory CD4007 MOSFET Amplifier Configuration
Figure 14: Common Source CD4007 MOSFET High Frequency Amplifier Circuit
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
5 50 500 5000 50000 500000 5000000
Gain
Volt
qage
(V/V
)
Frequency (Hz)
CD4007UBE MOSFET Amplifier Configuration
Common Source
Common Gate
CD4007UBE MOSFET Amplifier Configuration
ECGR 3155-System and Electronics Lab
Experiment #9 MOSFET Amplifier Configuration
Ethan Miller
R2
16K
ro
250K
R1
22K
RD
15K
RL
10K
VIN gm VGS
0 0 0
VGS++
GATE
gm Vbs
Csb
CdbCgs
Cgd
BODY
--VOUTVGS--
++VOUT DRAIN
SOUCRE
--Vbs
++Vbs
Page 17 of 33
Frequency
(Hz)
VIN
(mV)
Vout
(mV)
Gain (pk-
pk)
Frequency
(Hz)
VIN
(mV)
Vout
(mV)
Gain (pk-
pk)
10 101 3.2 0.0316831
7
10000 105 540 5.1428571
43
20 101 5.6 0.0554455
4
20000 105 540 5.1428571
43
40 103 8.7 0.0844660
2
40000 103 530 5.1456310
68
70 105 10.5 0.1 60000 103 520 5.0485436
89
80 105 15.3 0.1457142
9
80000 103 500 4.8543689
32
100 105 19.7 0.1876190
5
100000 103 470 4.5631067
96
200 105 48 0.4571428
6
200000 103 360 3.4951456
31
400 105 111 1.0571428
6
400000 101 221 2.1881188
12
600 105 165 1.5714285
7
600000 101 153 1.5148514
85
800 105 213 2.0285714
3
800000 103 117 1.1359223
3
1000 105 256 2.4380952
4
1000000 101 94 0.9306930
69
2000 105 394 3.7523809
5
1500000 101 64 0.6336633
66
4000 105 490 4.6666666
7
2000000 101 48 0.4752475
25
6000 105 510 4.8571428
6
2500000 103 39 0.3786407
77
8000 105 530 5.0476190
5
3000000 103 32.2 0.3126213
59
Table 6: Laboratory Tabular Results for a MOSFET Common Source Amplifier
Figure 15: Common Gate CD4007 MOSFET High Frequency Amplifier Circuit
ro
250K
RS
10K
RD
15K
RL
10K
VIN
gm VGS
0
VGS++
GATE
gm Vbs
Csb
CdbCgs
Cgd
BODY
--VOUTVGS--
++VOUT DRAIN
--Vbs
++Vbs
00
SOURCE
Page 18 of 33
Frequency
(Hz)
VIN
(mV)
Vout
(mV)
Gain (pk-
pk)
Frequency
(Hz)
VIN
(mV)
Vout
(mV)
Gain (pk-
pk)
10 106 10.2 0.0962264
15
10000 101 510 5.0495049
5
20 106 13.2 0.1245283
02
20000 101 510 5.0495049
5
40 105 15.3 0.1457142
86
40000 100 510 5.1
70 105 17.5 0.1666666
67
60000 98 490 5
80 105 20.2 0.1923809
52
80000 100 480 4.8
100 105 23.9 0.2276190
48
100000 98 460 4.6938775
51
200 105 54 0.5142857
14
200000 98 342 3.4897959
18
400 105 115 1.0952380
95
400000 96 213 2.21875
600 105 167 1.5904761
9
600000 96 147 1.53125
800 105 217 2.0666666
67
800000 96 113 1.1770833
33
1000 105 253 2.4095238
1
1000000 96 90 0.9375
2000 101 390 3.8613861
39
1500000 96 61 0.6354166
67
4000 101 470 4.6534653
47
2000000 96 47 0.4895833
33
6000 101 500 4.9504950
5
2500000 96 38 0.3958333
33
8000 101 510 5.0495049
5
3000000 98 30.6 0.3122448
98
Table 7: Laboratory Tabular Results for a MOSFET Common Gate Amplifier
Figure 16: Common Drain CD4007 MOSFET High Frequency Amplifier Circuit
ro
250K
R2
16K
RL
10K
gm VGS
VGS++
GATE
gm Vbs
Csb
Cdb
Cgs
Cgd
BODY
--VOUT
VGS--
++VOUT
DRAIN
--Vbs
++Vbs
R1
22K
RS
10K
VIN
0 0 0 0
SOURCE
Page 19 of 33
Figure 17: CD4007 MOSFET Common Drain Amplifier Circuit
Midband Voltage
Gain (V/V)
Lower Cutoff
Frequency (Hz)
High Cutoff
Frequency (Hz)
Bandwidth
(Hz)
Configura
tion
P-
Spice
Laborator
y
P-Spice Laborator
y
P-Spice Laborato
ry
P-
Spice
Labor
atory
Common
Source
4.3474 5.1428 133.059
7
1500 286947
00
150000 28694
567
14850
0
Common
Gate
4.372 5.0495 132.746
6
1500 271376
60
150000 27137
527
14850
0
Common
Drain
.784 0.8 48.215 300 N/A 1250000 N/A 12497
00
Table 8: Laboratory Tabular Results for MOSFET Configurations
RD
15K
R1
22K
R2
16KRS
10K
nnMOS
CG
1uF
VIN1Vac
VDD
15Vdc
0
RL
10K
CD
1uF
CS
1uF
Page 20 of 33
Figure 18: P-Spice CD4007 Common Drain MOSFET Amplifier Voltage Gain
Shown in Figures 14, 15 and 16 are the high frequency models for each the following
configurations: common source, common drain and common gate. In any of these amplifiers the
frequency was varied to find the midband voltage gain. As the frequency started to rise, in the
region between the 0 hertz to the low cutoff frequency the voltage increased by 20db.Here the
low cutoff frequency was determined by the external capacitors. Each capacitor played a major
role in the following equation
. [2]The equivalent resistance for each capacitor
was found by seen resistances when the input voltage was set to 0V and the other capacitors
were replaced by a short. Therefore the lowest cutoff frequency was determined by the highest of
the pole frequencies. In most cases the bypass capacitor at the source is this pole. A pole is where
the denominator of a transfer function (voltage gain) at a certain frequency where it equals zero.
Also note that the cutoff frequency can be found at which the output voltage is at 70.7% of the
maximum amplitude or from the equation
. From this result the higher the value of midband
voltage gain the smaller the bandwidth and the lower the midband voltage gain the larger the
bandwidth. [1]
Page 21 of 33
Figure 19: Laboratory Common Drain CD4007 MOSFET Amplifier Voltage Gain
The internal capacitors of MOSFET affect the physical operation inside the MOSFET
chip. These capacitors come from the depletion area between the diodes. The following are the
variety of capacitors: gate capacitance, source to body and the drain to body depletion
capacitance. The gate capacitance or normally called the gate electrode formed a parallel plate
capacitor with the channel, by having an oxide layer as the dielectric. This is made by a small
value of VDS which caused a current to flow through the channel. This current was transmitted by
the movement of free electrons voyage from source to drain. The movement or electron drift
velocity is defined by the following equation
and the charge per unit channel
length is defined as
. The next two capacitors deal with the
depletion are of the MOSFET. These capacitors are formed by the positive n source region
(source diffusion) in the reverse biased pn junction and the p type by the n positive drain region
(drain diffusion).
In order to find the high cutoff frequency the following equation must be applied
. The equivalent resistance for each capacitor was found by seen resistances when the
input voltage was set to 0V and the other capacitors were replaced by a short. Therefore the
highest cutoff frequency was determined by the lowest of the pole frequencies. [2]
-0.04
0.06
0.16
0.26
0.36
0.46
0.56
0.66
0.76
0.86
5 50 500 5000 50000 500000 5000000
Gain
Volt
age (
V/V
)
Frequency (Hz)
CD4007UBE MOSFETCommon Drain
Amplifier Configuration
CD4007UBE MOSFET Common Drain Amplifier
Configuration
ECGR 3155-Systems and Electronics Lab
Experiment #9 MOSFET Amplifier Configuration
Ethan Miller
Page 22 of 33
Frequency
(Hz)
VIN
(mV)
Vout
(mV)
Gain (pk-
pk)
Frequency
(Hz)
VIN
(mV)
Vout
(mV)
Gain (pk-
pk)
10 105 5.2 0.0495238
1
10000 105 86 0.8190476
19
20 105 7.6 0.0723809
5
20000 105 84 0.8
40 105 9.5 0.0904761
9
40000 105 84 0.8
70 105 12.4 0.1180952
4
60000 103 84 0.8155339
81
80 105 15.3 0.1457142
9
80000 103 84 0.8155339
81
100 105 18.5 0.1761904
8
100000 105 84 0.8
200 105 43 0.4095238
1
200000 101 82 0.8118811
88
400 105 67 0.6380952
4
400000 103 78 0.7572815
53
600 105 75 0.7142857
1
600000 103 72 0.6990291
26
800 105 80 0.7619047
6
800000 101 67 0.6633663
37
1000 105 82 0.7809523
8
1000000 101 60 0.5940594
06
2000 105 84 0.8 1500000 101 48 0.4752475
25
4000 105 84 0.8 2000000 101 40 0.3960396
04
6000 105 86 0.8190476
2
2500000 101 32.6 0.3227722
77
8000 105 86 0.8190476
2
3000000 103 28.7 0.2786407
77
Table 9: Laboratory Tabular Results for a MOSFET Common Drain Amplifier
Page 23 of 33
Laboratory Computation
MOSFET Biasing must be in the Saturation Region
(Eqn.4)
(Eqn.5)
Picked R2 16KΩ for voltage divider
(Eqn.6)
Midband Voltage Gain (V/V) with
Common source MOSFET amplifier
(Eqn.7)
(Eqn.8)
Page 24 of 33
Common Gate MOSFET amplifier
(Eqn.9)
Common Drain MOSFET amplifier
(Eqn.10)
Experiment 10:
In experiment 9 a MOSFET amplifier was constructed and biased to ensure the
amplifier was in the saturation region for a specification of IDS = 400µA, VS = 4V, VD =
9V, VGS = 2.3V, VT = 1.19V, and the transconductance (KN) value was 650 µA/V2. The
resister values were calculated and are shown in Equations 4, 5 and 6. Shown in Figure 8
was the P-Spice DC biasing for the MOSFET amplifier circuit. From the P-Spice
simulation the DC voltages and IDS current were found to be comparatively near to the
calculated values.
P-Spice was used to ensure a theoretical laboratory results to compare the
laboratory computation results. Shown in Figure 11 (experiment 9) was the P-Spice
midband voltage gain for a common source MOSFET amplifier. From experiment 9 the
laboratory computation was in close proximity to the P-Spice result.
Figure 20: P-Spice Input Impedance CD4007 MOSFET Common Source Amplifier
Page 25 of 33
Figure 21: Input Impedance CD4007 MOSFET Common Source Amplifier Circuit
Figure 22: P-Spice Output Impedance CD4007 MOSFET Common Source Amplifier
nnMOS
RD
15KR1
22K
R2
16K RS
10K
0
CS
1uF
CG
1uF
CD
1uF
RL
10K
VDD
15VdcVTEST1Vac
RTEST
1K
--VIN
++VIN
Page 26 of 33
Figure 23: Output Impedance CD4007 MOSFET Common Source Amplifier Circuit
Figure 24: Small Signal CD4007 MOSFET Amplifier Circuit
Two more graphs were generated in P-Spice, input and output impedances. These graphs
found the input impedance to be 9.264 kilohms and the output resistance was 15.103 kilohms.
These graphs were used from the input and output impedance circuit shown in Figures 21 and
23. The input impedance was formed by taking the test voltage divided by the test current and
the output impedance was taking in the same matter but the input voltage was shorted ( a voltage
source short was conducted by a line) and the load resister was disconnected.
During the lab a test resister of 1 kilohms was placed in the MOSFET amplifier circuit to
find the input and output impedances as the frequency was varied from10 hertz to 3 megahertz,
shown in Figures 21 and 23. The reason for this design was the need to find the current through
the voltage source. This was done by taking two oscilloscope probes at each end of the test
resister to measure the voltage drop. The current was found by using the equation of
. Therefore the input and output impedance was found by the following
equation
. [3]
nnMOS
R1
22K
R2
16K
RD
15K
RS
10K
RTEST1KCD
1uF
CS
1uF
CG
1uFVTEST
1Vac
VDD15Vdc
0
--VIN
++VIN
VINR2
16K
R1
22K
0 00 0 00
--VGS
DRAIN
++VOUTGATE
Source
++VGS
--VOUT
OUTPUT IMPEDANCEINPUT IMPEDANCE
gm Vgsr0
250K
RL
10K
RD15K
Page 27 of 33
The MOSFET observes the input and output impedance by the configuration of the
circuit. Since the test voltage was connected to the gate terminal, the only resistance that was
seen was the two bias resistors R1 and R2 in parallel. Given that the connection between the gate
terminal and the source terminal was never connected. Also, since a voltage was applied to the
gate terminal the input voltage was found at VGS, which turned on the MOSFET. On the other
hand the output impedance was found in the same manner but by applying a voltage at the output
does not turn on the MOSFET because the dependent current source was in dependence of VGS.
[4]
Figure 25: CD4007 MOSFET Input Resistance
From the tabular results of input impedance, shown in Table 10, a graph of the input
impedance was created and shown in Figure 25. The lab resulted in 9537.6 ohms; this was
exceptionally close to P-Spice and hand calculations. The lab resulted in a slight higher value
than P-Spice and hand calculation, this could have been diverted from the actual value by the
tolerances of the resisters.
0
2000
4000
6000
8000
10000
12000
1 10 100 1000 10000 100000 1000000 10000000
INP
UT
RE
SIS
TA
NC
E (Ω
)
FREQUENCY (Hz)
CD4007 MOSFET INPUT RESISTANCE
CD4007 MOSFET INPUT RESISTANCE
ECGR 3155-Systems and Electronics Lab
Experiment #10 MOSFET Amplifier Input/Output
Impedances
Ethan Miller
Page 28 of 33
Figure 26: CD4007 MOSFET Output Resistance
From the tabular results of the output impedance are shown in Table 11, a graph of the
output impedance was created and shown in Figure 26. The lab resulted in 16430 ohms; this was
similarly to what P-Spice and hand calculations. The lab resulted in a higher value than P-Spice
and hand calculation, this could have been diverted from the actual value by the tolerances of the
resisters and since the resisters had tolerances the current of drain to source could have changed
which may have changed the output resistance (r0).
Since the common source configuration had the same resister values as the common
source amplifier in experiment 9, the midband voltage gain and the DC voltages were found to
be similar. Shown in Figure 27 was a better diagram at the midband voltage gain MOSFET
common source amplifier. This voltage gain resulted in approximately 5 voltage peak to peak,
this was much higher than the P-Spice and hand calculation. The chip that was used was
CD4007UBE (1CCX6ZK E4) this chip may have had different characteristics of current flow
through the MOSFET.
0
5000
10000
15000
20000
25000
1 10 100 1000 10000 100000 1000000 10000000
INP
UT
RE
ISIS
TA
NC
E (Ω
)
FREQUENCY (Hz)
CD4007 MOSFET OUTPUT
RESISTANCE
CD4007 MOSFET OUTPUT RESISTANCE
ECGR 3155-Systmes and Electronics Lab
Experiment #10 MOSFET Amplifier Input/Output
Impedance
Ethan Miller
Page 29 of 33
Frequency
(Hz)
Vtest
(mV)
Vin
(mV)
Resistance
(Ω)
Current
(mA)
Output Resistance
(Ω)
10 111 101 993.5 0.010065425 10034.35
20 110 100 993.5 0.010065425 9935
40 109 99 993.5 0.010065425 9835.65
60 108 98 993.5 0.010065425 9736.3
80 107 97 993.5 0.010065425 9636.95
100 106 96 993.5 0.010065425 9537.6
200 106 96 993.5 0.010065425 9537.6
400 106 96 993.5 0.010065425 9537.6
600 106 96 993.5 0.010065425 9537.6
800 106 96 993.5 0.010065425 9537.6
1000 106 96 993.5 0.010065425 9537.6
2000 106 96 993.5 0.010065425 9537.6
4000 106 96 993.5 0.010065425 9537.6
6000 106 96 993.5 0.010065425 9537.6
8000 106 96 993.5 0.010065425 9537.6
10000 106 96 993.5 0.010065425 9537.6
20000 106 96 993.5 0.010065425 9537.6
40000 104 94 993.5 0.010065425 9338.9
60000 105 94 993.5 0.011071968 8489.909091
80000 105 93 993.5 0.01207851 7699.625
100000 105 91 993.5 0.014091595 6457.75
200000 103 80 993.5 0.023150478 3455.652174
400000 101 70 993.5 0.031202818 2243.387097
600000 101 68 993.5 0.033215903 2047.212121
800000 101 65 993.5 0.036235531 1793.819444
1000000 98 60 993.5 0.038248616 1568.684211
1500000 98 51 993.5 0.047307499 1078.053191
2000000 98 41 993.5 0.057372924 714.622807
2500000 98 35 993.5 0.063412179 551.9444444
3000000 98 29.3 993.5 0.069149472 423.7197962
Table 10: Laboratory Tabular Input Impedance
Page 30 of 33
Frequency
(Hz)
Vtest
(mV)
Vin
(mV)
Resistance
(Ω)
Current
(mA)
Output Resistance
(Ω)
10 108 20 97476 0.000902786 22153.63636
20 107 19.7 97476 0.000895605 21996.30241
40 109 19.1 97476 0.000922278 20709.58398
60 109 18.1 97476 0.000932537 19409.41254
80 113 18.5 97476 0.000969469 19082.60317
100 111 18.1 97476 0.000953055 18991.55651
200 111 17.1 97476 0.000963314 17751.22045
400 113 16.9 97476 0.000985884 17141.98127
600 109 15.7 97476 0.000957159 16402.71383
800 113 16.3 97476 0.000992039 16430.80455
1000 109 15.7 97476 0.000957159 16402.71383
2000 113 16.3 97476 0.000992039 16430.80455
4000 109 15.7 97476 0.000957159 16402.71383
6000 105 15.1 97476 0.000922278 16372.49833
8000 105 15.1 97476 0.000922278 16372.49833
10000 109 15.7 97476 0.000957159 16402.71383
20000 109 15.7 97476 0.000957159 16402.71383
40000 103 14.1 97476 0.000912019 15460.19798
60000 107 11.3 97476 0.00098178 11509.70533
80000 103 10 97476 0.000954081 10481.29032
100000 103 9.6 97476 0.000958185 10018.94647
200000 107 7.2 97476 0.001023842 7032.336673
400000 105 5.1 97476 0.001024868 4976.252252
600000 103 2.6 97476 0.001029997 2524.278884
800000 105 2.3 97476 0.001053593 2183.006816
1000000 103 1.8 97476 0.001038204 1733.762846
1500000 102 1.7 97476 0.001028971 1652.135593
2000000 101 1.6 97476 0.001019738 1569.030181
2500000 100 1.3 97476 0.001012557 1283.878419
3000000 100 1.1 97476 0.001014609 1084.16178
Table 11: Laboratory Tabular CD4007 MOSFET Output Impedance
Page 31 of 33
Laboratory Computation
(Eqn.11)
(Eqn.12)
0
1
2
3
4
5
6
1 10 100 1000 10000 100000 1000000 10000000
Gain
Volt
an
ge (
V/V
)
Frequency (Hz)
CD4007UBE MOSFET Common Source
Amplifier
CD4007UBE MOSFET Common Source Amplifier
ECGR 3155-Systems and Electronics Lab
Experiment #10 MOSFET Amplifier Input/Output
Impedances
Ethan Miller
Figure 27: CD4007UBE MOSFET Common Source Amplifier
Page 32 of 33
Conclusions:
Experiment 8:
In conclusion three different circuits were built in order to determine the operation
region of the MOSFET, the resistance between drain and source terminals and to
determine the diode characteristics inside the MOSFET. The CD4007 MOSFET found
three different regions of operation, the following operation regions were found:
saturation region, pinched off point and the ohmic/triode region. Each of the regions had
its importance to the MOSFET. The MOSFET only acted as an amplifier when the region
was found to be in the saturation region. During the ohmic region the MOSFET found an
internal variable resistance between the drain and source terminal. A change in voltage of
VGS changed the internal resistance in the MOSFET. Also found in the operation region
was the point at which VDS saturation was equaled to VDS. At this point the current IDS
was kept at a constant rate as the VDS were increased into the saturation region.
Found in the last circuit built (diode connected MOSFET) was found to act as a
diode since the gate terminal was connected to the drain terminal. As the gate and the
source were connected to each other the MOSFET was kept in the saturation region and
never entered into ohmic region.
Experiment 9:
In the development of the three different MOSFET amplifier circuits the common
drain and common gate had similar midband voltage gain as well as low and high cutoff
frequencies. An explanation for this result was the fact that where the input voltage was
positioned in each circuit ended up equaling the same amount which was found to be
VGS. The low cutoff frequency was determined by the external capacitors and the high
cutoff frequency was determined by the internal capacitors or distance between the two
diodes which formed a MOSFET. The common drain MOSFET amplifier had a
significant drop in midband voltage gain and a high bandwidth in compared to the other
configurations. This amplifier resulted in an approximate 1 volt peak to peak midband
voltage gain and a 1249700 hertz bandwidth.
Experiment 10:
In conclusion three circuits were built in order to find the midband voltage gain,
input and output impedances of a MOSFET amplifier. The midband voltage gain and DC
voltages resulted in a similar value as in experiment 9. A different chip which could have
had unusual current characteristics may have caused such a high value of voltage gain.
The input and output impedances were found to have close to the values found in P-Spice
and hand calculations. The output impedance was found to have a high value of
impedance due to the tolerance of resisters and the current flowing through the MOSFET.
Page 33 of 33
List of Attachments:
CD4007UBE Data Sheet
References: [8] Lab Handout “MOSFET”
[9] Lab Handout “MOSFET Amplifier Configuration”
[10] Lab Handout “MOSFET Amplifier Input/Output”
[1] "Electrial Network," 18 April 2011. [Online]. Available:
http://en.wikipedia.org/wiki/Electrical_network. [Accessed 21 Apirl 2011].
[2] "Chapter 8 MOSFET," West Virginia Univercity Department of Electrical and Computer
Engineering , 2 Feburay 2014. [Online]. Available:
http://www.csee.wvu.edu/digital/book/chapters/MOS2.pdf. [Accessed 9 July 2014].
[3] E. Project, "Power Supply For Intergrated Circuit," ElectronicsTutorials, 12 May 2014.
[Online]. Available: http://electronicsproject.org/power-supply-for-integrated-circuit-ics-and-
microprocessor/. [Accessed 3 June 2014].
[4] A. S. Sedra and K. C. Smith, Microelectronic Circuits, sixth ed., New York: Oxford
University Press, 2010.
[5] J. W. Nilsson and A. R. Susan, Electric Circuits, 9th ed., Saddle River: Pearson Prentice Hall,
2011.
This report was submitted in compliance with UNCC POLICY STATEMENT #105
THE CODE OF STUDENT ACADEMIC INTEGRITY, Revised August 24, 2008
(http://www.legal.uncc.edu/policies/ps-105.html) (ECM).