MRAM MRAM –– futurefuture ofofRandom Access Random Access MemoryMemory

Autorzy:Piotr BigajKonrad Mitka

PresentationPresentation AgendaAgenda

-- WhatWhat isis MRAM?MRAM?-- History History -- HowHow doesdoes itit workwork??-- MRAM MRAM inin comparisioncomparision to to otherother RAM RAM devicesdevices-- ExistingExisting memorymemory stickssticks

WhatWhat isis MRAM?MRAM?

MRAM = Magnetoresistive Random Access Memory

HistoryHistory

GMR & TMR GMR & TMR EffectsEffects

HowHow doesdoes itit workwork? (2)? (2)Read Current

Pinned Layed

Write Current

Sense Signal

Write or Read Current

Figure 3 shows a variation on the concept that uses spin dependent tunneling for a higher signal output and minimizing demagnetizing effects. A sandwich stripe with neither magnetic film "pinned" can be magnetized with a current through the sandwich into either of two magnetic states depending on the direction of current. With no magnetic field applied, the magnetizaions of the films are antiparallel and lie across the axis of the stripe. A tunnel barrier is deposited on top of the sandwich, and a pinned synthetic antiferromagnet is deposited on top of the barrier. The top layer of the synthetic antiferromagnet is pinned with an antiferromagnet. The synthetic antiferromagnetis comprised of two magnetic layerssandwiching a thin ruthenium layer, a structure which has very strong antiparallel coupling.Fig.3 1D Magnetic Write Sellection Cell

with tunneling Readout

HowHow doesdoes itit workwork? (2)? (2)

Fig.4. Vertical Memory Cell showing bit and word lines

One of the problems encountered in high density MRAM cells has been magnetic anomalies or vortices. A structure which may circumvent this problem is shown in Figure 4. Magnetic films of afew nanometers thickness are separated by thin copper layers, and alternating magnetic layers are of two significantly different thicknesses. When a bit current ispassed through the vertical stack, a circumferential magnetic field is created that can tend to magnetize these magnetic films, with the thinner magnetic layers switchingat lower currents (fields) and the thicker layers switching at higher currents (fields).

MemoryMemory CellCell OperationOperation ((WriteWrite))

Free LayerTunel BarrierFixed Layer

InsulatingTransistorOFF

Easy Axis Field

Hard Axix Field

Ieasy

- Current is passed throught the programming lines generating magnetic fields-The sum of magnetic field from both lines is needed to program the bit- There are no moving parts

MemoryMemory CellCell OperationOperation ((ReadRead))

Insulating Transistor ON

Isense - Current is passed through the bit- Resistance of the bit is sensed

MRAM MRAM inin comparisioncomparision to to otherother RAM RAM devicesdevices

Sample Application – Battery BackedSRAM Replacement

ExistingExisting MemoryMemory SticksSticksMR2A16A by MR2A16A by FreescaleFreescale

>Features>FeaturesCapacityCapacity

-- 4Mbit memory array4Mbit memory arrayConfigurationConfiguration

-- X16 configuration (8/16X16 configuration (8/16--bit access capability)bit access capability)-- 256Kx16bit organization256Kx16bit organization

Power RequirementsPower Requirements-- 3.3V single power supply3.3V single power supply-- Low Voltage InhibitLow Voltage Inhibit-- Prevents writes on power lossPrevents writes on power loss

PackagePackage-- InIn--Package Magnetic ShieldingPackage Magnetic Shielding-- SRAM compatible SRAM compatible pinoutpinout-- RoHSRoHS Compliant 44Compliant 44--Pin TSOP typePin TSOP type--II packageII package-- Moisture sensitivity level MSL3Moisture sensitivity level MSL3-- ThetajaThetaja = 60 degrees C/W= 60 degrees C/W

Temperature RangeTemperature Range-- Commercial Temperature (0Commercial Temperature (0--7070°°C)C)

I/O TTL compatibleI/O TTL compatibleTechnologyTechnology

-- Contains Contains FreescaleFreescale’’ss revolutionary revolutionary ““toggletoggle”” bit cellbit cell

ExistingExisting MemoryMemory SticksSticksHXNV0100 (64x16kb) by by HoneyWellHoneyWell

- Fabricated on S150 Silicon OnInsulator (SOI) CMOSUnderlayer Technology- 150 nm Process (Leff = 130 nm)- Soft Error Rate ≤1x10-10upsets/bit-day-No Latchup- Read Access Time ≤ 67 ns-Write Access Time ≤ 107 ns-Typical Operating Power ≤500 mW- >10 years Power-Off DataRetention- Single-Bit Error Detection &Correction (ECC)-Dual Power Supplies

-1.8 V ± 0.15V, 3.3 V ± 0.3V- 3.3V CMOS Compatible I/O

ReferencesReferences

TechnologicalTechnological issuesissues for highfor high--densitydensity MRAM MRAM developmentdevelopmentwwwwww..freescalefreescale..comcom//mrammram//wwwwww..resourceresource..philipsphilips..comcomwwwwww..honeywellhoneywell..comcomwwwwww..mrammram..infoinfo..comcom

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