1.Tariq Hashmat Tauheed -- Under the Supervision of Prof. M. Hasan -Final Year B.Tech. Electronics Engg. Zakir Husain College of Engineering & Technology

2. Moores Law Faces a Brick Wall. Steep rise in power dissipation per chip. Fundamentally unavoidable thermal noise to severely limit miniaturisation. Heat generated from an average workstation may shoot up to Mega Watts. Leakage currents critical Issue in CMOS. 3. So, MRAM? The Magneto resistive RAM is a promising candidate to challenge CMOS dominated memory world. NON-VOLATILITY HIGH SPEED PERFORMANCE INFINITE ENDURANCE LOW COST 4. The MAGNETIC TUNNEL JUNCTION is the heart of MRAM Minimum MTJ stack constitutes: Two magnetic layers, Thin dielectric barrier, A mechanism to hold the polarization of one of the magnetic layers in a fixed direction Transistor(s) and various electrodes and current carrying lines. 5. The three-layer Synthetic Anti Ferromagnet (SAF) Pinned/Ru/Fixed structure results in a magnetically rigid system and helps control magnetic coupling to the free layer. 6. Resistance of the memory bit either low or high depending on the relative magnetization, [parallel or antiparallel] of the free layer with respect to the fixed layer. Information storage a function of the magnetic orientation of the ferromagnetic layers in the MTJ. Therefore, external agent to switch the magnetic orientation. Multiple ways in which the magnetic switching can be done. 7. The Read Process Transistor in the cell is kept on. Sense Current Isense flown through the MTJ. Resistance encountered by Isense is measured. High resistance Antiparallel Magnetisation of MTJ Digital Value 0.1 Low resistance Parallel Magnetisation of MTJ Digital Value . 8. The Field Writing MRAM FW-MRAM Magnetic induction for storage of data bits. Combination of currents through the Bit Line (IB) and the Digit Line (ID). Magnetic orientation of the free layer in the MTJ is changed according to the induced magnetic field. Transistor kept off during the process. 9. Spin Torque Transferred MRAM STT-MRAM Magnetic switching based on Spin-Polarised Current. Torque' applied by the injected electron spins helps in magnetic switching of the free layer of the MTJ. The phenomenon of Spin Polarised Current induced Magnetic Switching was predicted by Slonczeski and Berger, 1996. 10. Embedded STT-MRAM for Mobile Applications In embedded mobile systems, STT-MRAM finds its use as: NVM Cache ROM Tightly Coupled Memory (TCM). Qualcomm Inc. presented some opportunities for embedded STT-MRAM in mobile applications. 11. The Multi Chip Package (MCP) in conventional embedded systems can be replaced by a single chip, courtesy high density. Significant power savings due to the absence of EBI power for MCP. Simpler architecture cuts down the costs. STT-MRAM Cache memory in an embedded system is about THREE TIMES smaller than its SRAM contemporary, 12. Logic Computing using the Magnetoresistive Element of MRAM Input lines A and B are operated with positive or negative currents I(A) and I(B) of equal magnitude. Third input C with current I(C) needed for rotation of both magnetic layers. Two step procedure: Presetting the MR, followed by the logical operation. 13. The AND Gate Before the logic operation the system is set to the antiparallel configuration by applying ZERO at both inputs A and B. This corresponds to output ZERO. A & B addressed independently with a ZERO or a ONE. Direction of magnetization remains unchanged if ZERO is applied at both inputs A and B. Same applicable for a ZERO and a ONE at the inputs. Magnetization of the upper layer can only be switched by applying a logical ONE at both inputs A & B. 14. 2010: July - Researchers create a new STT-RAM structure, reduces current by a factor of fifty. September - ENP announces a new single-board computer with 512KB of MRAM. 2011: February - BMW use new automotive-temperate Everspin MRAM in the S-1000RR super bike. August - Toshiba to use MRAM as cache for HDD and NAND. 2012: November - Everspin announces the world's first STTMRAM chip, launch in early 2013 December - Toshiba developed the lowest power consumption STT-MRAM, to accelerate R&D. 2013: June - Samsung seeks STT-MRAM research partners, offers funding and collaboration. August - Everspin announces sale of over 10 million MRAM chips, raised $15 million 15. The Everspin STT-MRAM chip 16. Laszlo B. Kish, End of Moores law: thermal (noise) death of integration in micro and nano electronics, Elselvier Physics Letters A 305 (2002) 144149. J. M. Slaughter et al, Fundamentals of MRAM Technology, Journal of Superconductivity: Incorporating Novel Magnetism, Vol. 15, No. 1, February2002. Dr G. Pan, MRAM - present state-of-the-art and future challenges, DSNetUK Workshop, January 2006. Richard William Dorrance, Modeling and Design of STT-MRAMs, MS Dissertation, University of California, 2011. L. Prejbeanu et al, Thermally assisted MRAM, Journal of Physics: Condensed Matter, 2007. A. Ney et al, Programmable computing with a single magnetoresistive element, Letters to Nature, Vol 425, October 2003. Seung H. Kang (Qualcomm Inc.), Embedded STT-MRAM for Mobile Applications: Enabling Advanced Chip Architectures, Non-Volatile Memories Workshop, UCSD, April 2010. Website: http://www.mram-info.com, last accessed 22nd October 2013, 23:33hrs