The Power Management Module (PMM), Unified Clock System (UCS), Port Map (PMAP), and Flashmodules are very flexible peripherals that require initialization within many applications. The MSP430F5xxand MSP430F6xx Core Library provide functions that implement the most common operations using thePMM, UCS, PMAP and Flash modules, such as changing the core voltage to operate at higherfrequencies, crystal/clock initialization, mapping port I/O, and write/erase flash operations. This applicationnote documents the definition and proper use of the available library calls.http://ti.com/mcuMicrocontroller| MCU http://www.ti.com/lsds/ti/microcontroller/home.page?DCMP=TI_MCUS&HQS=Other+OT+mcu8 bit Microcontroller | MCU http://www.ti.com/mcu/docs/mcuproductcontentnp.tsp?sectionId=95&tabId=2858&familyId=193716 bit Microcontroller | MCUhttp://www.ti.com/lsds/ti/microcontroller/16-bit_msp430/overview.page32 bit Microcontroller | MCU http://www.ti.com/lsds/ti/microcontroller/32-bit_c2000/overview.pageARM Microcontroller | MCU http://www.ti.com/lsds/ti/microcontroller/arm_stellaris/overview.page?DCMP=Luminary&HQS=Other+OT+stellaris
Application ReportSLAA448B–August 2010–Revised November 2011
MSP430F5xx and MSP430F6xx Core LibrariesStefan Schauer, Miguel Morales, Priya Thanigai ......................................................................... MSP430
ABSTRACT
The Power Management Module (PMM), Unified Clock System (UCS), Port Map (PMAP), and Flashmodules are very flexible peripherals that require initialization within many applications. The MSP430F5xxand MSP430F6xx Core Library provide functions that implement the most common operations using thePMM, UCS, PMAP and Flash modules, such as changing the core voltage to operate at higherfrequencies, crystal/clock initialization, mapping port I/O, and write/erase flash operations. This applicationnote documents the definition and proper use of the available library calls.
Project collateral and source code discussed in this application report can be downloaded fromhttp://www.ti.com/lit/zip/slaa448.
1.1 Importance of the Power Management Module (PMM)
The PMM manages the following internal circuitry:
• An integrated low-dropout voltage regulator (LDO) that produces a secondary core voltage (VCORE) fromthe primary voltage that is applied to the device (DVCC)
• Supply voltage supervisors (SVS) and supply voltage monitors (SVM) for the primary voltage (DVCC)and the secondary voltage (VCORE). The SVS and SVM include programmable threshold levels andpower-fail indicators.
Therefore, the PMM plays a crucial role in defining the maximum performance, valid voltage conditions,and current consumption for an application running on an MSP430x5xx or MSP430x6xx device.
The secondary voltage that is generated by the integrated LDO, VCORE, is programmable to one of fourcore voltage levels, shown as 0, 1, 2, and 3 in Figure 1. Each increase in VCORE allows the CPU to operateat a higher maximum frequency, fMAX, shown as f0, f1,f2, or f3 in Figure 1. The values of these frequenciesare specified in the device-specific data sheet. This feature allows the user the flexibility to trade powerconsumption in active and low-power modes for different degrees of maximum performance and minimumsupply voltage.
Figure 1. System Frequency vs Supply Voltage
Both the primary and secondary voltages, DVCC and VCORE, are protected by built-in SVM and SVScircuitry. Each SVM and SVS circuit is programmable to four voltage levels that map to the VCORE andminimum DVCC levels that are required for robust run-time behavior. The intended interaction betweenmonitor and supervisor is as follows: the monitor has a threshold voltage slightly higher than thesupervisor and triggers an interrupt in a decreasing voltage condition, so that the application can store anycritical run-time parameters. If the voltage continues to fall and reaches the supervisor threshold, the PMMresets the device. For a detailed description of the SVS and SVM behavior and the status and error flagsthat are referenced in this application report, see the MSP430x5xx/MSP430x6xx Family User’s Guide(SLAU208). [1]
NOTE: To align with the nomenclature in the MSP430x5xx/MSP430x6xx Family User’s Guide(SLAU208) [1], the primary voltage domain (DVCC) is referred to as the high-side voltage(SVSH/SVMH) and the secondary voltage domain (VCORE) is referred to as the low-side voltage(SVSL/SVML).
2 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
Moving between the different VCORE voltages requires a specific sequence of events and can be done onlyone level at a time; for example, to change from level 0 to level 3, the application code must step throughlevel 1 and level 2. Figure 2 shows the sequence of events required to modify VCORE.
Figure 2. Changing VCORE and SVML / SVSL Levels
VCORE increase:
1. SVML monitor level is incremented.2. VCORE level is incremented.3. The SVML Level Reached Interrupt Flag (SVSMLVLRIFG) in the PMMIFG register is polled. When
asserted, SVSMLVLRIFG indicates that the VCORE voltage has reached its next level.4. SVSL is increased. SVSL is changed last, because if SVSL were incremented prior to VCORE, it would
potentially cause a reset.
VCORE decrease:
5. Decrement SVML and SVSL levels.6. Decrement VCORE.
The SetVCore() function appropriately handles an increase or decrease of the core voltage.
NOTE: The procedure recommended above provides a workaround for the erratum FLASH37. Seethe device-specific erratasheet to determine if a device is affected by FLASH37. Theworkaround is also highlighted in the source code for the PMM library (HAL_PMM.c).
1.2 Recommended SVS and SVM Settings
The SVS and SVM on both the high side and the low side are enabled in normal performance modefollowing a brown-out reset condition. The device is held in reset until the SVS and SVM verify that theexternal and core voltages meet the minimum requirements of the default core voltage, which is levelzero. The SVS and SVM remain enabled unless disabled by the firmware.
The low-side SVS and SVM are useful for verifying the startup conditions and for verifying anymodification to the core voltage. However, in their default mode, they prevent the CPU from executingcode on wake-up from low-power modes 2, 3, and 4 for a full 150 µs, not 5 µs. This is because, in theirdefault states, the SVSL and SVML are powered down in the low-power mode of the PMM and need timefor their comparators to wake and stabilize before they can verify the voltage condition and release theCPU for execution. Note that the high-side SVS and SVM do not influence the wake time from low-powermodes.
3SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
If the wake-up from low-power modes needs to be shortened to 5 µs, the SVSL and SVML should bedisabled after the initialization of the core voltage at the beginning of the application. Disabling SVSL andSVML prevents them from gating the CPU on wake-up from LPM2, LPM3, and LPM4. The application isstill protected on the high side with SVSH and SVMH. The SetVCore() function automatically enables anddisables the SVS and SVM as necessary if a non-zero core voltage level is required. If the applicationdoes not require a change in the core voltage (that is, when the target MCLK is less than 8 MHz), theDISABLE_SVSL_SVML() and ENABLE_SVSH_RESET() macros can be used to disable the low-side SVSand SVM circuitry and enable only the high-side SVS POR reset, respectively.
1.3 Setting SVS/SVM Threshold Levels
The voltage thresholds for the SVS and SVM modules are programmable. On the high side, there are twobit fields that control these threshold levels – the SVSHRVL and SVSMHRRL. The SVSHRVL field definesthe voltage threshold at which the SVSH triggers a reset (also known as the SVSH ON voltage level). TheSVSMHRRL field defines the voltage threshold at which the SVSH releases the device from a reset (alsoknown as SVSH OFF voltage level). The MSP430x5xx/MSP430x6xx Family User’s Guide (SLAU208) [1]recommends the settings shown in Table 1 when setting these bits. The SetVCore() function defined inthe file HAL_PMM.c follows these recommendations and ensures that the SVS levels match the corevoltage levels that are used.
Table 1. Recommended SVSH Settings
Maximum fsys DVCC(MHz) (V) SVSHRVL[1:0] SVSMHRRL[2:0] PMMCOREV[1:0]
8 >1.8 00 000 00
12 >2.0 01 001 01
20 >2.2 10 101 10
25 >2.4 11 011 11
It is possible to set SVSMHRRL = 4, 5, 6, and 7 when the device is operating with SVSHRVL = 3 andPMMVCOREV = 3.
1.4 Advanced SVS Controls and Trade-Offs
In addition to the default SVS settings that are provided with the SetVCore() function, the SVS/SVMmodules can be optimized for wake-up speed, response time (propagation delay), and currentconsumption, as needed. The controls for this are provided in the macro definitions in Table 2.
The following controls can be optimized for the SVS/SVM modules:
• Protection in low power modes - LPM2, LPM3, and LPM4
• Wake-up time from LPM2, LPM3, and LPM4
• Response time to react to an SVS event
Selecting the LPM option, wake-up time, and response time that is best suited for the application is left tothe user.
A few typical examples illustrate the trade-offs:
Case A: The most robust protection that stays on in LPMs and has the fastest response and wake-up timeconsumes the most power.
Case B: With SVS high side active only in AM, no protection in LPMs, slow wake-up, and slow responsetime has SVS protection with the least current consumption.
Case C: An optimized case may be the one described in Section 1.2: turn off the low-side monitor andsupervisor, thereby saving power while keeping response time fast on the high side to help with timingcritical applications.
The user can call the SetVCore() function, which configures SVS/SVM high side and low side with therecommended or default configurations, or can call the macros provided to control the parameters as theapplication demands.
4 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
Any writes to the SVSMLCTL and SVSMHCTL registers require a delay time for these registers to settlebefore the new settings take effect. This delay time is dependent on whether the SVS and SVM modulesare configured for normal or full performance. See device-specific data sheet for exact delay times.
1.5 Using HAL_PMM.h and HAL_PMM.c
Table 2 shows the symbol definitions used in HAL_PMM.
Table 2. HAL_PMM Symbol Definitions
Symbol Definitions Description
_HAL_PMM_DISABLE_SVML_ Disables the low-side SVM when SetVCore is called
_HAL_PMM_DISABLE_SVSL_ Disables the low-side SVS when SetVCore is called
_HAL_PMM_DISABLE_FULL_PERFORMANCE_ Disables the low-side full-performance mode when SetVCore is called
Table 3. HAL_PMM Macro Definitions
Macro Name Description (1)
ENABLE_SVSL() / DISABLE_SVSL() Enables or disables the low-side SVS circuitry
ENABLE_SVML() / DISABLE_SVML() Enables or disables the low-side SVM circuitry
ENABLE_SVSH() / DISABLE_SVSH() Enables or disables the high-side SVS circuitry
ENABLE_SVMH() / DISABLE_SVMH() Enables or disables the high-side SVM circuitry
ENABLE_SVSL_SVML() / DISABLE_SVSL_SVML() Enables or disables the low-side SVS and SVM circuitry
ENABLE_SVSH_SVMH() / DISABLE_SVSH_SVMH() Enables or disables the high-side SVS and SVM circuitry
ENABLE_SVSL_RESET() / Enables or disables the POR signal generation when a low-voltage event isDISABLE_SVSL_RESET() registered by the low-side SVS
ENABLE_SVML_INTERRUPT() / Enables or disables the interrupt generation when a low-voltage event isDISABLE_SVML_INTERRUPT() registered by the low-side SVM
ENABLE_SVSH_RESET() / Enables or disables the POR signal generation when a low-voltage event isDISABLE_SVSH_RESET() registered by the high-side SVS
ENABLE_SVMH_INTERRUPT() / Enables or disables the interrupt generation when a low-voltage event isDISABLE_SVMH_INTERRUPT() registered by the high-side SVM
CLEAR_PMM_IFGS() Clear all interrupt flags for the PMM
SVSL_ENABLED_IN_LPM_FAST_WAKE() Enables supervisor low side in LPM with twake-up-fast(1) from LPM2, LPM3, and
LPM4
SVSL_ENABLED_IN_LPM_SLOW_WAKE() Enables supervisor low side in LPM with twake-up-slow(1) from LPM2, LPM3,
and LPM4
SVSL_DISABLED_IN_LPM_FAST_WAKE() Disables supervisor low side in LPM with twake-up-fast(1) from LPM2, LPM3,
and LPM4
SVSL_DISABLED_IN_LPM_SLOW_WAKE() Disables supervisor low side in LPM with twake-up-slow(1) from LPM2, LPM3,
and LPM4
SVSH_ENABLED_IN_LPM_NORM_PERF() Enables supervisor high side in LPM with tpd = 20 µs (1)
SVSH_ENABLED_IN_LPM_FULL_PERF() Enables supervisor high side in LPM with tpd = 2.5 µs (1)
SVSH_DISABLED_IN_LPM_NORM_PERF() Disables supervisor high side in LPM with tpd = 20 µs (1)
SVSH_DISABLED_IN_LPM_FULL_PERF() Disables supervisor high side in LPM with tpd = 2.5 µs (1)
SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() Optimized to provide twake-up-fast(1) from LPM2, LPM3, and LPM4 with least
power
SVSH_OPTIMIZED_IN_LPM_FULL_PERF() Optimized to provide tpd = 2.5 µs (1) in LPM with least power(1) See device-specific data sheet for accurate values of tpd and twake-up.
5SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
DescriptionSets the appropriate VCORE level. Calls the static SetVCoreUp() or SetVCoreDown() function therequired number of times depending on the current VCORE level, because the levels must be steppedthrough individually.
Parameterslevel
The target VCORE level
ReturnsA status indicator equal to zero (PMM_STATUS_OK) or one (PMM_STATUS_ERROR) that indicates avalid or invalid VCORE transition, respectively. An invalid VCORE transition exists if DVCC is less than theminimum required voltage for the target VCORE voltage.
6 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
The Unified Clock System (UCS) of the MSP430x5xx and MSP430x6xx devices is a natural evolution ofthe ultra-low power clock system from previous device families. The UCS is based on five available clocksources (VLO, REFO, XT1, XT2, and DCO) providing signals to three system clocks (MCLK, SMCLK,ACLK). Different low power modes are achieved by turning off the MCLK, SMCLK, ACLK, and integratedLDO. A short description of the clock sources and the systems clock are shown in Table 4 and Table 5.For a more detailed description, see the MSP430x5xx/MSP430x6xx Family User’s Guide (SLAU208).
REFO Reference oscillator. 32 kHz (±1%, ±3% over full temp range)
Ultralow-power oscillator, compatible with low-frequency 32768-Hz watch crystals and with standardXT1 (LFXT1, HFXT1) crystals, resonators, or external clock sources in the 4-MHz to 32-MHz range, including digital inputs.
Most commonly used as 32-kHz watch crystal oscillator.
Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clockXT2 sources in the 4-MHz to 32-MHz range, including digital inputs.
Internal digitally controlled oscillator (DCO) that can be stabilized by a frequency lock loop (FLL) thatDCO sets the DCO to a specified multiple of a reference frequency.
Table 5. System Clocks and Functionality on the MSP430
System Clock Description Low-Power Modes
MCLK Services the CPU. Commonly sourced by DCO. Active mode onlyMaster Clock
SMCLK Active mode,Services 'fast' system peripherals. Commonly sourced by DCO.Subsystem Master Clock LPM0 and LPM1
ACLK Active mode,Services 'slow' system peripherals. Commonly used for 32-kHz signal.Auxiliary Clock LPM0 to LPM3
System clocks of the MSP430x5xx generation are automatically enabled, regardless of the LPM mode ofoperation, if they are required for the proper operation of the peripheral module that they source. Thisadditional flexibility of the UCS, along with improved fail-safe logic, provides a robust clocking scheme forall applications.
2.1.1 Fail-Safe Logic
The UCS fail-safe logic plays an important part in providing a robust clocking scheme for MSP430x5xxand MSP430x6xx applications. This feature hinges on the ability to detect an oscillator fault for the XT1 inboth low-frequency and high-frequency modes (XT1LFOFFG and XT1HFOFFG respectively), thehigh-frequency XT2 (XT2OFFG), and the DCO (DCOFFG). These flags are set and latched when therespective oscillator is enabled but not operating properly; therefore, they must be explicitly cleared insoftware. First call all clock initialization, then call Clear_All_Osc_Flags(), and finally enable interrupts.Figure 3 shows the oscillator fault logic.
7SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
The oscillator fault flags on previous MSP430 generations are not latched and are asserted only as longas the failing condition exists. Therefore, an important difference between the families is that the fail-safebehavior in a 5xx-based MSP430 remains active until both the OFIFG and the respective fault flag arecleared in software.
This fail-safe behavior is implemented at the oscillator level, at the system clock level and, consequently,at the module level. Some notable highlights of this behavior are described below. For the full descriptionof fail-safe behavior and conditions, see the MSP430x5xx/MSP430x6xx Family User’s Guide (SLAU208).
• Low-frequency crystal oscillator 1 (LFXT1)
The low-frequency (32768 Hz) crystal oscillator is the default reference clock to the FLL. An assertedXT1LFOFFG switches the FLL reference from the failing LFXT1 to the internal 32-kHz REFO. This caninfluence the DCO accuracy, because the FLL crystal ppm specification is typically tighter than theREFO accuracy over temperature and voltage of ±3%.
• System Clocks (ACLK, SMCLK, MCLK)
A fault on the oscillator that is sourcing a system clock switches the source from the failing oscillator tothe DCO oscillator (DCOCLKDIV). This is true for all clock sources except the LFXT1. As previouslydescribed, a fault on the LFXT1 switches the source to the REFO. Because ACLK is the active clock inLPM3, there is a notable difference in the LPM3 current consumption when the REFO is the clocksource (~3 µA active) versus the LFXT1 (~300 nA active).
• Modules (WDT_A)
In watchdog mode, when SMCLK or ACLK fails, the clock source defaults to the VLOCLK.
The HAL_UCS.h and HAL_UCS.c library functions show how to properly initialize the XT1 inlow-frequency and high-frequency modes, the XT2, and the FLL.
8 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
Selects the source for the reference into the FLLSELECT_FLLREF(source) Example: SELECT_FLLREF(SELREF__XT1CLK)
Selects the source for ACLKSELECT_ACLK(source) Example: SELECT_ACLK(SELA__XT1CLK)
Selects the source for MCLKSELECT_MCLK(source) Example: SELECT_MCLK(SELM__XT2CLK)
Selects the source for SMCLKSELECT_SMCLK(source) Example: SELECT_SMCLK(SELS__XT2CLK)
Selects the source for MCLK and SMCLKSELECT_MCLK_SMCLK(source) Example: SELECT_MCLK_SMCLK(SELM__DCOCLK | SELS__DCOCLK)
ACLK_DIV(x) Sets ACLK frequency = ACLK/x; x = {1, 2, 4, 8, 12, 16}
MCLK_DIV(x) Sets MCLK frequency = MCLK/x; x = {1, 2, 4, 8, 12, 16}
SMCLK_DIV(x) Sets SMCLK frequency = SMCLK/x; x = {1, 2, 4, 8, 12, 16}
SELECT_FLLREFDIV(source) Sets the FLL reference frequency = FLLREF/x; x = {1, 2, 4, 8, 12, 16}(1) All macros mask the required bit changes in the UCS registers so that other clock settings are not affected.
2.2.1 void LFXT_Start(uint16_t xtdrive)
Description
Initializes the XT1 crystal oscillator to operate in low-frequency mode. This mode supports 32768-Hzcrystals. Loops until all oscillator fault flags are cleared, with no timeout, and sets the drive strength to auser-defined level. The maximum drive strength is used to initiate the crystal startup, but then the userlevel is programmed to the UCS registers.
Parameters
xtdrive The target drive strength after the oscillator has been successfully initialized. The lowestdrive strength is the recommended setting to provide low-power operation and reliablecrystal operation. The highest drive strength is recommended when the applicationenvironment causes a high degree of risk to the crystal oscillation.
Returns
None
9SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
Initializes the XT1 crystal oscillator to operate in low-frequency mode. This mode supports 32768-Hzcrystals. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented andequals to zero. Sets the drive strength to a user-defined level. The maximum drive strength is used toinitiate the crystal startup, and then the user level is programmed to the UCS registers.
Parameters
xtdrive The target drive strength after the oscillator has been successfully initialized. The lowestdrive strength is the recommended setting to provide low-power operation and reliablecrystal operation. The highest drive strength is recommended when the applicationenvironment causes a high degree of risk to the crystal oscillation.
timeout A count variable that is decremented every time the loop that clears the oscillator faultflags is executed. When timeout reaches 0, the loop that checks and clears the oscillatorfault flags is exited.
Returns
A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). AUCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.
2.2.3 void XT1_Start(uint16_t xtdrive)
Description
Initializes the XT1 crystal oscillator to operate in high-frequency mode. This mode supports crystalfrequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until alloscillator fault flags are cleared, with no timeout. See the device-specific data sheet for appropriate drivesettings.
Parameters
xtdrive The target drive strength for the XT1 crystal oscillator.
Returns
None
10 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
Initializes the XT1 crystal oscillator to operate in high-frequency mode. This mode supports crystalfrequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until alloscillator fault flags are cleared or until a timeout counter is decremented and equals zero. See thedevice-specific data sheet for appropriate drive settings.
Parameters
xtdrive The target drive strength for the XT1 crystal oscillator.timeout A count variable that is decremented every time the loop that clears the oscillator fault
flags is executed. When timeout reaches 0, the loop that checks and clears the oscillatorfault flags is exited.
Returns
A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). AUCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.
2.2.5 void XT1_Bypass(void)
Description
Initializes the XT1 oscillator to accept an external logic-level input square wave between 4 MHz and32 MHz in frequency. Loops until all oscillator fault flags are cleared, with no timeout. See thedevice-specific data sheet (general purpose I/O) for appropriate logic levels.
Parameters
None
Returns
None
11SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
Initializes the XT2 crystal oscillator, which supports crystal frequencies between 4 MHz and 32 MHz,depending on the selected drive strength. Loops until all oscillator fault flags are cleared, with no timeout.See the device-specific data sheet for appropriate drive settings.
Parameters
xtdrive The target drive strength for the XT1 crystal oscillator.
Returns
None
NOTE: When calling XT2_Start() or XT2_Start_Timeout() on a device that does not defineXT2DRIVE_x bits, pass zero as the xtdrive parameter.
Initializes the XT2 crystal oscillator, which supports crystal frequencies between 4 MHz and 32 MHz,depending on the selected drive strength. Loops until all oscillator fault flags are cleared or until atimeout counter is decremented and equals zero. See the device-specific data sheet for appropriate drivesettings.
Parameters
xtdrive The target drive strength for the XT2 crystal oscillator.timeout A count variable that is decremented every time the loop that clears the oscillator fault
flags is executed. When timeout reaches 0, the loop that checks and clears the oscillatorfault flags is exited.
Returns
A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). AUCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.
12 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
Initializes the XT2 oscillator to accept an external logic-level input square wave between 4 MHz and32 MHz in frequency. Loops until all oscillator fault flags are cleared, with no timeout. See thedevice-specific data sheet (general purpose I/O) for appropriate logic levels.
Parameters
None
Returns
None
2.2.9 void Init_FLL_Settle(uint16_t int fsystem, uint16_t ratio)
Description
Initializes the DCO to operate a frequency that is a multiple of the reference frequency into the FLL.Loops until all oscillator fault flags are cleared, with no timeout. If the frequency is greater than 16 MHz,the function sets the MCLK and SMCLK source to the undivided DCO frequency. Otherwise, the functionsets the MCLK and SMCLK source to the DCOCLKDIV frequency.Note that the default FLL reference frequency is LFXT1. Therefore, call the LFXT_Start orLFXT_Start_Timeout function before calling Init_FLL to properly initialize and clear the oscillator faultflags of LFXT1. Otherwise, the fail-safe behavior of LFXT1 switches the FLL reference to the internalREFO, which operates at slightly higher current and is slightly less accurate than an external 32-kHzcrystal.The FLL reference divider is assumed to be one. For dividers greater than one, the ratio parameter mustaccount for the divider in the factor y (FLL reference frequency).This function executes a software delay that is proportional in length to the ratio of the target FLLfrequency and the FLL reference. This allows the FLL an appropriate settling time before any other codeis executed.
Parameters
fsystem The target frequency for MCLK in kHzratio The ratio x/y, where x = fsystem and y = FLL reference frequency.
Returns
None
13SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
Clears and checks all oscillator fault flags. It uses a timeout feature and returns the appropriate oscillatorfault flag errors. This function should be called after initializing all system clocks. For example:
SELECT_ACLK(SELA__XT1CLK); // Select XT1 as ACLK sourceSELECT_SMCLK(SELS__XT2CLK); // Select XT2 as SMCLK source
// Clear all and global oscillator fault flagsClear_All_Osc_Flags(1000);
See the example API function call in MSP430xxxx_UCS_07.c.
Parameters
timeout A count variable that is decremented every time the loop that clears the oscillator faultflags is executed. When timeout reaches 0, the loop that checks and clears the oscillatorfault flags is exited.
Returns
Fault Oscillator fault flags. Software must parse the return value to determine the specific faultflag.
15SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
The Port Map feature of the MSP430x5xx and MSP430x6xx devices brings simplicity back to digitalhardware design. Port mapping allows the user to define the port pin on which certain peripheral signalsare available, as specified in the device data sheet. The relationship between the available port mapsignals to the port pins can be one-to-one, one-to-many, or even many-to-one, because the port mappingis reconfigurable in application. When the port pin is configured to peripheral mode, it reflects theperipheral signal that is programmed into its respective PxMAPy register. For a full description of the PortMapping module, see the MSP430x5xx/MSP430x6xx Family User’s Guide (SLAU208).
The following code snippet shows proper use of the configure_ports function. This is also shown in thecode example that comes with this application report.
/* port_mapping array - shows proper usage of the PM_ symbols to define P1-P3 */const unsigned char port_mapping[] ={// Port P1:PM_TA0CCR0A, PM_TA0CCR1A, PM_TA0CCR2A, PM_TA0CCR3A,PM_TA0CCR4A, PM_TA1CCR0A, PM_TA1CCR1A, PM_TA1CCR2A,
// Port P2:PM_UCA0RXD, PM_UCA0TXD, PM_NONE, PM_NONE,PM_UCB0SOMI, PM_UCA0SIMO, PM_UCB0CLK, PM_UCB0STE,
// Port P3:PM_NONE, PM_NONE, PM_NONE, PM_NONE,PM_NONE, PM_NONE, PM_NONE, PM_NONE,
port_mapping Pointer to initialization arrayPxMAPy Pointer to the first PortMap register to initializenum_of_ports Number of ports to be initializedport_map_reconfig Flag to enable/disable reconfiguration
Returns
None
16 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
The TLV structure is a table stored in flash memory that contains device-specific information. This table isread-only and is write-protected. It contains important information for using and calibrating the device. Alist of the contents of the TLV is available in the device-specific data sheet (in the Device Descriptorssection), and an explanation on its functionality is available in the MSP430x5xx/MSP430x6xx FamilyUser’s Guide (SLAU208).
The TLV structure uses a tag or base address to identify segments of the table where information isstored. Some examples of TLV tags are Peripheral Descriptor, Interrupts, Info Block and Die Record.This function retrieves the value of a tag and the length of the tag.
Parameters
tag This value represents the tag for which the information needs to be retrieved. Varioustags such as ADC (TLV_ADCCAL), Peripheral Descriptor (TLV_PDTAG) are defined inthe header file HAL_TLV.h.
instance In some cases a specific tag may have more than one instance. For example theremay be multiple instances of timer calibration data present under a single Timer Caltag. This variable specifies the instance for which information is to be retrieved (0, 1,etc.). When only one instance exists; 0 is passed.
*length This variable acts as a return through indirect reference. The function retrieves thevalue of the TLV tag length. This value is pointed to by *length and can be used by theapplication level once the function is called. If the specified tag is not found then thepointer is null 0.
**data_address This variable acts as a return through indirect reference. Once the function is calleddata_address points to the pointer that holds the values retrieved from the specifiedTLV tag. If the specified tag is not found then the pointer is null 0.
Returns
See description of parameters.
5.1.2 uint16_t Get_Device_Type(void)
Description
Retrieves the unique device ID from the TLV structure.
Parameters
None
Returns
The device ID is returned as type unsigned int.
19SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
The Peripheral Descriptor tag is split into two portions – a list of the available flash memory blocksfollowed by a list of available peripherals. This function is used to parse through the first portion andcalculate the total flash memory available in a device. The typical usage is to call the Get_TLV_Memorywhich returns a non-zero value until the entire memory list has been parsed. When a zero is returned, itindicates that all the memory blocks have been counted and the next address holds the beginning of thedevice peripheral list.
Parameters
instance In some cases a specific tag may have more than one instance. This variable specifiesthe instance for which information is to be retrieved (0, 1 etc). When only one instanceexists; 0 is passed.
Returns
The returned value is zero if the end of the memory list is reached.
The Peripheral Descriptor tag is split into two portions – a list of the available flash memory blocksfollowed by a list of available peripherals. This function is used to parse through the second portion andcan be used to check if a specific peripheral is present in a device.The function calls Get_TLV_Memory() recursively until the end of the memory list and consequently thebeginning of the peripheral list is reached.
Parameters
tag This value represents the tag for a specific peripheral for which the information needs tobe retrieved. In the header file HAL_TLV.h specific peripheral tags are pre-defined, forexample USCIA_B and TA0 are defined as TLV_PID_USCI_AB and TLV_PID_TA2respectively
instance In some cases a specific tag may have more than one instance. For example a devicemay have more than a single USCI module, each of which is defined by an instancenumber 0, 1, 2, etc. When only one instance exists; 0 is passed.
Returns
The returned value is zero if the specified tag value (peripheral) is not available in the device.
20 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
This function is used to retrieve information on available interrupt vectors. It allows the user to check if aspecific interrupt vector is defined in a given device.
Parameters
tag This value represents the tag for the interrupt vector. Interrupt vector tags number from 0to N depending on the number of available interrupts. Refer to the device datasheet for alist of available interrupts.
Returns
The returned value is zero is the specified interrupt vector is not defined.
21SLAA448B–August 2010–Revised November 2011 MSP430F5xx and MSP430F6xx Core LibrariesSubmit Documentation Feedback
See the accompanying zip file for the software that is associated with this library. The zip file can bedownloaded from http://www.ti.com/lit/zip/slaa448. The file structure and a brief description of the includedfiles are provided in the Readme.txt file present in the zip folder, and they are also described here.
The associated software is divided into two sections:
(A) F5xx_F6xx_Core_Lib: This folder contains all of the library’s source code files. These include theHAL_xxx.c and HAL_xxx.h files for each peripheral — PMM, UCS, PMAP, and flash.
(B) Application Examples: The application examples call functions from the Core library and show theiruse based on functionality. The examples are divided based on the device. See the file Index.txt for alist of code examples for each device.
6.1 Creating Projects and Workspaces
This section provides information on how to get the code examples working out-of-the-box. Theinstructions apply to Code Composer Studio V4.0 or later and IAR Embedded Workbench V5.10 or later.
6.1.1 Using the Library in IAR1. Create a project in IAR and select the required device specialization under Project → Options.
2. The project is created in the same directory level as the folders F5xx_F6xx_Core_Lib and FxxxxApplication Examples.
3. Right click on Project name → Add → Group and create a group F5xx_F6xx_Core_Lib.
4. Right click on CoreLib and add all files in folder F5xx_6xx_Core_Lib to the group.
5. Add the required example file from the folder Fxxxx Application Examples.
6. Add the include directory path so the Project can find the location of the header file.
This is done by Project → Options → C/C++ Compiler → Preprocessor Tab.Insert the line: $PROJ_DIR$\F5xx_F6xx_Core_Lib\ in the blank space provided.
Now the project is ready to compile.
6.1.2 Using the Library in CCS1. Open CCS and select a Workspace or create a new Workspace.
2. Create a new CCS Project (click File → New → CCS Project). Name the project, choose theappropriate Project Type (MSP430), and choose the device variant that corresponds to the device inuse.
3. Right click on Project Name → New → Folder.Select the Project Name as the parent folder and name the new folder CoreLib.
4. Add all the files in the folder F5xx_6xx_Core_Lib to the Project:Right click on Project Name → Add Files → (select files).Move the files to the CoreLib folder: Select files and right click → Move → select 'CoreLib' folder.
5. Add required example file from the folder MSP430xxxx Application Examples:Right click on Project Name → Add Files.
6. Double check that the predefined symbol under Project → Properties → C/C++ Build → PredefinedSymbols corresponds to the device in use such as "__MSP430F5438A__" in case of anMSP430F5438A.
7. Change the Include directory path so the Project can find the location of the F5xx_F6xx_Core_Libfolder.
Click Project → Properties → C/C++ Build → Include Options.Select the icon with the green plus sign and specify the path to the CoreLib folder.
Now the project is ready to compile.
22 MSP430F5xx and MSP430F6xx Core Libraries SLAA448B–August 2010–Revised November 2011Submit Documentation Feedback
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
