MSP432E401Y GPIO

Note: The information here is a subset of GPIO port information and thus you will need to refer to thetechnical reference manual for some particulars.

Block diagram of a GPIO port that is digital only:

The details of GPIO operation and the associated registers is found in the TI MSP432E4 TechnicalReference Manual starting on page 1192.

Credits: Information compiled here and figures shown here are from the TI MSP432E4 SimpleLinkMicrocontrollers Technical Reference Manual slau723

Block diagram of an I/O pad with both digital and analog capability:

(page 1195)

Base memory addresses for the GPIO ports:

(page 1201)

Each port has up to 8 pins associated with it. Some ports have less than 8 pins. Note that each port isallocated a 1024 word address space (32 bit addresses, i.e. 4 bytes per address) although not all addressesare used.

34 registers are used to configure, control, and handle data for each port. One of these 34 registers is thedata register from which the current data on a port can be read or to which data can be written.

For each port, the following registers and relative addresses (offset) are defined:

NOTE: The x in GPIOx is a place holder for the desired port such as GPIOA for port A etc.

Minimum sequence for configuring a GPIO pin for digital output (pages 1199-1200)

1) Enable the clock for the specific port by setting a bit in the RCGCGPIO register (SYSCTL->RCGCGPIO) that is part of the System Control block.Example: SYSCTL->RCGCGPIO |= SYSCTL_RCGCGPIO_R12

(see line 12450 in msp432e401.h header file for the RCGCGPIO bit field definitions)

2) Set the direction of the GPIO port pin using the GPIODIR register (GPIOx->DIR).

3) Configure the GPIOAFSEL register (GPIOx->AFSEL) to program the pin as a GPIO or alternatepin.

4) Configure the pin for digital I/O using the GPIODEN register (GPIOx->DEN)

5) If needed, set the drive level and slew rate of the pin (see table 17-1 for choices)a) Set the EDMn field in the GPIOPC registerb) Set or clear the GPIODR4R register bitsc) Set or clear the GPIODR8R register bitsd) Set or clear the GPIODR12R register bitse) Slew rate can be programmed using the GPIOSLR register if needed.

6) If open drain output is needed set a bit in the GPIOODR register (GPIOx->ODR)

Minimum sequence for configuring a GPIO pin for digital input

1) Enable the clock for the specific port by setting a bit in the RCGCGPIO register (SYSCTL->RCGCGPIO) that is part of the System Control block.

2) Set the direction of the GPIO port pin using the GPIODIR register (GPIOx->DIR).

3) Configure the GPIOAFSEL register (GPIOx->AFSEL) to program the pin as a GPIO or alternatepin.

4) If needed, configure the pin to have a pull-up or pull-down resistor connected to it.a) For pull-up, configure GPIOPUR register (GPIOx->PUR)b) For pull-down, configure GPIOPDR register (GPIOx->PDR)

5) Configure the pin for digital I/O using the GPIODEN register (GPIOx->DEN)

6) If an interrupt is desired when an input changes state then configure registers GPIOIS, GPIOEBE,GPIOEV, and GPIOIM. (see page 1200 and associated pages in the technical reference manual)

Note: See line 199 in msp432e401.h header file for bit field definitions such as BIT0, BIT1, etc.

Registers of principle interest when configuring a pin on a particular port for digital I/O

GPIODIR Direction 0 = input 1 = output(GPIOx->DIR)

GPIOIM Interrupt mask 0 = interrupt disabled 1= interrupt enabled(GPIOx->IM)

(This section only started. You will need to refer to the tech ref manual for now)

(See page 1196 for a complete description of data register operation)