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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
LOGIC GATES
AIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. Give the Timing simulation for critical path time calculation & also synthesis for Digital Circuit.
d. Implement the place & route technique for major FPGA vendor i.e., XILINX
e. Implement the designed digital circuit using FPGA &CPLD devices.
APPARATUS:
1. Computer system
2. Xilinx 7.0 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
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Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
VHDL PROGRAM:
ANDGATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;
Architecture and_gate_beh of and_gate is
Begin
process(a, b)
begin
if a = '1' and b = '1' then c <= '1';
else c <= '0';
end if;
end process;
end and_gate_beh;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
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Dataflow Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;
Architecture and_gate_df of and_gate is
Begin
c <= a and b;
end and_gate_df;
Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Architecture and_str of and_gate is
component and_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : and_gate port map (a,b,c);
end and_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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LOGIC SYMBOL AND TRUTH TABLE:
AND GATE TRUTH TABLE
7
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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SIMULATION RESULTS:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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OR GATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;
Architecture or_gate_beh of or_gate is
Begin
process(a, b)
begin
if a = '0' and b = '0' then c <= '0';
else c <= '1';
end if;
end process;
end or_gate_beh;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Dataflow Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;
Architecture or_gate_df of or_gate is
Begin
c <= a or b;
end or_gate_df;
Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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end or_gate;
Architecture or_str of or_gate is
component or_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : or_gate port map(a,b,c);
end or_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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_____________________________________________________________________________________
LOGIC SYMBOL AND TRUTH TABLE:
OR GATE TRUTH TABLE
12
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
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SIMULATION RESULTS:
ORGATE:-
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NOT GATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity not_gate is
Port ( a : in STD_LOGIC;
c : out STD_LOGIC);
end not_gate;
Architecture not_gate_beh of not_gate is
Begin
Process (a)
begin
if a = '0' then
c <= '1';
else
c <= '0';
end if;
end process;
end not_gate_beh;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Dataflow Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity not_gate is
Port ( a : in STD_LOGIC;
c : out STD_LOGIC);
end not_gate;
Architecture not_gate_df of not_gate is
Begin
c <= not a;
end not_gate_df;
Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity not_gate is
Port ( a : in STD_LOGIC;
c : out STD_LOGIC);
end not_gate;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Architecture not_str of not_gate is
component not_gate
Port ( a : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : not_gate port map(a,c);
end not_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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LOGIC SYMBOL AND TRUTH TABLE:
NOT GATE TRUTH TABLE
17
A Y
0 1
1 0
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
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SIMULATION RESULTS:
NOT GATE:-
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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NAND GATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity nand_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand_gate;
Architecture nand_gate_beh of nand_gate is
Begin
process(a, b)
begin
if a = '1' and b = '1' then c <= '0';
else c <= '1';
end if;
end process;
end nand_gate_beh;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Dataflow Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity nand_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand_gate;
Architecture nand_gate_df of nand_gate is
Begin
c <= a nand b;
end nand_gate_df;
Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity nand_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
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c : out STD_LOGIC);
end nand_gate;
Architecture nand_str of nand_gate is
component nand_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : nand_gate port map(a,b,c);
end nand_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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LOGIC SYMBOL AND TRUTH TABLE:
NAND GATE TRUTH TABLE
22
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SIMULATION RESULTS:
NANDGATE:-
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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NOR GATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity nor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gate;
Architecture nor_gate_beh of nor_gate is
Begin
process(a, b)
begin
if a = '0' and b = '0' then c <= '1';
else c <= '0';
end if;
end process;
end nor_gate_beh;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Dataflow Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity nor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gate;
Architecture nor_gate_df of nor_gate is
Begin
c <= a nor b;
end nor_gate_df;
Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity nor_gate is
Port ( a : in STD_LOGIC;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gate;
Architecture nor_str of nor_gate is
component nor_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : nor_gate port map(a,b,c);
end nor_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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_____________________________________________________________________________________
LOGIC SYMBOL AND TRUTH TABLE:
NOR GATE TRUTH TABLE
27
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SIMULATION RESULTS:
NORGATE:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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XOR GATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity xor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_gate;
Architecture xor_gate_beh of xor_gate is
Begin
process(a, b)
begin
if a = b then c <= '0';
else c <= '1';
end if;
end process;
end xor_gate_beh;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Dataflow MOdel:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity xor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_gate;
Architecture xor_gate_df of xor_gate is
Begin
c <= a xor b;
end xor_gate_df;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity xor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_gate;
Architecture xor_str of xor_gate is
component xor_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : xor_gate port map(a,b,c);
end xor_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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LOGIC SYMBOL AND TRUTH TABLE:
XOR GATE TRUTH TABLE
32
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SIMULATION RESULTS:
Xorgate:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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XNOR GATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity xnor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gate;
Architecture xnor_gate_beh of xnor_gate is
Begin
process(a, b)
begin
if a = b then c <= '1';
else c <= '0';
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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end if;
end process;
end xnor_gate_beh;
Dataflow Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity xnor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gate;
Architecture xnor_gate_df of xnor_gate is
Begin
c <= a xnor b;
end xnor_gate_df;
Structural Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity xnor_gate is
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gate;
Architecture xnor_str of xnor_gate is
component xnor_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
U1 : xnor_gate port map(a,b,c);
end xnor_str;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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_____________________________________________________________________________________
LOGIC SYMBOL AND TRUTH TABLE:
XNOR GATE TRUTH TABLE
37
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SIMULATION RESULTS:
Xnorgate:
RESULT:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
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3 – 8 DECODER
AIM:
To write VHDL and verilog program for 3 – 8 Decoder simulate the program and verify the
results.
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
See the output ports by varying the input ports.
VHDL PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( g1,g2,g3 : in std_logic;
A : in std_logic_vector(2 downto 0);
Y : out std_logic_vector(0 to 7));
end decoder;
architecture Behavioral of decoder is
signal Y1:std_logic_vector(0 to 7 );
begin with A select Y1<= "01111111" when "000",
"10111111" when "001",
"11011111" when "010",
"11101111" when "100",
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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_____________________________________________________________________________________
"11110111" when "011",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when others;
Y<= Y1 when (G1 and not G2 and not G3)='1'
else "11111111";
end Behavioral;
VERILOG PROGRAM:
module decoderverilog(a,b,c,en, z);
input a,b,c,en;
output [7:0] z;
wire abar,bbar,cbar;
not(abar,a);
not(bbar,b);
not(cbar,c);
and(z[0],en,abar,bbar,cbar);
and(z[1],en,abar,bbar,c);
and(z[2],en,abar,b,cbar);
and(z[3],en,abar,b,c);
and(z[4],en,a,bbar,cbar);
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and(z[5],en,a,bbar,c);
and(z[6],en,a,b,cbar);
and(z[7],en,a,b,c);
endmodule
LOGIC SYMBOL AND TRUTH TABLE:
3 x 8 decoder
TRUTH TABLE
44
A (0) OUT1
G1 OUT1G2A
OUT1G2B OUT1
A (1) OUT1A (2) OUT1
Y0 O1T
1
Y1 OUT
1Y2
OUT1
Y3 OUT
1
Y4 OUT
1Y5
OUT1Y6
OUT1
Y7 OUT
1
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Ex. No: Date:
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INPUTS OUTPUTS
G1 G2A_L G2B_L C B A Y7_L Y6_L Y5_L Y4_L Y3_L Y2_L Y1_L Y0_L
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
RTL SCHEMATIC:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : decodervhdl.ngr
Top Level Output File Name : decodervhdl
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 14
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_____________________________________________________________________________________
Macro Statistics :
# Decoders : 1
# 1-of-8 decoder : 1
Cell Usage :
# BELS : 10
# INV : 1
# LUT2 : 1
# LUT3 : 8
# FlipFlops/Latches : 8
# LDE : 8
# IO Buffers : 14
# IBUF : 6
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : xa2s50etq144-6
Number of Slices: 5 out of 768 0%
Number of Slice Flip Flops: 8 out of 1536 0%
Number of 4 input LUTs: 9 out of 1536 0%
Number of bonded IOBs: 14 out of 102 13%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
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-----------------------------------+------------------------+-------+
_n0000(_n00001:O) | NONE(*)(z_7) | 8 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial
logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with
BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock
signals to help prevent skew problems.
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: 4.922ns
Maximum output required time after clock: 6.613ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00001:O'
Total number of paths / destination ports: 32 / 16
-------------------------------------------------------------------------
Offset: 4.922ns (Levels of Logic = 2)
Source: e3_inv (PAD)
Destination: z_7 (LATCH)
Destination Clock: _n00001:O falling
Data Path: e3_inv to z_7
Gate Net
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.797 0.920 e3_inv_IBUF (e3_inv_IBUF)
INV:I->O 8 0.468 2.050 z_0__n00011_INV_0 (z_0__n0001)
LDE:GE 0.687 z_0
----------------------------------------
Total 4.922ns (1.952ns logic, 2.970ns route)
(39.7% logic, 60.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00001:O'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 6.613ns (Levels of Logic = 1)
Source: z_7 (LATCH)
Destination: z<7> (PAD)
Source Clock: _n00001:O falling
Data Path: z_7 to z<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LDE:G->Q 1 1.091 0.920 z_7 (z_7)
OBUF:I->O 4.602 z_7_OBUF (z<7>)
----------------------------------------
Total 6.613ns (5.693ns logic, 0.920ns route)
(86.1% logic, 13.9% route)
=========================================================================
CPU : 3.48 / 4.31 s | Elapsed : 4.00 / 4.00 s
-->
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Number of warnings : 1 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
SIMULATION RESULTS:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
2x4 DE MULTIPLEXER
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for demultiplexer , simulate the program and verify the
results
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
52
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
54
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
VHDL PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demultiplexer is
Port ( s1 : in std_logic;
sel : in std_logic_vector ( 1 downto 0);
q : out std_logic_vector ( 3 downto 0));
end demultiplexer;
architecture Behavioral of demultiplexer is
signal q1 : std_logic_vector ( 3 downto 0);
begin
with sel select q1<= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
q<= q1 when s1= '0'
else "1111";
end Behavioral;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
verilog program :
module demuxverilog(d,en, s, y);
input d,en;
input [2:0] s;
output [7:0] y;
wire s2bar,s1bar,s0bar;
not(s2bar,s[2]);
not(s1bar,s[1]);
not(s0bar,s[0]);
and(y[0],d,en,s2bar,s1bar,s0bar);
and(y[1],d,en,s2bar,s1bar,s[0]);
and(y[2],d,en,s2bar,s[1],s0bar);
and(y[3],d,en,s2bar,s[1],s[0]);
and(y[4],d,en,s[2],s1bar,s0bar);
and(y[5],d,en,s[2],s1bar,s[0]);
and(y[6],d,en,s[2],s[1],s0bar);
and(y[7],d,en,s[2],s[1],s[0]);
endmodule
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
LOGIC SYMBOL AND TRUTH TABLE:
2 X 4 DEMULTIPLEXER TRUTH TABLE
57
INPUTS OUTPUT
EN S0 S1 DATA Y
0 X X X 0
1 0 0 A Y0
1 0 1 A Y1
1 1 0 A Y2
1 1 1 A Y3
S0 OUT1
Y0 OUT1Y1 OUT1Y2 OUT1Y3 OUT1
A
S1 OUT1
EN
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
RTL SCHEMATIC:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : vhdldemux.ngr
Top Level Output File Name : vhdldemux
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 8
Cell Usage :
# BELS : 4
# LUT4 : 4
# IO Buffers : 8
# IBUF : 4
# OBUF : 4
=========================================================================
Device utilization summary:
---------------------------
59
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Selected Device : xa2s50etq144-6
Number of Slices: 2 out of 768 0%
Number of 4 input LUTs: 4 out of 1536 0%
Number of bonded IOBs: 8 out of 102 7%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 8.307ns
Timing Detail:
--------------
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 16 / 4
-------------------------------------------------------------------------
Delay: 8.307ns (Levels of Logic = 3)
Source: d (PAD)
Destination: y<3> (PAD)
Data Path: d to y<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 0.797 1.520 d_IBUF (d_IBUF)
LUT4:I0->O 1 0.468 0.920 _n00101 (y_2_OBUF)
OBUF:I->O 4.602 y_2_OBUF (y<2>)
----------------------------------------
Total 8.307ns (5.867ns logic, 2.440ns route)
(70.6% logic, 29.4% route)
=========================================================================
CPU : 3.95 / 4.83 s | Elapsed : 4.00 / 4.00 s
-->
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
61
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Number of infos : 0 ( 0 filtered)
SIMULATION RESULTS
62
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
8_3 ENCODER
AIM:
To write VHDL & verilog program for encoder ,simulate the program and verify the results.
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
63
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
64
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
65
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is
Port ( d : in std_logic_vector(7 downto 0);
b : out std_logic_vector(2 downto 0));
end encoder;
architecture Behavioral of encoder is
begin
process(d)
begin
case d is
when "00000001"=>b<="000";
when "00000010"=>b<="001";
when "00000100"=>b<="010";
when "00001000"=>b<="011";
when "00010000"=>b<="100";
when "00100000"=>b<="101";
when "01000000"=>b<="110";
when "10000000"=>b<="111";
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
when others =>null;
end case;
end process;
end Behavioral;
VERILOG CODE:
module encoder(d, en, y);
input [7:0] d;
input en;
output [2:0] y;
wire a,b,c;
or(a,d[1],d[3],d[5],d[7]);
or(b,d[2],d[3],d[4],d[7]);
or(c,d[4],d[5],d[6],d[7]);
and(y[0],a,en);
and(y[1],b,en);
and(y[2],c,en);
endmodule
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
RTL SCHEMATIC:
68
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : encoder.ngr
Top Level Output File Name : encoder
Output Format : NGC
69
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS : 11
# LUT2 : 2
# LUT3 : 1
# LUT4 : 8
# FlipFlops/Latches : 3
# LD : 3
# IO Buffers : 11
# IBUF : 8
# OBUF : 3
=========================================================================
Device utilization summary:
---------------------------
Selected Device : xa2s50etq144-6
Number of Slices: 6 out of 768 0%
Number of Slice Flip Flops: 3 out of 1536 0%
Number of 4 input LUTs: 11 out of 1536 0%
Number of bonded IOBs: 11 out of 102 10%
=========================================================================
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
N167(_n0040148:O) | NONE(*)(b_2) | 3 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial
logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with
BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock
signals to help prevent skew problems.
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: 4.927ns
Maximum output required time after clock: 6.613ns
Maximum combinational path delay: No path found
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_n0040148:O'
Total number of paths / destination ports: 24 / 3
-------------------------------------------------------------------------
Offset: 4.927ns (Levels of Logic = 3)
Source: d<2> (PAD)
Destination: b_0 (LATCH)
Destination Clock: _n0040148:O falling
Data Path: d<2> to b_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 0.797 1.320 d_2_IBUF (d_2_IBUF)
LUT2:I0->O 2 0.468 1.150 Ker121 (N12)
LUT4:I1->O 1 0.468 0.000 _n0000<0> (_n0000<0>)
LD:D 0.724 b_0
----------------------------------------
Total 4.927ns (2.457ns logic, 2.470ns route)
(49.9% logic, 50.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0040148:O'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 6.613ns (Levels of Logic = 1)
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Source: b_2 (LATCH)
Destination: b<2> (PAD)
Source Clock: _n0040148:O falling
Data Path: b_2 to b<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 1.091 0.920 b_2 (b_2)
OBUF:I->O 4.602 b_2_OBUF (b<2>)
----------------------------------------
Total 6.613ns (5.693ns logic, 0.920ns route)
(86.1% logic, 13.9% route)
=========================================================================
CPU : 2.70 / 2.97 s | Elapsed : 2.00 / 3.00 s
-->
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
73
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SIMULATION RESULTS
74
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
MOD-53 COUNTER
75
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for mod 53 counter ,simulate the program and verify the
results.
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
76
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
77
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
78
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
VHDL PROGRAM :
Library ieee;
Use iee.std_logic_1164.all;
Use iee.numeric_std_all;
Entity modul is
Generic (n bits:positive:=4;gpto positive:=12);
Port(clk,reset:in std_logic;
Q:out std_logic_vector(0 to nbits-1);
Qn:out std_logic_vector(0to n bits-1));
End module;
Architecture behavior of modul is
Begin
Process(clk)
Variable enter_value :unsigned(nbits-1 downto 0);
Begin
If(clk and clk’event==1)then
If(reset=’1’)then
Enter_value:=(other=>0);
Else
Enter_value:=(enter_value+1)modupto;
End if;
End if;
Q<=std_logic_vector(enter_value);
Qn<=std_logic_vector(enter_value);
End process;
End behaviour;
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
RTL SCHEMATIC
80
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : module.ngr
Top Level Output File Name : module
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 20
Macro Statistics :
# Counters : 1
# 7-bit up counter : 1
Cell Usage :
# BELS : 29
# GND : 1
# INV : 1
# LUT1 : 1
# LUT2 : 1
# LUT3 : 1
# LUT3_L : 7
# LUT4 : 2
# MUXCY : 7
# VCC : 1
# XORCY : 7
# FlipFlops/Latches : 7
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
# FDRSE : 7
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 19
# IBUF : 11
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s50eft256-6
Number of Slices: 6 out of 768 0%
Number of Slice Flip Flops: 7 out of 1536 0%
Number of 4 input LUTs: 12 out of 1536 0%
Number of bonded IOBs: 20 out of 182 10%
Number of GCLKs: 1 out of 4 25%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 7 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
Minimum period: 4.957ns (Maximum Frequency: 201.735MHz)
Minimum input arrival time before clock: 6.052ns
Maximum output required time after clock: 9.690ns
Maximum combinational path delay: 9.325ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 4.957ns (frequency: 201.735MHz)
Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Delay: 4.957ns (Levels of Logic = 8)
Source: iq_0 (FF)
Destination: iq_6 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: iq_0 to iq_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRSE:C->Q 3 0.992 1.320 iq_0 (iq_0)
LUT3_L:I2->LO 1 0.468 0.000 iq_inst_lut3_01 (iq_inst_lut3_0)
MUXCY:S->O 1 0.515 0.000 iq_inst_cy_1 (iq_inst_cy_1)
MUXCY:CI->O 1 0.058 0.000 iq_inst_cy_2 (iq_inst_cy_2)
MUXCY:CI->O 1 0.058 0.000 iq_inst_cy_3 (iq_inst_cy_3)
MUXCY:CI->O 1 0.058 0.000 iq_inst_cy_4 (iq_inst_cy_4)
MUXCY:CI->O 1 0.058 0.000 iq_inst_cy_5 (iq_inst_cy_5)
MUXCY:CI->O 0 0.058 0.000 iq_inst_cy_6 (iq_inst_cy_6)
XORCY:CI->O 1 0.648 0.000 iq_inst_sum_6 (iq_inst_sum_6)
83
MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
FDRSE:D 0.724 iq_6
----------------------------------------
Total 4.957ns (3.637ns logic, 1.320ns route)
(73.4% logic, 26.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 91 / 21
-------------------------------------------------------------------------
Offset: 6.052ns (Levels of Logic = 2)
Source: ld (PAD)
Destination: iq_6 (FF)
Destination Clock: clk rising
Data Path: ld to iq_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 9 0.797 2.150 ld_IBUF (ld_IBUF)
LUT3:I0->O 7 0.468 1.950 _n00051 (_n0005)
FDRSE:CE 0.687 iq_0
----------------------------------------
Total 6.052ns (1.952ns logic, 4.100ns route)
(32.3% logic, 67.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 14 / 8
-------------------------------------------------------------------------
Offset: 9.690ns (Levels of Logic = 3)
Source: iq_2 (FF)
Destination: rc0 (PAD)
Source Clock: clk rising
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Ex. No: Date:
_____________________________________________________________________________________
Data Path: iq_2 to rc0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRSE:C->Q 3 0.992 1.320 iq_2 (iq_2)
LUT4:I0->O 1 0.468 0.920 _n00017 (CHOICE23)
LUT2:I0->O 1 0.468 0.920 _n000119 (rc0_OBUF)
OBUF:I->O 4.602 rc0_OBUF (rc0)
----------------------------------------
Total 9.690ns (6.530ns logic, 3.160ns route)
(67.4% logic, 32.6% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 9.325ns (Levels of Logic = 4)
Source: ent (PAD)
Destination: rc0 (PAD)
Data Path: ent to rc0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.797 1.150 ent_IBUF (ent_IBUF)
LUT4:I2->O 1 0.468 0.920 _n00017 (CHOICE23)
LUT2:I0->O 1 0.468 0.920 _n000119 (rc0_OBUF)
OBUF:I->O 4.602 rc0_OBUF (rc0)
----------------------------------------
Total 9.325ns (6.335ns logic, 2.990ns route)
(67.9% logic, 32.1% route)
=========================================================================
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Ex. No: Date:
_____________________________________________________________________________________
CPU : 4.34 / 6.34 s | Elapsed : 5.00 / 6.00 s
-->
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
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Ex. No: Date:
_____________________________________________________________________________________
SIMULATION RESULTS
.
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Ex. No: Date:
_____________________________________________________________________________________
8x1 MULTIPLEXER
AIM:
To write VHDL & verilog program for Multiplexer, simulate the program and verify the results
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
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Ex. No: Date:
_____________________________________________________________________________________
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
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Ex. No: Date:
_____________________________________________________________________________________
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port ( s : in std_logic_vector(2 downto 0);
d : in std_logic_vector(7 downto 0);
y,y1 : out std_logic);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process ( s,d)
begin
case s is when "000" => y<= d(0) ;y1 <= not d(0);
when "001" => y<= d(1) ;y1 <= not d(1);
when "010" => y<= d(2) ;y1 <= not d(2);
when "011" => y<= d(3) ;y1 <= not d(3);
when "100" => y<= d(4) ;y1 <= not d(4);
when "101" => y<= d(5) ;y1 <= not d(5);
when "110" => y<= d(6) ;y1 <= not d(6);
when "111" => y<= d(7) ;y1 <= not d(7);
when others => y<='1';
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_____________________________________________________________________________________
end case;
end process;
end Behavioral;
VERILOG CODE:
module amuxverilog(a, s, y);
input [7:0] a;
input [2:0] s;
output y;
wire k,l,m,n,o,p,q,r,g,h,i;
not(g,s[2]);
not(g,s[1]);
not(i,s[0]);
and(k,a[0],g,h,i);
and(l,a[1],g,h,s[0]);
and(m,a[2],g,s[1],i);
and(n,a[3],g,s[1],s[0]);
and(o,a[4],s[2],h,i);
and(p,a[5],s[2],h,s[0]);
and(q,a[6],s[2],s[1],i);
and(r,a[7],s[2],s[1],s[0]);
or(y,k,l,m,n,o,p,q,r);
endmodule
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Ex. No: Date:
_____________________________________________________________________________________
LOGIC SYMBOL AND TRUTH TABLE:
8X1 MULTIPLEXER
TRUTH TABLE
INPUTS OUTPUT
EN S0 S1 S2 DATA Y
0 X X X X 0
1 0 0 0 A0 A0
1 0 0 1 A1 A1
93
S0 OUT1
A0 OUT1
A1 OUT1A2 OUT1A3 OUT1 Y
A4 OUT1A5 OUT1A6 OUT1A7 OUT1S1 OUT1S2 OUT1
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
1 0 1 0 A2 A2
1 0 1 1 A3 A3
1 1 0 0 A4 A4
1 1 0 1 A5 A5
1 1 1 0 A6 A6
1 1 1 1 A7 A7
RTL SCHEMATIC
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Ex. No: Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : mux.ngr
Top Level Output File Name : mux
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 13
Cell Usage :
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Ex. No: Date:
_____________________________________________________________________________________
# BELS : 7
# LUT2 : 1
# LUT4 : 5
# MUXF5 : 1
# IO Buffers : 13
# IBUF : 12
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : xa2s50etq144-6
Number of Slices: 3 out of 768 0%
Number of 4 input LUTs: 6 out of 1536 0%
Number of bonded IOBs: 13 out of 102 12%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
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_____________________________________________________________________________________
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 11.505ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 19 / 1
-------------------------------------------------------------------------
Delay: 11.505ns (Levels of Logic = 6)
Source: s<2> (PAD)
Destination: y (PAD)
Data Path: s<2> to y
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 0.797 1.520 s_2_IBUF (s_2_IBUF)
LUT4:I0->O 1 0.468 0.000 y97_F (N87)
MUXF5:I0->O 1 0.422 0.920 y97 (CHOICE71)
LUT4:I2->O 1 0.468 0.920 y111 (CHOICE72)
LUT2:I0->O 1 0.468 0.920 y124 (y_OBUF)
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_____________________________________________________________________________________
OBUF:I->O 4.602 y_OBUF (y)
----------------------------------------
Total 11.505ns (7.225ns logic, 4.280ns route)
(62.8% logic, 37.2% route)
=========================================================================
CPU : 2.44 / 2.73 s | Elapsed : 3.00 / 3.00 s
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
SIMULATION RESULTS
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Ex. No: Date:
_____________________________________________________________________________________
RIPPLE CARRY ADDER:
AIM:
To write VHDL & verilog program for ripple carry adder , simulate the program and verify the
results
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
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Ex. No: Date:
_____________________________________________________________________________________
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
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Ex. No: Date:
_____________________________________________________________________________________
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
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Ex. No: Date:
_____________________________________________________________________________________
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
VHDL CODE:
entity rca is
port(a:in std_logic _vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
cin:in std_logic;
sum:out std_logic _vector(3 downto 0);
cout:out std_logic);
end rca;
architecture rca of rca is
component fulladder is
port( a,b,c:in std_logic;
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_____________________________________________________________________________________
sum,carry:out std_logic);
end component;
sgnal c:std_logic_vector(2 downto 0);
begin
f1:fulladder portmap(a(0),b(0),cin,sum1(0),c(0));
f2:fulladder portmap(a(1),b(1),c(0),sum1(1),c(1));
f3:fulladder portmap(a(2),b(2),c(1),sum1(2),c(2));
f4:fulladder portmap(a(3),b(3),c(2),sum1(3),cout);
end rca;
---------------sub program for ripple carry adder---------------
Fulladder:
Entity fulladder is
Port(a,b,cin:in std_logic;
Sum,carry:out std_logic);
End fulladder;
Architecture behav of fulladder is
signal p,q,r,s,:std_logic;
begin
p<=a xorb;
sum<=p xor cin;
q<=a and b;
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_____________________________________________________________________________________
r<=b and c;
s<= and cin;
carry<=q or r or s;
end behav;
VERILOG CODE:
Module rca(a,b,cin,sum,carry);
Input[3:0]a;
Input[3:0]b;
Input cin;
Ouput[3:0]sum;
Output carry;
Wire x,y,z;
F1(cin,a[0],b[0],sum[0],x);
F2(x,a[1],b[1],sum[1],y);
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Ex. No: Date:
_____________________________________________________________________________________
F3(y,a[2],b[2],sum[2],z);
F4(z,a[3],b[3],sum[3],carry);
End module
-------------sub program for ripple carry adder--------------
Module fulladder(a,b,cin,sum,carry);
Input a,b,cin;
Output sum,carry;
Reg p,q,t2,t3;
Always @(a or b or c)
Begin
Sum=a^b^c;
Ps1=a^b;
Qt1=a&b;
Rt2=b&c;
St3=a&c;
Carry=(a&b/(b&c)/(a&c));
End
End module
RTL SCHEMATIC
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Ex. No: Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : rc_adder.ngr
Top Level Output File Name : rc_adder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
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Ex. No: Date:
_____________________________________________________________________________________
Design Statistics
# IOs : 13
Macro Statistics :
# Xors : 3
# 1-bit xor3 : 3
Cell Usage :
# BELS : 7
# LUT2 : 1
# LUT3 : 4
# LUT4 : 2
# IO Buffers : 13
# IBUF : 8
# OBUF : 5
=========================================================================
Device utilization summary:
---------------------------
Selected Device : xa2s50etq144-6
Number of Slices: 4 out of 768 0%
Number of 4 input LUTs: 7 out of 1536 0%
Number of bonded IOBs: 13 out of 102 12%
=========================================================================
TIMING REPORT
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Ex. No: Date:
_____________________________________________________________________________________
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 11.343ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 28 / 5
-------------------------------------------------------------------------
Delay: 11.343ns (Levels of Logic = 5)
Source: num1<0> (PAD)
Destination: carry (PAD)
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Ex. No: Date:
_____________________________________________________________________________________
Data Path: num1<0> to carry
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 0.797 1.320 num1_0_IBUF (num1_0_IBUF)
LUT4:I1->O 2 0.468 1.150 Ker41 (N4)
LUT3:I2->O 2 0.468 1.150 c21 (c2)
LUT3:I0->O 1 0.468 0.920 Mxor_sum<3>_Xo<1>1 (sum_3_OBUF)
OBUF:I->O 4.602 sum_3_OBUF (sum<3>)
----------------------------------------
Total 11.343ns (6.803ns logic, 4.540ns route)
(60.0% logic, 40.0% route)
=========================================================================
CPU : 2.80 / 3.19 s | Elapsed : 3.00 / 4.00 s
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
SIMULATION RESULTS
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
UNIVERSAL COUNTER
AIM:
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
To write VHDL & verilog program for universal counter, simulate the program and verify the
results
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
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Ex. No: Date:
_____________________________________________________________________________________
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
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Ex. No: Date:
_____________________________________________________________________________________
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
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Ex. No: Date:
_____________________________________________________________________________________
Vhdl code:
entity counter is
generic(n:integer:=8);
Port ( clk,reset,load,ud : in std_logic; din: in std_logic_vector(n-1 downto 0); q: out
std_logic_vector(n-1 downto 0));
end counter;
architecture Behavioral of counter is
signal count :std_logic_vector(n-1 downto 0);
begin
process(clk,reset,load,ud)
begin
if(clk='1' and clk'event )then
if(reset='1')then
count<="00000000";
else if(load='1')then
count<=din;
else
if(ud='1')then
count<=count+1;
else
count<=count-1;
end if;
end if;
end if;
end if;
q<=count;
end process;
end Behavioral;
VERILOG CODE:
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Ex. No: Date:
_____________________________________________________________________________________
module count(clk, reset, up_down, q);
input clk;
input reset;
input up_down;
output [7:0]q;
reg[7:0]count;
always@(posedge clk or posedge reset)
begin
if(reset==1)
count=0;
else
if(up_down==1)
count=count-1;
else
count=count+1;
end
assign q=count;
endmodule
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Ex. No: Date:
_____________________________________________________________________________________
RTL SCHEMATIC
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Ex. No: Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : counter.ngr
Top Level Output File Name : counter
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 20
Macro Statistics :
# Counters : 1
# 8-bit updown counter : 1
Cell Usage :
# BELS : 35
# GND : 1
# INV : 1
# LUT2 : 1
# LUT4_L : 8
# MULT_AND : 7
# MUXCY : 8
# VCC : 1
# XORCY : 8
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Ex. No: Date:
_____________________________________________________________________________________
# FlipFlops/Latches : 8
# FDRSE : 8
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 19
# IBUF : 11
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : xa2s50etq144-6
Number of Slices: 5 out of 768 0%
Number of Slice Flip Flops: 8 out of 1536 0%
Number of 4 input LUTs: 9 out of 1536 0%
Number of bonded IOBs: 20 out of 102 19%
Number of GCLKs: 1 out of 4 25%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
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Ex. No: Date:
_____________________________________________________________________________________
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 8 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 4.845ns (Maximum Frequency: 206.398MHz)
Minimum input arrival time before clock: 7.168ns
Maximum output required time after clock: 6.744ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 4.845ns (frequency: 206.398MHz)
Total number of paths / destination ports: 64 / 8
-------------------------------------------------------------------------
Delay: 4.845ns (Levels of Logic = 9)
Source: count_0 (FF)
Destination: count_7 (FF)
Source Clock: clk rising
Destination Clock: clk rising
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Ex. No: Date:
_____________________________________________________________________________________
Data Path: count_0 to count_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRSE:C->Q 2 0.992 1.150 count_0 (count_0)
LUT4_L:I1->LO 1 0.468 0.000 count_inst_lut4_01 (count_inst_lut4_0)
MUXCY:S->O 1 0.515 0.000 count_inst_cy_1 (count_inst_cy_1)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_2 (count_inst_cy_2)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_3 (count_inst_cy_3)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_4 (count_inst_cy_4)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_5 (count_inst_cy_5)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_6 (count_inst_cy_6)
MUXCY:CI->O 0 0.058 0.000 count_inst_cy_7 (count_inst_cy_7)
XORCY:CI->O 1 0.648 0.000 count_inst_sum_7 (count_inst_sum_7)
FDRSE:D 0.724 count_7
----------------------------------------
Total 4.845ns (3.695ns logic, 1.150ns route)
(76.3% logic, 23.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 160 / 16
-------------------------------------------------------------------------
Offset: 7.168ns (Levels of Logic = 11)
Source: load (PAD)
Destination: count_7 (FF)
Destination Clock: clk rising
Data Path: load to count_7
Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.797 1.150 load_IBUF (load_IBUF)
INV:I->O 8 0.468 2.050 count_inst_lut1_01_INV_0 (count_inst_lut1_0)
LUT4_L:I0->LO 1 0.468 0.000 count_inst_lut4_01 (count_inst_lut4_0)
MUXCY:S->O 1 0.515 0.000 count_inst_cy_1 (count_inst_cy_1)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_2 (count_inst_cy_2)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_3 (count_inst_cy_3)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_4 (count_inst_cy_4)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_5 (count_inst_cy_5)
MUXCY:CI->O 1 0.058 0.000 count_inst_cy_6 (count_inst_cy_6)
MUXCY:CI->O 0 0.058 0.000 count_inst_cy_7 (count_inst_cy_7)
XORCY:CI->O 1 0.648 0.000 count_inst_sum_7 (count_inst_sum_7)
FDRSE:D 0.724 count_7
----------------------------------------
Total 7.168ns (3.968ns logic, 3.200ns route)
(55.4% logic, 44.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 6.744ns (Levels of Logic = 1)
Source: count_7 (FF)
Destination: q<7> (PAD)
Source Clock: clk rising
Data Path: count_7 to q<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
FDRSE:C->Q 2 0.992 1.150 count_7 (count_7)
OBUF:I->O 4.602 q_7_OBUF (q<7>)
----------------------------------------
Total 6.744ns (5.594ns logic, 1.150ns route)
(82.9% logic, 17.1% route)
=========================================================================
CPU : 3.39 / 3.77 s | Elapsed : 4.00 / 4.00 s
-->
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
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_____________________________________________________________________________________
SIMULATION RESULTS
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UNIVERSAL SHIFT REGISTER
AIM:
To write VHDL & verilog program for universal shift register , simulate the program and verify
the results
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
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_____________________________________________________________________________________
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
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_____________________________________________________________________________________
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
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Ex. No: Date:
_____________________________________________________________________________________
VHDL CODE:
entity shiftreg is
Port ( clk : in std_logic; dsr : in std_logic; drl : in std_logic; clr_l : in std_logic;
clk_l : in std_logic; s : in std_logic_vector(1 downto 0); d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end shiftreg;
architecture Behavioral of shiftreg is
begin
process(clk,s,clr_l)
begin
if clr_l='0'then
q<=(others=>'0');
elsif clk_l='1'then
if(clk'event and clk='1')then
case s is
when"00"=>q<= q;
when"01"=>q<=q(2 downto 0)& dsr;
when"10"=>q<= drl & q(3 downto 1);
when"11"=>q<=d(3)& d(2)&d(1)&d(0);
when others=>null;
end case;
end if;
end if;
end process;
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end Behavioral;
VERILOG CODE:
module shift (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp <= tmp << 1;
tmp[0] <= SI;
end
assign SO = tmp[7];
endmodule
port(
C, SI, CLR : in std_logic;
SO : out std_logic);
end shift;
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_____________________________________________________________________________________
RTL SCHEMATIC
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SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : shift.ngr
Top Level Output File Name : shift
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 3
Macro Statistics :
# Shift Registers : 1
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# 8-bit shift register : 1
Cell Usage :
# BELS : 2
# GND : 1
# VCC : 1
# FlipFlops/Latches : 1
# FDE : 1
# Shifters : 1
# SRL16E : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 2
# IBUF : 1
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s50eft256-6
Number of Slices: 1 out of 768 0%
Number of Slice Flip Flops: 1 out of 1536 0%
Number of 4 input LUTs: 1 out of 1536 0%
Number of bonded IOBs: 3 out of 182 1%
Number of GCLKs: 1 out of 4 25%
=========================================================================
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TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
C | BUFGP | 2 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 4.712ns (Maximum Frequency: 212.224MHz)
Minimum input arrival time before clock: 2.300ns
Maximum output required time after clock: 6.514ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'C'
Clock period: 4.712ns (frequency: 212.224MHz)
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Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 4.712ns (Levels of Logic = 0)
Source: Mshreg_tmp<7>_srl_0 (FF)
Destination: Mshreg_tmp<7>_0 (FF)
Source Clock: C rising
Destination Clock: C rising
Data Path: Mshreg_tmp<7>_srl_0 to Mshreg_tmp<7>_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
SRL16E:CLK->Q 1 3.068 0.920 Mshreg_tmp<7>_srl_0 (Mshreg_tmp<7>__net0)
FDE:D 0.724 Mshreg_tmp<7>_0
----------------------------------------
Total 4.712ns (3.792ns logic, 0.920ns route)
(80.5% logic, 19.5% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'C'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.300ns (Levels of Logic = 1)
Source: SI (PAD)
Destination: Mshreg_tmp<7>_srl_0 (FF)
Destination Clock: C rising
Data Path: SI to Mshreg_tmp<7>_srl_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
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_____________________________________________________________________________________
---------------------------------------- ------------
IBUF:I->O 1 0.797 0.920 SI_IBUF (SI_IBUF)
SRL16E:D 0.583 Mshreg_tmp<7>_srl_0
----------------------------------------
Total 2.300ns (1.380ns logic, 0.920ns route)
(60.0% logic, 40.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'C'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 6.514ns (Levels of Logic = 1)
Source: Mshreg_tmp<7>_0 (FF)
Destination: SO (PAD)
Source Clock: C rising
Data Path: Mshreg_tmp<7>_0 to SO
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 1 0.992 0.920 Mshreg_tmp<7>_0 (Mshreg_tmp<7>_0)
OBUF:I->O 4.602 SO_OBUF (SO)
----------------------------------------
Total 6.514ns (5.594ns logic, 0.920ns route)
(85.9% logic, 14.1% route)
=========================================================================
CPU : 3.38 / 5.47 s | Elapsed : 3.00 / 5.00 s
-->
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_____________________________________________________________________________________
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
SIMULATION RESULTS
.
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COMPARATOR
AIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. Give the Timing simulation for critical path time calculation & also
synthesis for digital Circuit.
d. Implement the place & route technique for major FPGA vendori.e. XILINX
e. Implement the designed digital circuit using FPGA &CPLD devices.
APPARATUS:
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Ex. No: Date:
_____________________________________________________________________________________
1. System
2. Xilinx Software
3. Sparton-3 FPGA devices
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
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Ex. No: Date:
_____________________________________________________________________________________
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
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Ex. No: Date:
_____________________________________________________________________________________
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Generic(N:integer :=3);
port(a,b:in std_logic_vector(n downto 0); alb,aeb,agb: out std_logic);
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_____________________________________________________________________________________
end comparator;
architecture Behavioral of comparator is
begin
process(a,b)
begin
if(a<b) then alb<='1';
else alb<='0';
end if;
if(a>b)
then agb<='1';else agb<='0';
end if;
if(a=b)then aeb<='1';else aeb<='0';
end if;
end process;
end Behavioral;
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Ex. No: Date:
_____________________________________________________________________________________
RTL Schematic:
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_____________________________________________________________________________________
Fig:Block Diagram Representation For Comparator
Fig: RTL Schematic Report for Comparator
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Fig:Technical Schematic Report For Comparator
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Ex. No: Date:
_____________________________________________________________________________________
================================================================================
* Synthesis Report for Comparator *
=================================================================================
Final Results
RTL Top Level Output File Name : comparator.ngr
Top Level Output File Name : comparator
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS : 11
# LUT2 : 1
# LUT4 : 8
# MUXF5 : 2
# IO Buffers : 11
# IBUF : 8
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_____________________________________________________________________________________
# OBUF :
===============================================================
Timing Report for Comparator:
==============================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 38 / 3
----------------------------------------------------------------------------------------------------
Delay : 9.683ns (Levels of Logic = 5)
Source : a<1> (PAD)
Destination : agb (PAD)
Data Path: a<1> to agb
Gate Net
Cell: in->out fan-out Delay Delay Logical Name (Net Name)
---------------------------------------- ---------------------------------------------------------
IBUF:I->O 3 0.715 1.066 a_1_IBUF (a_1_IBUF)
LUT4:I0->O 2 0.479 1.040 agb139 (agb1_map106)
LUT4:I0->O 1 0.479 0.000 agb1842 (N198)
MUXF5:I0->O 1 0.314 0.681 agb184_f5 (agb_OBUF)
OBUF:I->O 4.909 agb_OBUF (agb)
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_____________________________________________________________________________________
--------------------------------------------------------------------------------------------------
Total 9.683ns (6.896ns logic, 2.787ns route)
(71.2% logic, 28.8% route)
PRECAUTIONS:
Note down the results without parallax error.
Avoid the loose connections while designs the circuit.
Observe the waveforms carefully.
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Ex. No: Date:
_____________________________________________________________________________________
Fig: Simulation Report For Comparator
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Ex. No: Date:
_____________________________________________________________________________________
DFLIPFLOP
AIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. Give the Timing simulation for critical path time calculation & also
synthesis for digital circuit.
d. Implement the place & route technique for major FPGA vendor i.e., XILINX
e. Implement the designed digital circuit using FPGA &CPLD devices.
APPARATUS:
1. System
2. Xilinx Software
3. Sparton-3 FPGA devices
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
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Ex. No: Date:
_____________________________________________________________________________________
Choose the settings & click on next & finally click on finish.
Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
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Ex. No: Date:
_____________________________________________________________________________________
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
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Ex. No: Date:
_____________________________________________________________________________________
See the output ports by varying the input ports.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dflipflop is
Port ( clk : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end dflipflop;
architecture Behavioral of dflipflopf is
begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
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_____________________________________________________________________________________
end if;
end process;
end Behavioral;
RTL SCHEMATIC:
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_____________________________________________________________________________________
Fig: technology schematic
SYNTHESIS:
================================================================* Final
Report *
===============================================================
Final Results
RTL Top Level Output File Name : dflipflop.ngr
Top Level Output File Name : dflip-flop
Output Format : NGC
Optimization Goal : Speed
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_____________________________________________________________________________________
Keep Hierarchy : NO
Design Statistics
# IOs : 3
Macro Statistics:
# Registers : 1
# 1-bit register : 1
Cell Usage:
# Flip-flops/Latches : 1
# FD : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 2
# IBUF : 1
# OBUF : 1
================================================================Timing constraint: Default
OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 1 / 1
---------------------------------------------------------------------------------------------------------
Offset: 2.441ns (Levels of Logic = 1)
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_____________________________________________________________________________________
Source: d (PAD)
Destination: q (FF)
Destination Clock: clk rising
Data Path: d to q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------------------------------------------------------- -------
IBUF:I->O 1 0.797 0.920 d_IBUF (d_IBUF)
FD:D 0.724 q
--------------------------------------------------------------------------------------------------
Total 2.441ns (1.521ns logic, 0.920ns route)
(62.3% logic, 37.7% route)
PRECAUTIONS:
Note down the results without parallax error.
Avoid the loose connections while designs the circuit.
Observe the waveforms carefully.
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Ex. No: Date:
_____________________________________________________________________________________
SIMULATION:
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Ex. No: Date:
_____________________________________________________________________________________
JK FLIPFLOP
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Ex. No: Date:
_____________________________________________________________________________________
AIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. Give the Timing simulation for critical path time calculation & also
Synthesis for digital circuit.
d. Implement the place & route technique for major FPGA vendor i.e., XILINX
e. Implement the designed digital circuit using FPGA &CPLD devices.
APPARATUS:
1. System
2. Xilinx Software
3. Sparton-3 FPGA devices
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.
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Ex. No: Date:
_____________________________________________________________________________________
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
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Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
See the output ports by varying the input ports.
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PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( clk : in bit;
j : in bit;
k : in bit;
reset : in bit;
q : buffer bit);
end jkff;
architecture Behavioral of jkff is
begin
process(clk,reset)
begin
if(reset='1') then
q <='0';
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elsif(clk'event and clk='1') then
if(j='0' and k='0') then
q<=q;
elsif(j='0' and k='1') then
q<='0';
elsif(j='1' and k='0') then
q<='1';
elsif(j='1' and k='1') then
q<= not q;
end if;
end if;
end process;
end Behavioral;
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RTL SCHEMATIC:
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SYNTHESIS:
===============================================================
* Final Report *
===============================================================
Final Results
RTL Top Level Output File Name : jkff.ngr
Top Level Output File Name : jkff
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 5
Macro Statistics :
# Registers : 1
# 1-bit register : 1
# Multiplexers : 1
# 1-bit 4-to-1 multiplexer : 1
Cell Usage :
# BELS : 2
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# LUT2 : 1
# LUT3_L : 1
# FlipFlops/Latches : 1
# FDCE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 4
# IBUF : 3
# OBUF : 1
=============================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.334ns (frequency: 299.940MHz)
Total number of paths / destination ports: 1 / 1
-----------------------------------------------------------------------------------------------------
Delay: 3.334ns (Levels of Logic = 1)
Source: q (FF)
Destination: q (FF)
Source Clock: clk rising
Destination Clock: clk rising
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Data Path: q to Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -------------------------------------------------------
FDCE:C->Q 2 0.992 1.150 q (q_OBUF)
LUT3_L:I2->LO 1 0.468 0.000 _n00011 (_n0001)
FDCE:D 0.724 q
-------------------------------------------------------------------------------------------------
Total 3.334ns (2.184ns logic, 1.150ns route)
(65.5% logic, 34.5% route)
PRECAUTIONS:
Note down the results without parallax error.
Avoid the loose connections while designs the circuit.
Observe the waveforms carefully.
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SIMULATION:
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SR FLIPFLOP
AIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. Give the Timing simulation for critical path time calculation & also
Synthesis for digital circuit.
d. Implement the place & route technique for major FPGA vendor i.e., XILINX
e. Implement the designed digital circuit using FPGA &CPLD devices.
APPARATUS:
1. System
2. Xilinx Software
3. Sparton-3 FPGA devices
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
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Double click on create new source.
Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click on‘t’ ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will get model sim
simulator option on the process window.
Click on ‘+’ icon of model sim simulator then double click on simulator behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.
Right click on the signal and select the force value.
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Change the value from ‘U’ to either ‘0’ or ‘1’ and click OK and click on run icon & similarly vary the
inputs value for all possible options and observe the output.
Close the model sim simulator and come back to implementation in the source for options.
Click on ‘+’ icon of user constraints and double click on floor plan ID pre-Synthesis.
Click on ‘Yes’ and enter the pin numbers in the LOC column and click on save icon and click on ‘OK’.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the ‘.bit’ file & select open when device XC3S400 is selected and click OK.
Right click on device XC3S400 and choose program option by clicking of right click and click on OK.
Impact will start to download the ‘bit’ file to board.
Once you got the program succeeded message ,you can test the output on board.
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See the output ports by varying the input ports.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity srff is
Port ( s : in bit;
r : in bit;
clk : in bit;
q : buffer std_logic);
end srff;
architecture Behavioral of srff is
begin
process(clk)
begin
if clk='1' and clk'event then
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if(s='0' and r='0') then q<=q;
elsif(s='0' and r='1') then q<='0';
elsif(s='1' and r='0') then q<='1';
elsif(s='1' and r='1') then q<='Z';
end if;
end if;
end process;
end Behavioral;
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RTL SCHEMATIC:
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FIG: TECHNOLOGICAL SCHEMATIC
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SYNTHESIS:
================================================================
* Final Report *
================================================================
Final Results
RTL Top Level Output File Name : srff.ngr
Top Level Output File Name : srff
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 4
Macro Statistics :
# Registers : 2
# 1-bit register : 2
# Multiplexers : 1
# 1-bit 4-to-1 multiplexer : 1
# Tristates : 1
# 1-bit tristate buffer : 1
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Cell Usage :
# BELS : 3
# LUT2 : 3
# FlipFlops/Latches : 2
# FDE : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 3
# IBUF : 2
# OBUFT : 1
================================================================Device utilization
summary:
--------------------------------------------------------------------------------------------------------
Selected Device : 2s50eft256-6
Number of Slices: 2 out of 768 0%
Number of Slice Flip Flops: 2 out of 1536 0%
Number of 4 input LUTs: 3 out of 1536 0%
Number of bonded IOBs: 4 out of 182 2%
Number of GCLKs: 1 out of 4 25%
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================================================================Timing constraint: Default
OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 8 / 4
-------------------------------------------------------------------------------------------------------
Offset: 4.422ns (Levels of Logic = 2)
Source: r (PAD)
Destination: Mtrien_q (FF)
Destination Clock: clk rising
Data Path: r to Mtrien_q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -------------------------------------------------
IBUF:I->O 3 0.797 1.320 r_IBUF (r_IBUF)
LUT2:I0->O 2 0.468 1.150 _n00121 (_n0012)
FDE:CE 0.687 Mtrien_q
-----------------------------------------------------------------------------------------------
Total 4.422ns (1.952ns logic, 2.470ns route)
(44.1% logic, 55.9% route)
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PRECAUTIONS:
Note down the results without parallax error.
Avoid the loose connections while designs the circuit.
Observe the waveforms carefully.
SIMULATION
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