1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click pulse (b) one load pulse (c) eight clock pulses (d) one clock pulse for each1 in the data 3. To parallel load a byte of data into a shift register with a synchronous load, there must be (a) one click pulse (b) one clock pulse for each1 in the data (c) eight clock pulses (d) one clock pulse for each 0 in the data 4. The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains (a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101 5. With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in (a) 80 µs (b) 8 µs (c) 80ms (d) 10 µs 6. With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register (a) in 8 µs (b) in the propagation delay time of eight flip-flops (c) in 1 µs (d) in the propagation delay time of one flip-flop 7. A modulus-10 Johnson counter requires (a) Ten flip-flops (b) four flip-flops (c) five flip-flops (d) twelve flip 8. A modulus10-ring counter requires a minimum of (a) Ten flip-flops (b) five flip-flops (c) four flip-flops (d) twelve flip-flops 9. When an 8-bit serial in/ serial out shift register is used for a 24 µs time delay. The clock frequency must be (a) 41.67 KHz (b) 333 KHz (c) 125 KHz (d) 8 MHz 10. The purpose of the ring counter in the keyboard encoding circuit of Figure 10-38 is (a) To sequentially apply a HIGH to each row for detection of key closure (b) to provide trigger pulses for the key code register (c) To sequentially apply a LOW to each row for detection of key closure (d) To sequentially reverse bias the diodes in each row 11. A CPLD is a (a) CMOS PLD (b) Complex PLD (c) Complementary PLD (d) capacitive PLD 12. A CPLD contains (a) Shift registers (b) Programmable interconnections (c)logic arrays (d) answer (a) & (c)
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1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage
2. To serially shift a byte of data into a shift register, there must be (a) one click pulse (b) one load pulse (c) eight clock pulses (d) one clock pulse for each1 in the data 3. To parallel load a byte of data into a shift register with a synchronous load, there must be (a) one click pulse (b) one clock pulse for each1 in the data (c) eight clock pulses (d) one clock pulse for each 0 in the data 4. The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state of 11100100. After two clock pulses, the register contains
(a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101 5. With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in (a) 80 µs (b) 8 µs (c) 80ms (d) 10 µs 6. With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register (a) in 8 µs (b) in the propagation delay time of eight flip-flops (c) in 1 µs (d) in the propagation delay time of one flip-flop 7. A modulus-10 Johnson counter requires (a) Ten flip-flops (b) four flip-flops (c) five flip-flops (d) twelve flip 8. A modulus10-ring counter requires a minimum of (a) Ten flip-flops (b) five flip-flops (c) four flip-flops (d) twelve flip-flops 9. When an 8-bit serial in/ serial out shift register is used for a 24 µs time delay. The clock
frequency must be (a) 41.67 KHz (b) 333 KHz (c) 125 KHz (d) 8 MHz 10. The purpose of the ring counter in the keyboard encoding circuit of Figure 10-38 is (a) To sequentially apply a HIGH to each row for detection of key closure (b) to provide trigger pulses for the key code register (c) To sequentially apply a LOW to each row for detection of key closure (d) To sequentially reverse bias the diodes in each row 11. A CPLD is a (a) CMOS PLD (b) Complex PLD (c) Complementary PLD (d) capacitive PLD 12. A CPLD contains (a) Shift registers (b) Programmable interconnections
(a) Ripple counter (b) multiple clock counters (c) decade counters (d) modulus counter 2. An asynchronous counter differs from a synchronous counter in (a) The number of states in its sequence (b) The method of clocking
(c) The type of flip-flops used (d) the value of the modulus 3. The modulus of a counter is (a) The number of flip-flops (b) The actual number of states in its sequence (c) The number of times it recycles in a second (d) The maximum possible number of states 4. A 3-bit binary counter has a maximum modulus of (a) 3 (b) 6 (c) 8 (d) 16 5. A 4-bit binary counter has a maximum modulus of (a) 16 (b) 32 (c) 8 (d) 4 6. A modulus-12 counter must have (a) 12 flip flops (b) 3 flip flops (c) 4 flip flops (d) synchronous clocking 7. Which one of the following is an example of a counter with a truncated modulus? (a) Modulus 8 (b) Modulus 14 (c) Modulus 16 (d) Modulus 32 8. A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock
to Q output of 12 ns. For the counter to recycle form 1111 to 0000. It takes a total of (a) 12 ns (b) 24 ns (c) 48 ns (d) 36 ns 9. A BCD counter is an example of (a) a full-modulus counter (b) a decade counter (c) A truncated-modulus counter (d) answers (b) and (c) 10. Which of the following is an invalid state in an 8421 BCD counter? (a) 1100 (b) 0010 (c) 0101 (d) 1000 11. The cascaded modulus-10 counters have an overall modulus of (a) 30 (b) 100 (c) 1000 (d) 10,000 12. A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5
counter, a modulus-8 counter, and two modulus-10 counters. The lowest output frequency possible is
13. A 4-bit binary up/down counter is in the binary state of zero. The next state in DOWN mode is
(a) 0001 (b) 1111 (c) 1100 (d) 1110 14. The terminal count of a modulus-13 binary counter is (a) 0000 (b) 1111 (c) 1101 (d) 1100 15. Which of the following ABEL equations refers to a registered output? (a) X = A & B; (b) !X = !(A&B); (c) X: = A & B (d) X - > A & B
1. If an S-R latch has a 1 on the S input and a 0 on the R input then the S input goes to 0, the latch will be (a) set (b) reset (c) invalid (d) clear
2. The invalid state of an S-R latch occurs when (a) S= 1, R=0 (b) S=0 , R=1 (c) S=1, R=1 (d) S=0 , R=0 3. For a gated D latch, the Q output always equals to the D input (a) Before the enable pulse (b) during the enable pulse (c) Immediately after the enable pulse (d) answer (b) and (c) 4. Like the latch, the flip-flop belongs to a category of logic circuits known as (a) Mono stable multivibrators (b) bi stable multi vibrators (c) astable multivibrators (d) one-shots 5. The purpose of the clock input to a flip-flop is to (a) Clear the device (b) Set the device
(c) Always cause the output to change states (d) Cause the output to assume a state dependent on the controlling (S-R, J-K , or D) inputs.
6. For an edge-triggered D flip-flop. (a) A change in the state of the flip-flop can occur only at a clock pulse edge. (b) The state that the flip-flop goes to depends on the D input (c) The output follows the input at each clock pulse (d) All of these answers
7. A feature that distinguishes the J-K flip-flop from the S-R flip-flop is the (a) toggle conditions (b) Preset input (c) type of clock (d) clear input 8. A flip-flop is in the toggle condition when (a) J=1, K=0 (b) J=1, K=1 (c) J=0 , K=0 (d) J=0, K=1 9. A J-K flip-flop with J=1 and K=1 has a 10 KHz clock input. The Q output is
(a) constantly HIGH (b) Constantly LOW (c) a 10 KHz square wave (d) a 5 KHz square wave
10. A one-shot is a type of (a) monostable multivibrator (b) astable multi vibrator (c) timer (d) answer (a) & (c) 11. The output pulse width of a non re-triggerable one-shot depends on (a) The trigger intervals (b) The supply voltage (c) A resistor and capacitor (d) The threshold voltage 12. An stable multivibrator (a) requires a periodic trigger input (b) has no stable state (c) Is an oscillator
(d) produces a periodic pulse output (e) answers (a),(b),(c) & (d) (f) answers (b), (c) and (d) only 13. The GAL22V10 has
(a) 10 inputs and 22 outputs (b) 22 inputs and 10 outputs (c) 8 inputs and 10 input/outputs (d) 11 inputs and 10 outputs
14. The GAL16V8 has (a) 8 inputs and 16 outputs (b) 16 inputs and 8 outputs (c) 8 inputs and 8 input/outputs (d) 8 inputs and 8 outputs
15. An OLMC is an (a) Output Latch Main Cell (b) Odd Logic Multiplexer cell (c) Optimum Logic Minimization (d) Output Logic Macro cell 16. A typical OLMC consists of (a) Gates, multiplexers, and a flip-flop (b) Gates and a shift register (c) A Gray code counter (d) A fixed logic array
1. The GAL22V10 has
(a) 10 Inputs and 22 outputs (b) 22 dedicated inputs and 10 outputs (c) 12 dedicated inputs and 10 dedicated outputs (d) 12 dedicated inputs and 10 outputs any of which can be an input
2. The GAL22V10 operates on a de-supply voltage of (a) .5 V (b) 10 V (c) 3.3 V (d) 1.2 V 3. OLMC stands for (a) Output logic modular circuit (b) Output logic macrocell (c) Output latch memory cell (d) Overall logic matrix circuit 4. The three states of a tri state output buffer are (a) HIGH, LOW, High impedance (b) HIGH, LOW, Ground
(c) HIGH, LOW, in between (d) Right, Left, center 5. The OLMC of the GAL22V10 contains (a) One OR gate, one flip-flop, two multiplexers
(b) One OR gate, one flip-flop, one multiplexer (c) One AND gate, one latch, two multiplexers (d) One OR gate, one flip-flop, two decoders
6. The GAL16V8 has (a)16 dedicated inputs and 8 outputs (b) 8 dedicated inputs and 8 inputs/outputs (c) 8 inputs and 16 outputs (d) 16 input/outputs and 8 outputs 7. ABEL stands for (a) Advanced Bit Enable Language (b) Alternate Boolean Expression Language (c) Advanced Boolean Expression Language (d) Advanced Boolean Expression Logic 8. ABEL provides three means of data entry as follows. (a) Equation, graph, state diagram (b) Equation, truth table, state diagram (c) Equation, schematic, table (d) Word, number, symbol 9. A test vector
(a) Tests a logic design in an SPLD (b) Tests the HDL before Programming (c) Tests the compiler (d) Tests the SPLD before programming
10. The three sections of an ABEL input file are (a) Declarations, target device, test vectors (b) Device, Pins, sets
(c) Declarations, logic descriptions, test vectors (d) Device declaration, pin declaration, set declaration
11. A cell map is the same as (a) The JTAG (b) The JEDEC file (c) The fuse map (d) both (b) and (c) 12. The symbol for NOT, AND, OR, and, XOR in ABEL are (a) !, & , +, $ (b) !, @, #, $
(c) !, &, #, $ (d) *, &, + , ! 13. The sum-of-products expression, X= `ABC + A`BC + AB`C is written in ABEL as (a) X= !ABC # A!BC # AB!C; (b) X = = !A & B & C # A&!B&C # A&B&!C; (c) X= !A&B&C # A&!B&C # A&B&!C (d) X= (!A&B&C) + (A& !B & C) + (A&B&!C);
1. A half – adder is characterized by (a) Two inputs and two outputs (b) Three inputs and two outputs (c) Two inputs and three outputs (d) two inputs and one output 2. A full-adder is characterized by (a) Two inputs and two outputs (b) three inputs and two outputs (c) Two inputs and three outputs (d) Two inputs and one output 3. The inputs to a full-adder are A=1, B=1, Cin= 0 the outputs are (a) ∑ = 1, Cout = 1 (b) ∑ = 1, Cout = 0 (c) ∑ = 0, Cout = 1(d) ∑ = 0, Cout = 0 4. A r-bit parallel adder can add (a) Two 4-bit binary number (b) Two 2-bit binary number (c) Four bit at a time (d) Four bits in sequence 5. The 74LS83A is an example of a 4-bit parallel adder. To expand this device to an 8-bit
adder. You must (a) Use four adders with no interconnections. (b) Use two adders and connect the sum outputs of one to the bit inputs of the other (c) Use eight adders with no interconnections. (d) Use two adders with the carry output of one connected to the carry input of the
other. 6. If a 74HC85 magnitude comparator has A= 1011 and B= 1001 on its inputs, the outputs
are (a) A > B = 0, A < B =1, A= B = 0 (b) A > B=1, A< B= 0, A= B =0 (c) A > B = 1, A < B = 1, A= B = 0 (d) A > B=0, A< B = 0, A = B=1 7. If a 1-of-16 decoder with active LOW outputs exhibits a LOW on the decimal 12 output,
what (a) A3 A2 A1 A0 = 1010 (b) A3 A2 A1 A0 = 1110 (c) A3 A2 A1 A0 = 1100 (d) A3 A2 A1 A0 = 0100 8. A BCD-to-7 segment decoder has 0100 on its inputs. (a) a ,c ,f ,g (b) b, c, f, g (c) b, c, e, f (d) b, d, e, g 9. If an octal-to-binary priority encoder has its 0,2,5 and 6 inputs at the active level, the
active- High binary output is (a) 110 (b) 010 (c) 101 (d) 000 10. In general, a multiplexer has (a) One data input, several data outputs, and selection inputs (b) One data input, one data output, and one selection inputs (c) Several data inputs, several data outputs, and selection inputs (d) Several data inputs, one data output, and selection inputs 11. Data Selectors are basically the same as (a) Decoders (b) demultiplexers (c) Multiplexer (d) Encoders 12. Which of the following codes exhibit even parity? (a) 10011000 (b) 01111000 (c) 11111111 (d) 11010101 (e) all (f) both answers (a) and (c)
13. To conventionally program an SPLD , you need a (a) Special fixture (b) Special fixture and a master PLD that has been preprogrammed at the factory (c) Computer and a programmer (d) Computer, a programmer, and HDL software (e) Computer, a programmer and BASIC software 14. ISP stands for (a) In-System Programmable (b) Integrated System Program (c) Integrated Silicon Programmer 15. ABEL and CUPL are types of (a) Programmers (b) PLDs (c) HDL Software (d) disk operation 2 systems 16. A logic circuit design to be implemented in an SPLD is first description in (a) A declaration (b) An input file (c) A JEDEC file (d) a documentation file
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