Multi-Site Parallel Testing with the S535 Wafer Acceptance Test System––APPLICATION NOTE

In semiconductor wafer production, minimizing the cost of test has

been identified as the number one challenge. The biggest factor

in the cost of test, as well as in the cost of test system ownership,

is throughput of the tester/prober combination. Multi-site parallel

testing, regardless of the specific application, offers the greatest

improvement to throughput for on-wafer test. This is because the

majority of the overhead costs relate to the combination of test

time plus moving the probe pins to the next test site. Increasing

the throughput of this tester/prober combination can result in a

significantly reduced cost of test and faster production ramp-up.

Fig 1. The S535 system (show to the right) is configured for multi-site parallel testing, which is ideal for applications such as:

• Multi-site, small-scale analog/mixed signal functional testing

• Multi-site parametric die sort

• Multi-site wafer level reliability (WLR) testing

The Multi-site Parallel Test ConceptThe device under test (DUT) or test element group (TEG) on the

wafer includes a number of elements that require testing. In a

sequential test regime (Figure 2), the testing of each element, no

matter how simple, adds to the overall test time. If two identical

elements on different sites can be tested in parallel (Figure 3), the

total test throughput can be doubled. In addition, the number of

prober moves is cut in half, resulting in a significant improvement in

test system throughput improvement.Figure 1. S535 Multi-Site Test System.

Figure 3. Multi-Site prober movement and test sequence.

Figure 2. Traditional Single-Site prober movement and test sequence.

PARALLEL TEST PROBER MOVEMENT

PROBER MOVEMENT

2 | WWW.TEK.COM/KEITHLEY

Multi-Site Parallel Testing with the S535 Wafer Acceptance Test System APPLICATION NOTE

The multi-site parallel test concept has throughput advantages

over traditional parallel test methods. Traditional parallel testing

is performed on multiple devices on the same site. Once all

testing on one site is completed, the prober indexes to the

next site. By contrast, the multi-site parallel testing method is

performed on multiple devices on different (multiple) sites at

the same time. This eliminates all “dead time” between tests,

and means there is no waiting for any one test to complete

before the prober indexes to the next site. The test program is

written so that similar devices are tested at the same time.

ConsiderationsIt is important to take possible parasitic interactions

between devices into consideration. The coupling through

the wafer substrate or the common terminal on vertical devices

may require executing certain low current tests sequentially.

For example, when measuring device leakage levels of a few

pico-amps, there can be interaction between devices. In such

cases, the test plan would consist of a combination of single-

site sequential tests and multi-site parallel tests. Fortunately,

most testing of small-scale analog/mixed signal devices does

not require measuring leakage currents this low.

Another key is managing the limitations of the probing

technology. If the distances between sites that are to be

probed simultaneously are too far away, the probe station

can suffer from alignment errors, which can result in

inconsistent test results and poor yields. Be sure to check

with the prober vendor to determine the maximum distance

between test sites.

System Architecture

A multi-site tester can be thought of as a system of multi-group

testers. Each group consists of all the resources needed to

execute a suite of tests on a single site. Figures 5 and 6 illustrate

two types of multi-group testers. Each group has several

source-measure units (SMUs) for DC testing. The TSP (Test

Script Processor) master unit is unique Keithley technology

that enables each group to operate autonomously, independent

from the other group. Tektronix/Keithley has two types of multi-

site system solutions, which are defined by software. The first

solution is based on Keithley Test Environment (KTE) software,

which runs on a Linux controller (Figure 5). The second solution

is based on Automated Characterization Suite (ACS) software,

which runs on a Windows® controller (Figure 6).

Figure 5. S535 KTE multi-site system architecture.

Figure 6. S500 ACS multi-site system architecture.

SMU1 (Master)

SMU2

Prob

e C

ard

SITE

1SI

TE 2

GROUP 1

SMU3

SMUn

SMU1 (Master)

SMU2

GROUP 2

SMU3

SMUn

Mat

rix

Linu

x C

ontro

ller

TSP

Mas

ter

SMU1 (Master)

SMU2

Prob

e Ca

rd

SITE

1SI

TE 2

GROUP 1

SMU3

SMUn

SMU1 (Master)

SMU2

GROUP 2

SMU3

SMUn

Mat

rix

Win

dows

Con

trolle

r

Figure 4. Multi-site probing example with acceptable distance between test sites.

SITE 1

SITE 2

WWW.TEK.COM/KEITHLEY | 3

Multi-Site Parallel Testing with the S535 Wafer Acceptance Test System APPLICATION NOTE

Benchmark Examples

Wafer Acceptance Test (WAT) of an RF Amplifier1. DC functional testing is performed directly on the device. A total of 2,000 devices (sites) are tested on each wafer.

2. A typical single-site, sequential tester requires 4 seconds per site for all measurements, and 0.2 seconds for each prober movement between sites. The total wafer test time is 8,400 seconds or 2.34 hours.

3. The S535 Multi-Site Parallel Tester also takes 4 seconds to perform all measurements, however it tests 2 sites at the same time, therefore taking an equivalent time of 2 seconds per site. Prober movement time remains 0.2 seconds, however since the devices are tested in parallel, there are half as many moves to make to cover the entire wafer. Total wafer test time is 4200 seconds or 1.17 hours.

Conclusion: By reducing WAT time from 2.34 hrs/wafer to 1.17 hrs/wafer, an additional 3.4 wafers are able to be processed per 8 hour shift. Projecting this to 24/7/365 operation, the use of multi-site parallel test enables an additional 3700 wafers to be processed per year, which is an incremental output of 7.4 million devices.

S535 KTE Multi-Site System FeaturesThe Linux-based S535 KTE system architecture is illustrated

in Figure 5. Note the TSP master unit on the left-hand side,

which handles all communications traffic and enhances

throughput. This single master unit concept ensures accurate

time synchronization for all the instruments under its control

• All LAN communications and the new TSP Master feature enhance overall speed improvement

• 2636B, 2461 SMU, and 7510 DMM available

• Max 200V @ 100mA (with the Model 2636B SMU)

• Max 100V @ 1A (with the Model 2461 SMU)

• Max dual 32 output pins with three SMUs and GND unit per site, or quad 16 output pins with one SMU and GND unit per site

• Linux-operated workstation

S500 ACS Multi-Site System FeaturesThe Windows-based S500 ACS system architecture is

illustrated in Figure 6. Each group has its own TSP master

unit, which supports independent operation of the group.

Also, ACS allows for creating a flexible configuration:

• Supports most instruments as options, including C-V meter, DMM, etc.

• Customized hardware configuration available

• No limit on the number of output pins

• High throughput performance

• Customized test module available

• Windows-operated workstation

Measurement ProberIndex Measurement X 2000 sites = 8400 sec./wafer =

2.34 hrs./waferProberIndex

ProberIndex

ProberIndex

4 sec. 0.2 sec. 0.2 sec.

0.2 sec. 0.2 sec.

Site01:

Measurement

Measurement

Measurement

Measurement

Site101: Site102: 4 sec./2 = 2 equivalent seconds

4 sec.

Site02:

Site01: Site02:

4 sec./2 = 2 equivalent seconds

X 2000 sites = 4200 sec./wafer = 1.17 hrs./wafer

SINGLE-SITE OPERATION

MULTI-SITE OPERATION

4 | WWW.TEK.COM/KEITHLEY

Multi-Site Parallel Testing with the S535 Wafer Acceptance Test System APPLICATION NOTE

SINGLE-SITE OPERATION

MULTI-SITE OPERATION

TEST SITE #1 and #11

Site01: TEG01ProberIndex Measurement X 50 sites = 160 sec./wafer =

2.67 min./wafer

ProberIndex

ProberIndex

2.8 sec. 0.2 sec. 0.2 sec.

X 25 sites = 80 sec./wafer = 1.34 min./wafer

Site01: TEG02

2.8 sec.

Measurement

Measurement

Site01: TEG01

Measurement

Site01: TEG02

Measurement

Measurement

Site11: TEG01

Site11: TEG02

2.8 sec./2 = 1.4 equivalent seconds 2.8 sec./2 = 1.4 equivalent seconds

ProberIndex

0.2 sec. 0.2 sec.

TEST SITE #1

Single-site, sequential test stations. Multi-site, parallel test station.

Figure 7. Using a multi-site parallel test system can cut the total cost of ownership in half by doubling production throughput while reducing the number of probers, freeing up fab floor space, and reducing maintenance requirements.

TEG Testing of an Image Sensor

1. DC parametric testing is performed on two TEGs per test site. A total of 50 sites are tested on each wafer.

2. A typical single-site, sequential tester requires 2.8 seconds per site for all measurements, and two 0.2 second prober movements per site. The total wafer test time is 160 seconds or 2.67 minutes.

3. The S535 Multi-Site Parallel Tester also takes 2.8 seconds to perform all measurements, however it tests 2 sites at the same time, therefore taking an equivalent time of 1.4 seconds per site. Prober movement time remains 0.2 seconds, however since the TEGs are tested in parallel, there are half as many moves to make to cover the entire wafer. Total wafer test time is 80 seconds or 1.34 minutes.

Conclusion: By testing two TEGs in parallel, the S535 Multi-Site Parallel Tester doubles the throughput of the tester/prober combination compared to the single-site, sequential tester. By comparison, increasing the measurement speed of the single-site sequential tester by 30% results in a total wafer test time of 118 seconds or 1.97 minutes. In this case, the multi-site parallel tester is 32% faster due to the impact of reduced prober index time.

ConclusionReducing the cost of test and the cost of ownership are significant challenges in the semiconductor production market.

Throughput of the tester/prober combination is the largest factor in both cases.

WWW.TEK.COM/KEITHLEY | 5

Multi-Site Parallel Testing with the S535 Wafer Acceptance Test System APPLICATION NOTE

Contact Information: Australia* 1 800 709 465

Austria 00800 2255 4835

Balkans, Israel, South Africa and other ISE Countries +41 52 675 3777

Belgium* 00800 2255 4835

Brazil +55 (11) 3759 7627

Canada 1 800 833 9200

Central East Europe / Baltics +41 52 675 3777

Central Europe / Greece +41 52 675 3777

Denmark +45 80 88 1401

Finland +41 52 675 3777

France* 00800 2255 4835

Germany* 00800 2255 4835

Hong Kong 400 820 5835

India 000 800 650 1835

Indonesia 007 803 601 5249

Italy 00800 2255 4835

Japan 81 (3) 6714 3086

Luxembourg +41 52 675 3777

Malaysia 1 800 22 55835

Mexico, Central/South America and Caribbean 52 (55) 56 04 50 90

Middle East, Asia, and North Africa +41 52 675 3777

The Netherlands* 00800 2255 4835

New Zealand 0800 800 238

Norway 800 16098

People’s Republic of China 400 820 5835

Philippines 1 800 1601 0077

Poland +41 52 675 3777

Portugal 80 08 12370

Republic of Korea +82 2 565 1455

Russia / CIS +7 (495) 6647564

Singapore 800 6011 473

South Africa +41 52 675 3777

Spain* 00800 2255 4835

Sweden* 00800 2255 4835

Switzerland* 00800 2255 4835

Taiwan 886 (2) 2656 6688

Thailand 1 800 011 931

United Kingdom / Ireland* 00800 2255 4835

USA 1 800 833 9200

Vietnam 12060128

* European toll-free number. If not

accessible, call: +41 52 675 3777Rev. 02.2018

Find more valuable resources at TEK.COM

Copyright © Tektronix. All rights reserved. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Specification and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. All other trade names referenced are the service marks, trademarks or registered trademarks of their respective companies.

071618 AH 1KW-61423-0