Guest Editors’ Introduction.........................................................................................................................................................................................................................

MULTICORE: THE VIEWFROM EUROPE

......As guest editors, we are extremelyhonored to introduce the IEEE Micro specialissue on European multicore computingprojects. In 2004, the European Commissionfunded the HiPEAC Network of Excellenceas an instrument to overcome the researchlandscape fragmentation in the fields of com-puter architecture and compilation in Eu-rope. In response to the paradigm shift tomulticore-based computers, the EuropeanCommission has also invested in several collab-orative research projects that investigate a widerange of topics aimed at advancing the state ofthe art in multicore computing, most of whichare defined in the context of the HiPEACnetwork. Many of these projects are in theirfinal phases or successfully completed.

This special issue seeks to provide a ratherrepresentative snapshot of the innovationsthat have taken place in these projects. Weanticipated the challenge of addressing proj-ects that had to be performed under collabo-ration by multiple partners, usually fromresearch institutions and companies locatedin different European countries and recog-nized as such by the European Union.

Editorial previewThe first article presents ArchExplorer, a

Web-based open design exploration frame-work that overcomes the burdens of paramet-ric exploration using automated architecturalcomposition in order to focus on structuralexploration, thus expanding the design spaceexploration’s scope. The authors illustratetheir approach through both a careful studyof the on-chip memory subsystem and a

comprehensive investigation of the impactvarious multicore system parameters (such asthe number of cores and processing elements,cache size, and communication infrastructurebandwidth) have on system power consump-tion, chip area, and performance. ArchE-xplorer is one of the great HiPEAC networkcontributions to our research community.

The next four articles describe some of themain results of the Scalable Computer Archi-tecture project. SARC was one of the threeprojects supported by the Future and Emerg-ing Technologies initiative in AdvancedComputing Architectures launched by theEuropean Commission in 2006. It was con-cerned with long-term research (year 2015and onward) in advanced computer architec-ture, compilation, and programming models.It focused on a systematic, scalable approachto computer systems design, ranging fromsmall energy-critical embedded systems tolarge-scale networked data servers.

Ramirez et al. describe the SARC hetero-geneous architecture and its support for theemerging master-worker programming mod-els. The authors study SARC architectureperformance for a set of representative appli-cations from the multimedia, bioinformatics,and scientific domains.

In ‘‘Explicit Communication and Syn-chronization in SARC,’’ Katevenis et al. de-scribe the advanced SARC communicationinterface, a hardware primitive that unifiesthe functionalities of a cache controller andnetwork interface. The article describes thesynchronization and explicit communicationprimitives and discusses the SARC robust

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Mateo Valero

Barcelona Supercomputing

Center

Universitat Politecnica

de Catalunya

Nacho Navarro

Universitat Politecnica

de Catalunya

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2 Published by the IEEE Computer Society 0272-1732/10/$26.00 �c 2010 IEEE

mechanism for event responses. The authorsreport full-system simulation results thatachieved a 10- to 40-percent speed increaseover traditional cache architectures with64 cores. Other improvements concern on-chip network traffic and lock and barrierlatencies.

In their article, Ferrer et al. discuss the scal-ability and productivity of six parallelprogramming models for heterogeneousarchitectures. They conclude that a task-based approach using code and data annota-tions requires the minimal programmingeffort while sustaining close to best perfor-mance. The proposed programming modelmotivated the Open MP extension targetingthe SARC heterogeneous architecture.

In ‘‘SARC Coherence: Scaling DirectoryCache Coherence in Performance andPower,’’ Kaxiras and Keramidas describehow to improve the power scalability ofshared memory multicores by making direc-tory cache coherence more efficient. Theauthors show how to eliminate invalidationtraffic on writes and directory indirectionfor finding the writer. The proposed methodachieves both significant power and perfor-mance improvements compared to a classicalMESI protocol.

The last three articles describe projectswith focuses ranging from hard real-timeembedded multicore design to an automatedtoolchain for application mapping on heter-ogeneous platforms.

Ungerer et al. describe the MERASA

approach to high-performance, real-timemulticore design and analysis techniquesthat guarantees precise timing analyzabilityand predictability. The authors validate theproposed hardware and software techniquesusing a real-world industry-driven scenario.

In ‘‘The VELOX Transactional-MemoryStack,’’ Felber et al. describe their integratedtransactional memory stack, consisting ofhardware support, runtime libraries, com-pilers, programming models, and applicationenvironments. The authors carefully evaluatethe main challenges of the proposed transac-tional memory integration into real systems.

Finally, Bertels et al. present the hArtestoolchain for automated application mappingon a heterogeneous platform consisting of anARM processor, a digital signal processor,

and a field-programmable gate array. Theauthors validate the toolchain using severalcomputationally intensive applications. Theyshow that hArtes supports easy design spaceexploration while performing applicationmapping under restricted hardware availabil-ity and real-time execution constraints.

We hope that you will enjoy the selectedarticles, and we encourage you to provide uswith your feedback.

Article selection process and reviewersWe received more than 30 contributions

from 15 different European projects. Thestrong sampling of completed and ongoingwork in the multicore field was very gratify-ing. Our first thanks go to all of the authorsof the submitted papers, and to all of thereviewers who provided valuable feedbackto help improve the papers’ content andhelped narrow the decision to one appropri-ate subset. We had to involve David Albo-nesi, Chuck Moore, and Ronny Ronen tolead the review of papers we had conflictswith. We are honored to have them onboard and thank them for their great work.

We assigned a minimum of four reviewersto each paper. The strong quality of thepapers made our decision very hard, and fi-nally, due to space constraints, we could se-lect only eight papers for the issue. Becausewe appreciated the involvement of all of thecontributing projects in promoting multicoreresearch in Europe, we convinced the journalto include short summaries of all of the proj-ects with links to their sites (see the ‘‘Euro-pean Multicore Processing Projects’’ sidebarat the end of this special section). These proj-ects provide a good overview of the variety oftopics the European research community isaddressing. Please do not hesitate to contactthe project coordinators if you need more in-formation on a specific topic. MICRO

AcknowledgmentsWe thank Panos Tsarchopoulos, our proj-

ect officer at the European Commission, forhis unconditional support for multicorecomputing research. He strongly believes inthe strengths and the high quality of the Eu-ropean research community, and continuesto successfully support our research fieldinside the European Commission, as is

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indicated by the continuously increasingfunding for this important topic. Wewould like to especially acknowledge Stama-tis Vassiliadis, a great scientist and humanbeing who was one of the main driving forcesbehind the establishment of the HiPEAC,SARC, and hArtes projects presented inthis special issue. Unfortunately, we lost Sta-matis in April 2007, and so our HiPEAC re-search community and the SARC and hArtesprojects were unable to benefit from his deeptechnical insight, enormous enthusiasm, andborderless drive. We are grateful to DavidAlbonesi, IEEE Micro’s editor in chief, forhis continuous support throughout the pro-cess. We thank again all those who contrib-uted time and effort to selecting the articlesand making suggestions for improvements.Finally, thanks to Debby Mosher, adminis-trator for IEEE Micro, for managing the sub-mission and evaluation process, and JoanTaylor for overseeing and building the finalversion of the issue.

Mateo Valero is a professor in the ComputerArchitecture Department at the Universitat

Politecnica de Catalunya (UPC) and thedirector of the Barcelona SupercomputingCenter, the National Center of Supercomput-ing in Spain. His research interests focuses onhigh-performance architectures. Valero has aPhD in telecommunications from UPC. Heis a Fellow of IEEE and the ACM and anIntel Distinguished Research Fellow.

Nacho Navarro is an associate professor ofcomputer engineering at the UniversitatPolitecnica de Catalunya (UPC) and a seniorresearcher at the Barcelona SupercomputingCenter. His research interests include hetero-geneous accelerators (FPGAs and GPUs),runtime support for parallelism and operatingsystems for multicores Navarro has a PhD incomputer science from UPC. He a memberof IEEE, the IEEE Computer Society, andthe ACM.

Direct questions and comments about thisarticle to Mateo Valero or Nacho Navarro,Computer Architecture Dept., UniversitatPolitecnica de Catalunya, Jordi Girona 3,08034 Barcelona, Spain; {mateo, nacho}@ac.upc.edu.

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GUEST EDITORS’ INTRODUCTION