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Multilevel Metallization

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    MULTI LEVEL METALLIZATION

    S.SANGAMESHWAR RAOENGINEERING PHYSICS

    IIT DELHI

    INDO-GERMAN WINTER ACADEMY 2005

    JAMSHEDPUR, INDIA

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    OVERVIEW

    Metallization Importance of Multilevel metallization

    RC Time Delay

    Interconnection materials Metals Junction spiking, Stress migration, Electromigration Properties of Al, Cu, W etc Dielectrics

    Diffusion Barriers and Adhesion Promoters Metallization processing

    PVD, CVD, Electroplating Damascene Process

    Chemical Mechanical Polishing

    Conclusion References

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    Metallization

    Metallization is the process that makes accessible the IC to the

    outside world through conducting pads.

    Doped silicon conduct electricity but have large resistance and lack

    interconnecting facility Thin conductive metal films (Al, Cu, Au, Ag etc) are used as

    interconnects between Si and external leads

    Local Interconnects

    Global Interconnects

    First Level Dielectric

    Ref: Modified Picture from SILICON VLSI TECHNOLOGY By Plummer et al

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    Why interconnect structures are important?

    MetalDielectric

    Global Interconnect

    R = L

    WH

    C = HL

    Ls

    RC = L2

    WLs

    Rough Estimation of Interconnect RC Time Delay

    As technology progresses, Ls decreases RC

    delay increases

    To decrease RC delay -, , L should take low values

    Ls

    L

    H

    R

    C

    W

    Fig: Interconnection delay and device delay

    Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 87-151

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    Needs of new technology

    Lower resistivity metal for interconnect wiring

    Lower dielectric constant material for the interlayer

    dielectric

    Smaller wire lengths-Multilevel Metallization

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    Multi level metallization

    Metal interconnections span several planes isolated by the insulating dielectric layers interconnected by the wiring in the third dimension through the holes

    in the dielectric planes

    Three dimensional network of interconnections is given the namemultilevel interconnections

    Fig: Two level Metallization

    Local Interconnects

    Global Interconnects

    First Level Dielectric

    Second leveldielectric

    Vias

    Ref: Modified Picture from SILICON VLSI TECHNOLOGY By Plummer et al

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    Uses -Multi level metallization

    Reduced interconnection lengths-enhanced

    performance due to reduced RC

    Densification-higher package densities

    Design flexibility

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    Interconnection materials

    MetalsMetal Issues

    Junction spiking Electromigration

    Stress migration

    Important metals

    Aluminum Copper

    Tungsten

    Silver, Gold

    Dielectrics Diffusion barriers and Adhesion promoters

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    Low resistivity

    Easy to deposit Easy to etch and planarize

    High melting point

    High electromigration resistance

    Mechanical stability, adherence to interlayer dielectrics and other

    materials on chip

    Substrate matched coefficient of thermal expansion

    Low stress, high stress migration resistance

    Metals Requirements

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    Controlled microstructure

    Preferably uniform large grains and smooth surfaces

    Oxidation/corrosion resistance

    Low chemical reactivity

    Ideally passivates itself

    Compatible with surrounding materials and their processing

    Bondable to wirings in package

    Environmentally safe material during processing and actual use,and recyclable

    Reliable

    Low cost

    Metals Requirements.contd

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    Metals

    0.82.11.21.92.5

    Thermal stress per degree for

    films on Si(x107 dyn cm-2 0C-1)

    7.83.73.22.22.3Delay

    PoorGoodPoorPoorPoorAdhesion to SiO2

    GoodGoodExcellentPoorPoorCorrosion in air

    13891713223438Specific heat capacity(Jkg-1K-1)

    338766010649621085M.P (0C)

    4.523.514.219.117Coeff. of thermal expansion CTE

    x 106(0C-1)

    1.742.3583.154.253.98Thermal conductivity(Wcm-1)

    41.17.067.858.2712.98Youngs modulus(x10-11 dyn cm-2)

    5.652.662.351.591.67Resistivity

    WAlAuAgCuProperty\Metal

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    Early ICs used pure Al as the interconnect material

    Low resistivity

    Strong adhesion with Si Corrosion resistant

    Problems with pure Al

    Junction spiking

    Electromigration

    Stress migration

    Later ICs used Al alloyed with Cu

    Aluminum

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    Junction spiking

    Solubility of Si in Al is 0. 5 wt% at 4500

    CSi will dissolve into the Al during annealing (at 4500C)

    Solution

    Add Si to the Al

    Introduce a barrier metal layer between the Al and the Si substrate.(TiN)

    Al spikes

    Consider Al-Si contact

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    Stress migration

    Due to difference between coefficient of thermal expansion for Al

    and Si

    Al 23 x 10-6 0

    C-1

    and Si 2.6 x 10-6 0

    C-1

    High compressive stresses in Al at high temperatures

    Movement of Al occurs along grain boundaries

    Whole grains of Al pushed upward forming hillocks Under tensile stress voids are formed

    Al hillock

    SiO2

    Grain Boundary

    Al

    Si substrate

    Compressivestress (due tothermalexpansiondifferencebetween film andsubstrate)

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    Stress migrationcontd

    Consequences

    Electrical shorts between interconnect levels

    Rough surface topography making lithography and etch difficult

    Solution

    Addition of elements that have limited solubility

    Ex:- Cu atoms segregate and precipitate preferentially along the grainboundaries suppressing hillock formation

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    Electromigration

    Transport of mass in metals under the influence of high current

    Occurs by transfer of momentum from electrons to the positive

    metal ions

    High current densities in the smaller devices are responsible forelectron migration

    Grain boundary diffusion is the primary vehicle of mass transport

    Metal in some regions pile up and voids form in other regions

    SiO2

    Al film

    HillockformationElectron

    Flow

    Void

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    Solutions - Electromigration

    Alloying with copper (Al with 0.5%Cu)

    Multilayer structure

    Shunt layer provides alternative path for current flow

    If shunt layer has high melting point and strong mechanical properties,

    they can be more rigid and act as barrier to hillock and void formation

    Oxide

    Ti

    Al

    Void

    Current Flow

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    Good corrosion resistance

    Electromigration and stressmigration stability

    Excellent depositionmethods

    Sometimes used for filling ofvias called plugs

    High resistivity

    Poor adhesion (Adhesionpromoter required-Ti/TiN)

    Tungsten Gold

    Low resistivity

    Very inert; adheres poorly

    Very costly

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    Copper

    Higher conductivity

    More electromigrationresistance

    Higher ultimate tensile

    strength

    Higher melting point, low

    CTE

    Higher thermal conductivity,

    high specific heat, lesser

    Joule heating

    Lack of feasible dry etching

    method

    Lack of self passivating

    oxide similar to Al2O3 on Al

    Poor adhesion to dielectric

    materials such as SiO2 and

    low-k polymers

    Draw backsBenefits

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    Silicides

    Silicon forms stable metallic compound (MSix) with

    metal, called silicide

    Low resistivity and high thermal stability of metal

    silicides make them suitable for VLSI applications

    Silicides be used as local interconnects and adhesion

    promoters

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    Diffusion barriers and adhesion promotersContd

    Barrier

    To stop reaction between

    metals (W, Al etc) and Si or

    between two layers

    Passive barrier (TiN)

    Stuffed barrier (Ti-W alloy)

    Sacrificial barrier

    TiN has contact resistance higher barrier than TiSi2

    Bilayer structure of TiSi2/TiN is used as adhesion promoter and diffusion

    barrier

    Fig: Adhesion and barrier layers

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    Dielectrics

    Conventional SiO2-high dielectric constant-high RC delay

    New materialsFluorine doped SiO2 ~3

    Polymers ~1.9-2.9

    Aerogels ~1.01-2.0

    Small dielectric constant

    High breakdown voltage

    Good adhesion

    High temperature stability

    Low stress

    Dielectric Requirements

    Some dielectrics

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    Multilevel Metallization Processing

    Metal deposition

    PVD

    EvaporationResistance heated Evaporation

    Inductively heated evaporationElectron beam Evaporation

    SputteringDC, RF sputtering

    Magnetron sputtering

    CVD

    Electroplating

    Via and trench formation

    Chemical mechanical Planarization

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    Fig: Two level Metallization

    Local Interconnects

    Global Interconnects

    First Level Dielectric

    Second leveldielectric

    Vias

    Fig: SEM Image showing trenches and vias

    Ref: SILICON VLSI

    TECHNOLOGYBy Plummer et al

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    Physical Vapor Deposition

    Evaporation

    1. Evaporation 2. Sputtering

    Ref: Prof.S.Kal, IIT Kharagpur

    Resistance heated evaporation

    E-Beam Evaporation

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    Sputter Deposition

    Earlier generation ICs- Evaporation

    Present technique Sputtering- Better step coverageRef: Prof.S.Kal, IIT Kharagpur

    Simple DCsputtering is used for

    elemental metal deposition

    For deposition of insulating materials

    such as SiO2, Si3N4, an RFplasma is

    used

    Application of magnetic field

    increases ion bombardment rate

    Magnetic sputtering

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    Step Coverage

    Ref: Prof.S.Kal, IIT Karagpur

    Conformal step coverage refers to

    uniform thickness on both horizontal and

    vertical surfaces

    In evaporation, the deposition speciestravel essentially in straight lines

    because of very low pressure

    Step coverage is very poor

    Solution:2) Sputtering on heated

    substances to cause reflow1) Rotate the wafer

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    Bias sputtering

    Ref: Prof.S.Kal, IIT Kharagpur

    If substrate and deposited films are

    conductive, it is possible to adjust the

    bias on the substrate with respect tothe plasma

    Placing a negative bias on the

    substrate, the ion bombardment of thesubstrate is increased

    Since the sputter etched film may redeposit on the wafer if sputtered

    at low bias, a net improvement in the step coverage may be achieved

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    Chemical Vapor deposition

    Gases are introduced into the substrate that react and form the

    desired film on the surface of the substrate

    Can coat large number of wafers at same time

    Better conformal step coverage than PVD over a wide range of

    topographic profiles

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    Silicide Deposition

    Direct deposition

    and selective etching

    Sputtering from a composite

    target

    Co-sputtering from two targets

    Co-evaporation of metal and Si

    CVD

    Self-aligned silicide process

    Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 87-151

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    Common deposition techniques

    ElectroplatingCu

    CVD

    Reactive Sputter DepositionTiN

    Sputter and surface reactionTiSi2

    Low Pressure CVDW

    Magnetron Sputter deposition (standard, ionized, orcollimated)Ti and Ti-W

    Magnetron Sputter depositionAl

    ProcessMetal

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    Aluminum

    CVD not good for alloys

    Unwanted reactions between the precursors for the various metals

    DC magnetron sputtering is used

    High deposition rates

    Heat the wafers to 150-3500C-To improve step coverage

    Further high temperatures 450-5500

    C For filling deepcontacts and vias

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    Etching of the metal or dielectric films

    Metallization + Lithography+ Etching = Desired pattern

    Dry etching- also called reactive ion etchingChlorine and chlorine containing gases are used to etch Al

    Lack of volatile copper species- Dry etching not possible for Cu

    Wet etching in chemicals - Not good option as it is isotropic

    Solution Damascene Process

    Etching

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    Copper

    Step coverage poor with PVD methods

    Electroplating

    Cu2+ + 2e- Cu

    Thin seed layer (Cu) is required for electrical contact for

    electroplating

    Seed layer by sputtering or CVD

    Excellent filling of vias with electroplating

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    Damascene Technology

    Via and trench formation

    Adhesion and Barrier Layer

    deposition

    Chemical Mechanical

    Planarization

    Second Level Dielectric

    Deposition

    Via and trench formation

    Dry etching is not requiredRef: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 87-151

    Damascene Technology

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    Damascene Technology

    Trench first approach Via first approach

    Major Drawback of Trench first approach: After trench formation,

    photoresist completely pools down into the trench

    Forming fine vias in thick photoresists becomes problem

    Via first approach is most preferred

    Ref: www.icknowledge.com/threshold_simonton/techtrends01.pdf

    Chemical Mechanical Polishing

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    Chemical Mechanical Polishing

    Components

    Surface to be polished (Wafer) Slurry abrasive + chemical

    component Polishing pad

    Mechanism Combination of chemical and

    mechanical effects

    Abrasive particles in slurrygrind against material andloosens it

    Chemicals in slurry etch anddissolve the material

    Chemicals help in damagefree sample

    To achieve planar surface over the entire chip and waferReferred to as global planarityDielectrics, poly silicon or oxide and various metal films can be polished

    Ref: http://www.agc.co.jp/english/products/semiconductor/cmp.html

    Fig: Schematic set-up for CMP

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    Early 2 level structure After CMP

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    Alternatives for future interconnections

    Optical Interconnections

    Higher bandwidth, higher density

    Elimination of cross-talk

    High TC

    superconductors

    Zero resistance below TC High current densities can be carried

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    Conclusion

    Interconnect parameter now dominate nearly all aspects of IC

    performance such as delay, power dissipation, and

    electromigration

    Multi level metallization reduces the RC delay

    Different physical properties of the materials and deposition

    techniques have to be considered

    Sometimes multilayer structures may have to be used (adhesion& barrier layers etc)

    Al as the interconnect material has limitations, Cu is being used

    now But even Cu has some limitations. New technologies like

    damascene, CMP have been developed to overcome the

    limitations of etching etc

    R f

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    References

    1. Multilevel interconnections for ULSI era, S.P.Murarka, Materials

    Science and Engineering, R(19), 87-151

    2. SILICON VLSI TECHNOLOGY By Plummer et al

    3. VLSI Metallization, Prof.S.kal, IIT Kaharagpur

    4. Microchip Fabrication, Peter van Zant, Mc Graw hill

    5. Fundamentals of Semiconductor Processing Technologies, Badih-el

    Kareh, Kluwer Academic Publishers

    6. Semiconductor Devices Physics and Technology, S.M.Sze, Wiley

    7. http://www.agc.co.jp/english/products/semiconductor/cmp.html

    8. www.icknowledge.com/threshold_simonton/techtrends01.pdf

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