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7/27/2019 Myth8 Processor Datapath
1/13
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2/13
Register File
ALU
controlsignals
controlsignals
Control
Unit(CU)
rkrj
rirj rk
Fetch
& Load IR(> 1cc)
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uction Flow
MEMORY SYSTEM
Memory Data Bus
CPU
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8 8
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opcode ri
dr_enb dr_sel[0..1]
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(a) The Myth8 Processor
(1cc)
Decode &
PCIncr
(>= 1cc)
(in ALU)
& Write
Read, Exe.
7/27/2019 Myth8 Processor Datapath
3/13
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4/13
result_sel=00
(select write bus)
result_sel=00
(select write bus)
cntr0=1(MUL DONE) [rj -> ReadBusA
rk -> ReadBusB]
[rj -> ReadBusA
rk -> ReadBusBcounter ,- m-1]
[r7
7/27/2019 Myth8 Processor Datapath
5/13
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7/27/2019 Myth8 Processor Datapath
6/13
Register File
ALU
controlsignals
controlsignals
Con
trolUnit(CU)
rkrj
rirj rk
MEMORY SYSTEM
Memory Data Bus
CPU
readwrite
Mux
Read Bus BRead Bus A
alu_sel[0..2]
a_sel[0..2]
b_sel[0..2]
MAR
mar_sel
8
8
8
MDR
ir1_selir0_sel
r0write
ri_sel
rj_sel
rk_sel
cout, m7, v
8 8
Write Bus
r7write
Memory Address Bus
opcode
cin
IR1IR0
Clk
Clk
Clk
result_sel[0..1]
Clk
4-8 sign ext.
opcode ri
dr_enb dr_sel[0..1]
Clk
The Myth8 Processor
7/27/2019 Myth8 Processor Datapath
7/13
Register File
ALU
controlsignals
controlsignals
Con
trolUnit(CU)
rkrj
rirj rk
MEMORY SYSTEM
Memory Data Bus
CPU
readwrite
Mux
Read Bus BRead Bus A
alu_sel[0..2]
a_sel[0..2]
b_sel[0..2]
MAR
mar_sel
8
8
8
MDR
ir1_selir0_sel
r0write
ri_sel
rj_sel
rk_sel
cout, m7, v
8 8
Write Bus
r7write
Memory Address Bus
opcode
cin
IR1IR0
Clk
Clk
Clk
result_sel[0..1]
Clk
4-8 sign ext.
opcode ri
dr_enb dr_sel[0..1]
Clk
The Myth8 Processor
7/27/2019 Myth8 Processor Datapath
8/13
C U F S M D e s i g n S t r a t e g i e s : D e s i g n C o r r e c t n e s s
1 . F o r a m a j o r o p e r a t i o n ( e . g . , f e t c h & d e c o d e ) , t r a c e t h e d a t a p a t h t h r o u g h
t h e c o m p u t e r s y s t e m ( p r o c e s s o r , m e m o r y , I / O , e t c . ) n e e d e d f o r e x e c u t i n g
t h i s o p e r a t i o n .
2 . B r e a k u p t h e d a t a p a t h i n t o s u b p a t h s s . t . e a c h s u b p a t h s t a r t s f r o m a
r e g i s t e r r e a d ( e x p l i c i t o r i m p l i c i t ) , h a s a n o p t i o n a l o p e r a t i o n , a n d , e x c e p t
p o s s i b l y t h e l a s t s u b p a t h , e n d s w i t h a r e g i s t e r w r i t e .
3 . E a c h s u b p a t h n e e d s t o b e i m p l e m e n t e d b y a s i n g l e s t a t e ( c o n t r o l s i g n a l s
t o i m p l e m e n t t h e s u b p a t h a r e s e t i n t h e c o r r e s p o n d i n g s t a t e ) .
4 . A s u b p a t h i s d e p e n d e n t o n t h e d a t a p r o d u c e d a s a r e g i s t e r w r i t e i n t h e
p r e v i o u s s u b p a t h . T h i s d a t a d e p e n d e n c y i s r e e c t e d b y t h e i r c o r r e s p o n d -
i n g s t a t e s f o l l o w i n g e a c h o t h e r i n t h e s a m e o r d e r a s t h e s u b p a t h s .
Subpath nSubpath 1 Subpath 2
Register
Register
Register
Register
[operation] [operation] [operation] [operation]
Major Operation
7/27/2019 Myth8 Processor Datapath
9/13
C U F S M D e s i g n S t r a t e g i e s : D e s i g n C o r r e c t n e s s ( c o n t d . )
1 . T h e s u b p a t h d e t e r m i n a t i o n f o r t h e f e t c h - i n t o - I R 1 - & - d e c o d e a n d i n c r e -
m e n t p c=
r 7 o p e r a t i o n s i s i l l u s t r a t e d i n t h e g u r e b e l o w s u b p a t h s a r e
# ' e d i n i t a l i c s
Register File
ALU
O1
O2
O1
O2
O1
O2
O1
O2
MEMORY SYSTEM
Memory Data Bus
CPU
readwrite
dr_enb
Mux
Read Bus BRead Bus A
alu_sel[0..2]
a_sel[0..2]
b_sel[0..2]
dr_sel[0..1]
result_sel[0..1]
MAR
mar_sel
8
8
8
Memory Address Bus
MDRIR1IR0
ir1_selir0_sel
r0write
r0writeri_sel
rj_sel
rk_sel
cin
cout, m7, v
opcode
8 8
r7
r6
ANDADDA
Write Bus
Myth8 and "datapaths" for fetch-decode & increment pcDatapath for fetch (to IR1) and decode
"Datapath" for increment pc=r7
1
2
3
1
2
7/27/2019 Myth8 Processor Datapath
10/13
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7/27/2019 Myth8 Processor Datapath
11/13
C U F S M D e s i g n S t r a t e g i e s : D e s i g n E c i e n c y
1 . W h i l e s u b p a t h s o f o n e o p e r a t i o n n e e d t o b e i m p l e m e n t e d i n s e p a r a t e
s t a t e s , s u b p a t h s o f 2 o r m o r e o p e r a t i o n s ( a t m o s t o n e s u b p a t h f r o m e a c h
o p e r a t i o n ) m a y b e c o m b i n e d i n t o o n e s t a t e i f : ( a ) t h e r e i s n o d a t a d e p e n -
d e n c y b e t w e e n t h e m ( d a t a p r o d u c e d b y o n e i s n o t n e e d e d b y t h e o t h e r ) ,
a n d ( b ) t h e r e a r e n o r e s o u r c e c o n i c t s | t h e s a m e r e s o u r c e i s n o t n e e d e d
f o r m o r e t h a n o n e p u r p o s e i n a n y c l o c k c y c l e . R e s o u r c e s i n c l u d e r e g i s t e r s ,
A L U , b u s e s a n d o t h e r c o n n e c t i o n s , m e m o r y .
2 . I m p l e m e n t i n g s u b p a t h s o f d i e r e n t o p e r a t i o n s s i m u l t a n e o u s l y i n o n e s t a t e ,
s p e e d s u p t h e o v e r a l l s p e e d o v e r a l l o p e r a t i o n s a n d r e d u c e s t h e n u m b e r o f
s t a t e s r e q u i r e d i n t h e C o n t r o l U n i t .
Register File
ALU
O1
O2
O1
O2
O1
O2
O1
O2
MEMORY SYSTEM
Memory Data Bus
CPU
readwrite
dr_enb
Mux
Read Bus BRead Bus A
alu_sel[0..2]
a_sel[0..2]
b_sel[0..2]
dr_sel[0..1]
result_sel[0..1]
MAR
mar_sel
8
8
8
Memory Address Bus
MDRIR1IR0
ir1_selir0_sel
r0write
r0writeri_sel
rj_sel
rk_sel
cin
cout, m7, v
opcode
8 8
r7
r6
ANDADDA
Write Bus
Myth8 and "datapaths" for fetch-decode & increment pc
Datapath for fetch (to IR1) and decode
"Datapath" for increment pc=r7
1
2
3
1
2
7/27/2019 Myth8 Processor Datapath
12/13
C U F S M D e s i g n S t r a t e g i e s : D e s i g n E c i e n c y ( c o n t d . )
1 . I n t h e g u r e b e l o w , s u b p a t h s 1 o f f e t c h - i n t o - I R 1 - & - d e c o d e a n d i n c r e -
m e n t p c=
r 7 o p e r a t i o n s c a n b e c o m b i n e d i n t o o n e s t a t e , a s c a n s u b p a t h s
2 o f t h e s e o p e r a t i o n s | n o t e n o r e s o u r c e c o n i c t .
Register File
ALU
O1
O2
O1
O2
O1
O2
O1
O2
MEMORY SYSTEM
Memory Data Bus
CPU
readwrite
dr_enb
Mux
Read Bus BRead Bus A
alu_sel[0..2]
a_sel[0..2]
b_sel[0..2]
dr_sel[0..1]
result_sel[0..1]
MAR
mar_sel
8
8
8
Memory Address Bus
MDRIR1IR0
ir1_selir0_sel
r0write
r0writeri_sel
rj_sel
rk_sel
cin
cout, m7, v
opcode
8 8
r7
r6
ANDADDA
Write Bus
Myth8 and "datapaths" for fetch-decode & increment pcDatapath for fetch (to IR1) and decode
"Datapath" for increment pc=r7
1
2
3
1
2
7/27/2019 Myth8 Processor Datapath
13/13
P i p e l i n e d M y t h 8 P r o c e s s o r
Register File
O1
O2
O1
O2
O1
O2
O1
O2
ALUalu_sel[0..2]
cin
cout, m7, v Decode & ALU
Stage
ALU o/pregister
8Reg. fileo/p regs
MEMORY SYSTEM
Memory Data Bus
CPU
readwrite
dr_enb
Mux
a_sel[0..2]b_sel[0..2]
dr_sel[0..1]
result_sel[0..1]
MAR
mar_sel
8
8
Memory Address Bus
MDR
r0write
r0writeri_selrj_sel
rk_sel
8 8
Write Bus
Read Bus A Read Bus B
IR0IR1
ir1_sel ir0_sel
FetchCU
ReadCU
ALUCU
WriteCU
Opcode register
opcode
Fetch Stage
Decode & Read
Stage
Decode &
Write
Stage
The Myth8 Pipelined Processor