IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 3503

Accurate Compact Modeling for Sub-20-nm NANDFlash Cell Array Simulation Using the PSP Model

Jongwook Jeon, Il Han Park, Myounggon Kang, Student Member, IEEE, Wookghee Hahn,Kihwan Choi, Student Member, IEEE, Sunghee Yun, Gi-Young Yang,

Keun-Ho Lee, Young-Kwan Park, and Chilhee Chung

AbstractIn this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potentialby using PSP metal-oxide-semiconductor description. Cell-to-cellcoupling, FowlerNordheim tunneling, and new leakage currentformulas have been implemented on Verilog-A compact model.The channel potential calculation of the PSP model enablesaccurate modeling of channel coupling and leakage currentswhich are associated with the boosted channel. In addition, themodel parameter extraction procedure through 3-D technologycomputer-aided design (TCAD) and SPICE simulation is pre-sented. The simulation results agree well with measured data ofsub-20-nm NAND cells.

Index TermsCell-to-cell coupling, compact modeling,FowlerNordheim (FN) tunneling, leakage current, NAND Flash,SPICE simulation.

I. INTRODUCTION

SCALING OF Flash memory cell size reduces the marginof multithreshold voltage level, while cell-to-cell interfer-ence, which is well known as the most critical scaling barrierfor NAND Flash memories, is increased [1]. This brings anessential requirement of an accurate circuit level simulator todesign advanced multilevel memories, which can help designoptimized algorithms for program/erase (P/E) and read opera-tions [2], [3]. Although several papers about analytic modelingof Flash memory cell for SPICE simulation have been re-ported [4][8], they are mainly focusing on either basic Fowler-Nordheim (FN) tunneling during P/E operations or interferencebetween neighboring floating gates (FGs). There is a call formore thorough investigations on phenomena at a string leveland various operations with nanoscale devices. Although thebehavior of channel potential was investigated with BSIM4 in[9], the accurate calculation of channel potential and leakage

Manuscript received May 1, 2012; revised June 28, 2012 and August 13,2012; accepted September 4, 2012. Date of publication October 24, 2012; dateof current version November 16, 2012. This work was supported by SamsungElectronics Company, Ltd. The review of this paper was arranged by EditorY.-H. Shih.

J. Jeon, S. Yun, G.-Y. Yang, K.-H. Lee, Y.-K. Park, and C. Chung are withSemiconductor R&D Center, Device Solutions Business, Samsung ElectronicsCompany, Ltd., Hwaseong 445-701, Korea (e-mail: voix0707@naver.com;sunghee.yun@samsung.com; giyoung.yang@samsung.com; keunho.lee@samsung.com; youngpark@samsung.com; chungc@samsung.com).

I. H. Park, M. Kang, W. Hahn, and K. Choi are with the Flash DesignTeam, Memory Division, Device Solutions Business, Samsung ElectronicsCompany, Ltd., Hwaseong 445-701, Korea (e-mail: ilhan.park@samsung.com;kang77@snu.ac.kr; wg.hahn@samsung.com; kihwan.choi@samsung.com).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2012.2219863

current models of boosted channel are not available becauseBSIM4 is a threshold-voltage-based model.

In this work, we have developed a channel-potential-basedaccurate FG Flash cell compact model with sub-20-nm NANDcell strings. To model a Flash cell, a surface-potential-basedmodel is much more appropriate than a threshold-voltage-basedmodel because boosted channel potential can be defined. Thesurface-potential-based model can also be used to model the ca-pacitive coupling and leakage currents accurately. To describethe boosted channel potential, we have adopted PSP metal-oxide-semiconductor (MOS) description, which is a surface-potential-based model [10]. We have developed cell-to-cellcoupling, FN tunneling current, and leakage current modelsbased on the channel potential approach, and they are imple-mented into Verilog-A. Precise leakage models related with theboosted channel are proposed from the results of device leveltechnology computer-aided design (TCAD) simulation. TCADsimulation is also used to calculate FG coupling and channelboosting ratio. The model parameters are extracted from themeasurement of a sub-20-nm Flash cell array, and the predictedresults show good agreement with the measured array behav-iors. In addition, the extraction procedure of the parameters ispresented. The developed model accurately describes both dcand transient behavior of a NAND Flash array.

II. COMPACT MODELING OF A FLASH CELL

Fig. 1 shows the NAND Flash array used for developing thecompact model. Sixty-four NAND Flash cells are connectedin a string (WL0WL63) with two dummy cells (Dummy0and Dummy1), one ground select line (GSL), and one stringselect line (SSL). CSL means common source line bias, andPPW means pocket p-well bias. The simulated NAND Flasharray is composed of three identical strings, and the centeris the one to be analyzed, whereas the two side strings areaggressors to describe capacitive coupling effects on the mainstring. The memory cell is the FG type, and it is described asMOS transistors with a stacked ONO capacitor CONO in seriesto the FG terminal as shown in Fig. 1. Word-line (WL) bias isapplied to the control gate (CG). In addition, the P/E currentsource is attached between the body and the FG.

A. Capacitive Coupling

The capacitive coupling in Flash cells is shown inFig. 2(a)(c). Coupling capacitance components are mainlyseparated into two categories, which are related with

0018-9383/$31.00 2012 IEEE

3504 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 1. Schematic of a NAND Flash array. Sixty-four cells are organized in asingle string. Three identical strings form a basic NAND Flash array.

Fig. 2. Cell-to-cell capacitance coupling considered in this work: (a) Alongthe BL direction, (b) along the WL direction, and (c) along the diagonaldirection.

the FG and the channel potentials. In this paper, FG-related components, i.e., CONO, CCGFG(WL), CFGFG(BL),CFGFG(WL), and CFGFG(Diag), are calculated by the 3-DTCAD simulations. The amount of charge variations inFG of the victim (QFG_VICTIM) cell is measured bythe changes in the bias of the aggressors (VAGG_NODE).Then, coupling capacitance (CCOUP) can be calculated

as CCOUP = QFG_VICTIM/VAGG_NODE. The channel-related components, CCG-CH(WL), CFG-CH(WL), CFG-CH(BL),CCH-CH(BL), and CFG-CH(Diag), are modeled as follows. Theinfluence of channel coupling is implemented by calculatingthe channel potential variation associated with the potentialvariations of CG, FG, and channel of adjacent cells, instead ofadding direct coupling capacitance. The reason is that channelnode is defined as an output node only. The channel potentialvariation can be quantified by formulating the effective gatevoltage. In sub-20-nm technology, the short-channel effectsshould be carefully considered. The PSP model provides nec-essary parameters describing the short-channel effects suchas velocity saturation, DIBL, channel length modulation, andmobility degradation [11]. These effects are automatically takeninto account in the calculation of the surface potential of thedrain side (D). The channel potential (VCH) is defined as themidchannel surface potential VCH = (S + D)/2, where Sis the surface potential of the source side. The effective gate-to-body voltage (V GB) due to the channel potential variation isformulated as

V GB=VGS + VSB +VG VFB +VG_coup1 +VG_coup2

+VG_coup3 +VG_coup4 +VG_coup5 +VG_coup6 (1)

where VGS is the FG bias, VG is the effect of drain-induced barrier lowering (DIBL), and VFB is the flatbandvoltage. The channel potential variation is modeled by usingVG_coup1, VG_coup2, VG_coup3, VG_coup4, VG_coup5,and VG_coup6 which are defined as

VG_coup1 =COUPWG VCG(Adj.WL) (2)VG_coup2 =COUPWF VFG(Adj.WL) (3)VG_coup3 =COUPBG VCG(Adj.BL) (4)VG_coup4 =COUPBF VFG(Adj.BL) (5)VG_coup5 =COUPBC VCH(Adj.BL) (6)VG_coup6 =COUPDF VFG(Adj.Diag.) (7)

where VFG(Adj,BL), VFG(Adj,WL), and VFG(Adj,Diag.) mean theFG potentials of adjacent bit line (BL), WL, and diagonal,respectively. VCG(Adj,BL) and VCG(Adj,WL) mean the CG po-tentials of adjacent BL and WL, respectively. VCH(Adj,BL)means the channel potential of adjacent BL. COUPBF, theadjacent COUPWF, and COUPDF represent the couplingeffects of FG along the BL, WL, and diagonal directions,respectively. COUPBG and COUPWG represent the couplingeffects of the adjacent CG along the BL and WL directions,respectively. COUPBC represents the coupling effect of theadjacent channel along the BL direction.

B. FN Tunneling Currents

To model the change of the FG charge during P/E, the FNtunneling mechanism [12] is used

IFN = AREA E2TUN exp(/ETUN) (8)

JEON et al.: ACCURATE COMPACT MODELING FOR NAND FLASH CELL ARRAY SIMULATION 3505

Fig. 3. Three-dimensional TCAD simulation results of two leakage currentmechanisms (BTBT and II) for EEE and PEP patterns.

where and are optimized parameters, AREA is the tunnelFN injection area, and ETUN is the electric field through theoxide. Note that ETUN is accurately calculated by using thechannel potential as in ETUN = (V GB VFB VCH)/TOX.

C. Leakage Currents

Based on the different mechanism, the leakage current in aNAND Flash array can be separated into junction leakage andGIDL current. The junction leakage current occurs in narrowdepletion region when there is a large potential differencebetween the channel and the body, and it is modeled with band-to-band tunneling (BTBT) and impact ionization (II) compo-nents. The junction leakage current is dependent on the stateof the neighbor channels of the side strings (programmed orinhibited). Fig. 3 shows the 3D-TCAD simulation results ofBTBT and II leakage currents in EEE and PEP patterns whereE means inhibited string and P is programmed string. Thedominant leakage mechanism is different in the two cases dueto the boosted channel potential level and the depletion width.BTBT and II models are transformed by using the advanceddiode model (level500) [13]

Iii_CHS

=

{0 for VCS0ZAVCS Irev exp

( ZBVCS

)for VCS>0

(9)

Ibtbt_CHB

=

0 for VCB0BT1(

BT2WdepVCB

)1.5exp

(BT2Wdep

VCB

) for VCB>0 (10)

Fig. 4. Experimental conditions to observe GIDL current properties of GSL.

Fig. 5. Definition of the index of boosting potential Vboost.

Iii_CHB

=

{0 for VCB0ZCZD

VCBWdep

Irev exp(ZDWdepVCB

)for VCB>0

(11)

where Wdep is the depletion width, Wdep = (2 Si VCB/qNeff)

1/2, Irev is the reverse bias saturation current,Irev = 7.13 1013[A], VCB is the reverse bias between thechannel and the body, and VCS is the reverse bias between thechannel and the source. BT1, BT2, ZA,ZB,ZC, and ZDare optimized parameters. Iii_CHS is the II current flowingthrough channel to source which is caused by the reverse biasbetween boosted channel and low potential source as shownin Fig. 3(b). High-electric-field-dependent leakage currentsbetween channel and body are modeled with Ibtbt_CH andIiiCHB taking pattern dependence into account as shown inFig. 3(c) and (d). In PSP model, the GIDL current model iscalculated in a single MOSFET by using the gatedrain overlap(VOV) and the drainbody (VDB) voltage [14]. However,GIDL current model should be reexamined in NAND Flasharray circumstance because the adjacent cells and strings affectthe GIDL current behavior. The indirect approach is used tocharacterize GIDL current by adopting the index of boostingpotential Vboost in this work. Fig. 4 shows the experimentalsetup to observe GIDL current properties in NAND cell arraywhere incremental-step-pulse programming (ISPP) is used toprogram. Vboost is defined as the threshold voltage differenceof the cells (WL32) between programmed and inhibitedstrings as shown in Fig. 5. Vboost will be dropped when theleakage currents flow out of the boosted channel region. Vboostdecreases as VGSL is set lower than the threshold voltage ofGSL as shown in Fig. 6(a) and (b), and it is the evidence of theexistence of GIDL current of GSL. The pattern and adjacentcell voltage dependences are observed in Fig. 6(a) and (b),respectively. This GIDL current dependence of neighbor cells

3506 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 6. Measured Vboost in experiments of Fig. 4. (a) Pattern and (b) adjacentcell dependences on GIDL current are observed.

along BL and WL directions is also observed in GIDL currentof the cell region. Based on this investigation, it is deducedthat, when calculating GIDL current, neighbor cells should betaken into account. The new GIDL current model is proposedas follows. To develop GIDL current model, the BTBT modelof the uniform electric field limit by Kane and Keldysh wasused [15]. GIDL current model of the PSP is also based on thismodel [11].

GIDL current based on [15] is expressed as

JGIDL E2tov exp (BGIDL/Etov) (12)

where BGIDL is a physical parameter which is dependent on thedirect/indirect tunneling and the effective mobility. The valueof BGIDL is 1.9 107 [V cm1] [16]. Etov is the maximumelectric field at the Si/SiO2 interface in the drain overlap region.Etov consists of a dominant vertical component of victim andneighbor cells and a lateral component which is proportionalto VDB and VSB. While only VDB is considered in PSP model,the effect of VSB on GIDL current is also taken into accountbecause the lateral field is comparable to the vertical field atthe point of the GIDL current occurrence [17]. Thus, Etovis calculated as (15) shown at the bottom of the page whereCGIDL, DGIDL, EGIDL, and FGIDL are empirical parameters.COX is the gate oxide capacitance per unit area. Using (12) and(15), the GIDL current becomes

IGIDL = AGIDL V 2tov exp(BGIDL

Vtov

)(16)

where AGIDL=(WLovCox/Si)2 and BGIDL=SiBGIDL/Cox.The values of AGIDL and BGIDL can be modulated to themeasured data to optimize the magnitude and the gate voltagedependence of the GIDL current, respectively. As three addi-

Fig. 7. Extraction procedure diagram of model parameter.

tional terminals of VOV(WL), VOV(BL), and VSB are introduced,new GIDL current parameters of DGIDL, EGIDL, and FGIDLare adopted. If DGIDL, EGIDL, and FGIDL parameters are setto zero, GIDL model (16) becomes the same as that in the PSPmodel [14].

III. PARAMETER EXTRACTION AND RESULTS

The model parameter extraction procedure is shown in Fig. 7.To obtain the model parameters, we have used cell array ofreal NAND Flash circumstance as depicted in Section II. Pat-tern initialization means that the initial status of the victimcells FG node is set to initial status of measurements, andit is performed by injecting some amount of charge into FGnode. Before starting parameter extraction, physical processparameters of channel length/width, overlap length, dopingconcentration of body and gate poly, and oxide thickness areset into the PSP model. As mentioned in Section II, FG-related coupling capacitances are obtained from well-calibrated3-D TCAD simulation. The optimized PSP model parametersets are obtained from measured dc data by using the geneticalgorithm with the array simulation [18]. When measuring the

Evertical =QSSi

COXSi

(VOV(VIC) + EGIDLVOV(WL) + FGIDLVOV(BL)

)(13)

Elateral =CGIDLVDB DGIDLVSB (14)

Etov =COXSi

(VOV(VIC) + EGIDLVOV(WL) + FGIDLVOV(BL)

)2+ (CGIDLVDB DGIDLVSB)2

=COXSi

Vtov (15)

JEON et al.: ACCURATE COMPACT MODELING FOR NAND FLASH CELL ARRAY SIMULATION 3507

Fig. 8. Transfer curve of main cell in which symbols are measured and linesare simulated data. Insets are plotted in linear scale.

dc characteristics of the NAND array, the pass bias (Vpass)should be large enough to turn on the cell transistors in allcell patterns. The parameters for channel coupling capacitances(COUPWG, COUPWF, COUPBG, COUPBF, COUPBC,and COUPDF) are extracted in sequence. These parametersare extracted from the cell-to-cell coupling measurements.The channel coupling parameters are extracted for variousinitial Vths of the victim cell. The magnitude of interferencefrom each direction is dominantly determined by FG-to-CHand CG-to-CH coupling parameters of COUPWF, COUPBF,COUPDF, COUPWG, and COUPBG. The dependence ofBL interference on initial Vth of the victim cell is modeledby CH-to-CH coupling parameter COUPBC. One iterativeprocess is required between dc and channel coupling modelingbecause they are related interdependently. The model param-eters of FN tunneling current ( and ) are extracted fromthe measurement of program and erase speeds. The junctioncapacitance (Cjunc) and outer fringe capacitance (Cof) shouldbe considered to acquire accurate boosting channel potential.From 3-D TCAD simulation, the boosting channel potential canbe plotted versus VFG. Cjunc and Cof and these two capaci-tances are fitted to the 3-D TCAD simulation result. Note thatthe leakage components in 3-D TCAD simulation are turnedoff to confirm the only effect of parasitic capacitances on theboosting ratio. The next step is an extraction of the leakagecurrent parameters. ZA and ZB are extracted from the result ofEEE pattern in which the II between boosted channel and low-potential-source region is the dominant leakage mechanism.BT1, BT2, ZC, and ZD are obtained from the results of PEPand PEE patterns. The GIDL current parameters of AGIDL,BGIDL, CGIDL, DGIDL, EGIDL, and FGIDL are obtained frompattern and adjacent cell (Dummy0 for GSL-GIDL and WL31for cell-GIDL) dependences. DGIDL, EGIDL, and FGIDL areoptimized with the effects of VSB (VCSL), adjacent WL cells,and adjacent BL cells, respectively. In order to extract the modelparameter of the junction leakage current, GIDL current shouldbe suppressed by biasing lower Vpass voltage to the adjacentcells. By biasing lower Vpass voltage to VDUM0 and VWL0, thefield crowding between GSL and Dummy0 can be eliminated;as a result, GSL-GIDL current is suppressed. Before extractingthe model parameter related to the GIDL current, the modelparameters related to the junction leakage current are extracted.Note that the coupling and the leakage current models should beconsidered in the two side strings as well as in the center string.Fig. 8 shows the results of dc transfer curve simulation where

Fig. 9. (a) Experiments of cell-to-cell interference and (b) modeling resultsfor various initial victim states.

Fig. 10. Program speed where the FN tunneling current model is verified.

BL current is plotted versus WL32 voltage for various bodybiases (VPPW), in which Vpass is biased at other WL cells andGSL/SSL is turned on. Fig. 9(a) shows cell-to-cell interferencewhich is equivalent to Vth shift of a victim cell as those ofadjacent cell (aggressors) change where P1 and P3 represent thestates of Vth = 0 V and 4 V, respectively. The proposed channelcoupling model shows good agreement with the measureddata in Fig. 9(b). In addition, the channel coupling effect isclearly described in this figure. The model without channelcoupling effect cannot predict the interference behaviors forvarious initial victim states. This is why the surface-potential-based compact model is needed for sub-20-nm NAND Flash cellmodeling. By extracting the FN parameters ( and ) proposedin Section II-B, the program speed for various VPGMs is wellpredicted as shown in Fig. 10. The proposed junction leakageand GSL-GIDL current models show good agreement withthe measured Vboost data in Figs. 11 and 12, respectively.Note that the table in Fig. 11 shows the experimental setup tomeasure the junction leakage current with suppressing GIDLcurrent as mentioned before. As VGSL decreases, GIDL currentincreases, and then, the boosted channel potential decreases.As a result, the junction leakage current is decreased due tothe reduced boosted channel potential. It is explained that theVboost drops and saturates when decreasing VGSL as shown inFig. 12. Fig. 13 shows the measurement conditions under thecell-GIDL current. Fig. 14 shows the results of the cell-GIDLmodel. It is verified that the proposed leakage current modelsreflect well for various patterns and neighbor cell effects inFigs. 1113. The comparison between the proposed model andthe measured Vth versus ISPP for various patterns is shown in

3508 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 11. Pattern dependence of Vboost under junction leakage current flow.

Fig. 12. (a) Pattern and (b) adjacent cell (Dummy0) dependences of Vboostunder the GSL-GIDL leakage current flow.

Fig. 13. Experimental conditions to observe GIDL current properties of cellregion.

Fig. 14. (a) Pattern and (b) adjacent cell (WL31) dependences of Vboostunder the cell-GIDL current flow.

Fig. 15. Since this disturb behavior is strongly dependent oncell-to-cell coupling, FN tunneling, and leakage currents, it isconfirmed that the proposed models are accurately developedto predict Flash cell array characteristics. When simulating theprogram operation in the full NAND array (3 64 cells), the

Fig. 15. Disturb simulation results for various patterns.

total CPU time is approximately 1200 s (ISPP from 13 to20.2 V with 0.3-V step). The total CPU time for simulation isdependent on the operation types of the NAND Flash array.

IV. CONCLUSION

In this paper, we have investigated the compact modeling forNAND Flash array simulation in which the surface-potential-based PSP model was used. In NAND Flash strings, the modelsof cell-to-cell coupling, junction leakage, and GIDL currentare proposed from the analysis of 3-D TCAD simulationand measured data. In addition, we presented the procedureof model parameter extraction which allows extracting exactmodel parameter sets. The modeling results were verified withthe measured data, and good agreement was observed. Thedeveloped model allows accurately predicting the dc and tran-sient properties of sub-20-nm NAND Flash cell array includingdisturb behavior. Thus, it can be used to develop optimizedalgorithms and to examine fail mechanisms.

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Jongwook Jeon received the Ph.D. degree from theDepartment of Electrical Engineering, Seoul Na-tional University, Seoul, Korea.

He is currently with Semiconductor R&D Cen-ter, Device Solutions Business, Samsung ElectronicsCompany, Ltd., Hwaseong, Korea.

Il Han Park received the Ph.D. degree in electricalengineering from Seoul National University, Seoul,Korea.

He is currently with Flash Design Team, MemoryDivision, Device Solutions Business, Samsung Elec-tronics Company, Ltd., Hwaseong, Korea.

Myounggon Kang (S10) received the Ph.D. degreefrom Seoul National University, Seoul, Korea.

He is currently with Flash Design Team, MemoryDivision, Device Solutions Business, Samsung Elec-tronics Company, Ltd., Hwaseong, Korea.

Wookghee Hahn received the M.S. degree in electri-cal engineering from Korea University, Seoul, Korea.

He is currently with the Flash Design Team, Mem-ory Division, Device Solutions Business, SamsungElectronics Company, Ltd., Hwaseong, Korea.

Kihwan Choi (S01) received the Ph.D. degree fromthe University of Southern California, Los Angeles,in 2005.

He is currently with the Flash Design Team, Mem-ory Division, Device Solutions Business, SamsungElectronics Company, Ltd., Hwaseong, Korea.

Sunghee Yun received the M.S. and Ph.D. degreesfrom Stanford University, Stanford, CA, in 2000 and2004, respectively.

Since 2004, he has been with Semiconductor R&DCenter, Device Solutions Business, Samsung Elec-tronics Company, Ltd., Hwaseong, Korea.

Gi-Young Yang received the Ph.D. degree from theKorea Advanced Institute of Science and Technol-ogy, Daejeon, Korea.

He is currently with Semiconductor R&D Cen-ter, Device Solutions Business, Samsung ElectronicsCompany, Ltd., Hwaseong, Korea.

Keun-Ho Lee received the Ph.D. degree from theKorea Advanced Institute of Science and Technol-ogy, Daejeon, Korea.

He is currently with TCAD group, SemiconductorR&D Center, Device Solutions Business, SamsungElectronics Company, Ltd., Hwaseong, Korea.

Young-Kwan Park received the M.S. degree fromSamsung Semiconductor Institute of Technology,Yongin, Korea.

He is currently the Vice President of CAE team,Samsung Electronics Company, Ltd., Hwaseong,Korea.

Chilhee Chung received the Ph.D. degree fromMichigan State University, East Lansing, Michigan.

He is currently the Executive Vice Presidentof the Semiconductor R&D Center, Device Solu-tions Business, Samsung Electronics Company, Ltd.,Hwaseong, Korea.