Nanoscale Resistive Memory (Memristor) Based on Amorphous ... · •Both 0 and 1 can have a...

1

Wei Lu

University of Michigan Electrical Engineering and Computer

Science

Resistive Memories Based on Amorphous

Films

Crossbar Inc

Lu Group EECS, UM 2

Introduction

Hysteretic resistive switches and crossbar structures

– Simple structure

• Formed by two-terminal devices

• Not limited by transistor scaling

– Ultra-high density

• NAND-like layout, cell size 4F2

• Terabit potential

– Large connectivity

– Memory, logic/neuromorphic applications crossbar Structure

single-cell structure

Lu Group EECS, UM 3

ITRS_ERD workshop, April 2010

Resistive Switching Memory

Lu Group EECS, UM 4

• Switching type: bipolar

• Electric field-driven redox

chemical effect

• Metal filament formation

• Electrode plays active role

(Ag or Cu)

• Materials: chalcogenides (e.g. GeS, GeSe, …), other amorphous films (e.g. oxides, a-Si, a-C, …)

RRAM – ECM Cell

Schindler et al., Proc. IEEE Non-volatile Memory Technology Symp. 82, 2007.

ElectroChemical Metallization Cell Ag/Ag-Ge-Se/Pt

Lu Group EECS, UM 5

•Ag/SiO2/Pt structure, sputtered SiO2 film •The filament grows from the IE backwards toward the AE •Branched structures were observed with wider branches pointing to the AE •Single filament dominates

ECM: Visualization of Filament

Partially formed filaments Completed filament

+ -

-

Ag

Pt

200nm

Yang, Gao, Chang, Gaba, Pan, and W. Lu, Nature Communications, 3, 732, 2012.

Lu Group EECS, UM 6

Before erasing After erasing

Pt

Ag

Pt

Ag

Ag/SiO2/Pt structure

Visualization of Filament, TEM

•A single filament dominates the switching process


Lu Group EECS, UM 7

Compositional Analysis of the filament

The filament was verified to be composed of elemental fcc Ag particles (i.e. not Ag ions or oxides) Thin Ag filaments are not stable and naturally break into discrete Ag particles High conductance can be maintained when the particles are closely spaced


Ag filament in SiO2

Lu Group EECS, UM 8

HRTEM, showing the particles are (111) Ag with fcc structure

Ag particles forming the filament

2 nm

• The filament was verified to be composed of elemental fcc Ag particles

• Thin Ag filaments are not stable and naturally break into discrete Ag particles

Compositional Analysis of the filament


Ag filament in a-Si

Lu Group EECS, UM 9

Visualization of Ag Filament, in-situ TEM

c d e f gAg Ag Ag Ag Ag

W W W W W

+ + + + +

- - - - -

W

a-Si

Ag

a b

Cu

rre

nt

(μA

)

c d e

g

f

0 100 200 300 400 500

Time (s)

0.0

0.5

1.0

1.5

2.0

2.5

20nm 20nm 20nm 20nm

100nm

Yang, et al. Nature Communications, 3, 732, 2012.

c d e f gAg Ag Ag Ag Ag

W W W W W

+ + + + +

- - - - -

W

a-Si

Ag

a b

Cu

rre

nt

(μA

)

c d e

g

f

0 100 200 300 400 500

Time (s)

0.0

0.5

1.0

1.5

2.0

2.5

20nm 20nm 20nm 20nm 20nm

100nm

Bulk RRAM on W probe Ag +

W -

Lu Group EECS, UM 10

Pillar structure

a-Si RRAM Crossbar Structure

•Two terminal resistance switching device

•Ag inside a-Si matrix

•Small cell size, < 50 nmx50 nm (density > 1010/cm2)

•CMOS compatible materials and processes

Jo et al. Nano Lett., 8, 392 (2008)

Crossbar array

Kim, Jo, W. Lu, Appl. Phys. Lett. 96, 053106 (2010)


Resistance Switching Characteristics

Kim, Jo, W. Lu, Appl. Phys. Lett. 96, 053106 (2010) Jo, Kim, W. Lu, Nano Lett., 8, 392 (2008) 0 200 400 600 800 1000 1200

0

50

-3

-2

-1

0

1

Volta

ge

(V)

Time (ns)

Curr

ent(n

A) on on off

read1 read2 read3-2V -3.5V

-4 -2 0 2 4 6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Voltag e (V )

Curr

ent(

100

nA)

6-4 -2 0 2 4

10-12

Voltage(V)

10-6

10-7

10-8

10-9

10-10

10-11

Ag

Pt

IREAD

Sneak path

involves one

reverse-biased

cell


> 1e8 W/E endurance 1e6 on/off Can be switched within 50ns

Write/Read/Erase/Read pulse : 50nsec ,5V /50usec, 0.7V /100nsec, -3.5V /50usec, 0.7V

on off on off

Endurance and Speed

Kim et al, Appl. Phys. Lett. 96, 053106 (2010) Jo et al. Nano Lett., 8, 392 (2008)

-2 -1 0 1 2 3

10-14

10-12

10-10

10-8

Cu

rre

nt

(A)

Bias (V)

Virgin

106

107

108

100

101

102

103

104

105

106

107

108

0

10

20

30

40

50

Me

asu

red

Cu

rre

nt

(nA

)

Endurance Cycle

0 100 200 300 400

0.0

0.1

0.2

0.3

0.4

0.5

Ou

tpu

t (V

)Time (uS)

Endurance Cycles 104, 10

5

106, 10

7


• up to 8 levels (3 bits) per cell demonstrated

• cell resistance controlled by the current-limiting control resistor

Multi-Level Storage

Jo et al. Nano Lett. 9, 496-500 (2009).

Kim et al, Appl. Phys. Lett. 96, 053106 (2010)


Integrated Crossbar Array/CMOS System

Kim, Gaba, Wheeler, Cruz-Albrecht, Srivinara, W. Lu Nano Lett., 12, 389–395 (2012).

CMOS

Crossbar

array

500nm

•Low-temperature process, RRAM array fabricated on top of CMOS •CMOS provides address mux/demux •RRAM array: 100nm pitch, 50nm linewidth with density of 10Gbits/cm2

•CMOS units – larger but fewer units needed. 2n CMOS cells control n2 memory cells

“1R” array, no

external

selectors or

diodes


East

Data A

East Address

Decoder

East

Data B

East

Address <1>

East

Address <n>

Pad

Via between nanowire and CMOS

CMOS chip I/O terminal Pad

Switch 1

Switch 2

Switch N

N n

South Connections

North Connections

West C

on

ne

ction

s

via




I-V of the integrated Crossbar/CMOS system

Threshold voltage (V)

•Tight distribution from 256 devices measured •Devices shown good on/off and intrinsic diode characteristics


Average 2.30 V Stan. dev. 0.07 V



- Crossbar array operation, array written followed by read - Programming and reading through integrated CMOS address decoders - Each bit written with a single 3.5V, 100us pulse

Results from a 40x40 crossbar array integrated on CMOS


Stored/retrieved array 1 Stored/retrieved array 2



1 and 0 states are clearly distinguishable from the 1600 cells in the crossbar

Target Ron = 500k


Kim et al. Nano Lett., 12, 389–395 (2012).

0

50

100

150

200

50K 100K 500K 1M 5M 10M 50M 100M 500M

50K 100K 500K 1M 5M 10M 50M 100M 500M

# in

bin

s Original

0

50

100

150

200

# in

bin

s

Complementary


Multi-Level Storage

•Different on-states can be obtained by changing Rs •Tight resistance distribution can still be obtained for multi-level storage

Kim et al. Nano Lett., 12, 389–395 (2012).


Crossbar Inc - Startup company founded in 2010 to fabricate a-Si

based RRAM in commercial fab.

Fully VC-funded, Silicon Valley HQ

CMOS compatible process with superior proven performance

Currently has ~ 20 full-time staffs

From Lab to Fab

• CMOS Compatible

• 3D Stackable, Scalable Architecture – Low thermal budget process

• Architectures proven include multiple Via schemes and Subtractive etching

Crossbar Inc’s non-volatile memory

technology RRAM array fabricated on 8”

wafers in a commercial fab


2

24

22

4

2

2/12/1

22)(2

eVm

h

lweVm

h

lw

eeV

eeV

lwh

eAI

I-V equation, tunneling through a barrier with thickness of w-l with barrier height

l is the length of the filament, determined by Eq. 2

lw

EV

lw

EV

eed

dt

dl00 //

0

de

kTE

20 d is the step length of the filament

(1)

(2)

Model Development

aS VRIV

The voltage across the device V is related to I and applied voltage Va

(3)

vvwGi ),(

),( vwfw

First order model: Two equations describing switching behavior w: state variable

P. Sheridan, K. Kim, W. Lu, Nanoscale 3, 3833 (2011).

RS

RRAM

Series resistor

w-l

Va

E=aV


Rs= 500kOhm

Filament length vs. applied voltage

Device current vs. applied voltage

Device voltage vs. applied voltage

SPICE Model – DC Sweep

•Direct SPICE simulation to predict RRAM switching dynamics.

•Threshold effect, multi-level, exponential dependence of switching time on voltage

captured



SPICE Model, Transient Effects

write

read

SET

SET

•RRAM switching transient effects captured in SPICE



Redox Memory – Valency Change Cell

• Materials: TiO2, HfO2, TaOx ...

• Switching type: bipolar

• Electric field-driven redox chemical effect

• Oxygen exchange between two pre-defined oxide layers

• “bulk” effect or filament effect

• On/off, uniformity

Oxide layer 1 “switching” layer

Oxide layer 2 “base” layer

“0” “1”


Valency-Change Devices Based on TaOx

Y. Yang, P. Sheridan, W. Lu, App. Phys. Lett. 100, 203112 (2012)

Bipolar switching


IREAD

Sneak path problem in passive Crossbar arrays

asymmetric

Possible device type 1

Vread-½ Vread

symmetric

½ Vread

Possible device type 2

-½ VreadVread

Valency-Change Devices Based on TaOx


Complementary Resistive Cell based on TaOx

•Internal distribution of VO can be used to represent the cell state

•Both 0 and 1 can have a high-resistive layer and are of high resistance at low bias

•All 4 states need to be accessed during CRS operation

Y. Yang, P. Sheridan, and W. Lu, Appl. Phys. Lett. 100, 203112 (2012)

CRS switching

Read “0”

Read “1”


Acknowledgements

*Sung-Hyun Jo, *Kuk-Hwan Kim

Siddharth Gaba, *Ting Chang

Patrick Sheridan, ShinHyun Choi

Jiantao Zhou, Chao Du, Jihang

Lee, Wen Ma, *Eric Dattoli

Wayne Fung, Lin Chen

*Seok-Youl Choi, *Woo Hyung Lee

Grad students:

•National Science Foundation (ECS-0601478, CCF-0621823, ECCS-0804863, CNS-0949667, CAREER ECCS-0954621). •DARPA SyNAPSE program •DARPA UPSIDE program •Air Force MURI program, Air Force q-2DEG program, Engineering Translational Research (ETR) Grant Dr. L. Liu

*Xiaojie Hao

PostDocs:

* Dr. Qing Wan

Visiting scholars:

*Dr. Zhongqing Ji

* alumni

Dr. Yuchao Yang Funding:

Collaborators:

•Dr. N. Srinivasa, Dr. D. Wheeler, Dr. T. Hussain. Dr. J. Cruz-Albrecht, HRL Labs, •Prof. Z. Zhang, Prof. P. Mazumder, Prof. M. Zochowski, UM, •Prof. D. Strukov, UCSB, •Prof. J. Hasler, GeorgiaTech, •Prof. G. Guo, Prof. T. Tu, USTC, China •Prof. R. Li, CAS, China

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Nanoscale Resistive Memory (Memristor) Based on Amorphous ... · •Both 0 and 1 can have a...

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