5.3. Power supplies .................................................................................. 26 5.4. Internal and External Pads (“Connectors”) ......................................... 27 5.5. Board View ........................................................................................ 30 5.6. Support for IMX6ULL ......................................................................... 32
6. Building carrier board pattern for hosting nanoSOM™ NS01 .............. 33 6.1 One Important addition for internal pads ............................................. 36 6.2 Some specific signals ......................................................................... 38 6.3 Using FRAM with nanoSOMTM ............................................................ 40 6.4 Using TPM module with nanoSOMTM .................................................. 41
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1. Introduction
This document is hardware presentation of nanoSOM™ NS01.
The document can help user quickly understand module interface specifications, electrical and mechanical details.
nanoSOM™ NS01 is member of EXOR’s nanoSOM™ family, very small, but powerful PCB
board, without connectors.
Practically, user can consider nanoSOM™ (NS01) as “a component”, which can be
soldered directly in users, custom carrier board.
nanoSOM™ NS01 is based at IMX6UL processor (package 9 mm x 9 mm) and full
features, described in this document, suppose using this processor. In addition to IMX6UL, nanoSOM™ NS01 can support also IMX6ULL processor with
some reduced features.
See in chapter 5.6 for details.
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2. nanoSOM™ technology
nanoSOM™ is one ultra-compact SOM, that introduces new connection, technical
similar to chip scale package of IC, that allows soldering to the main carrier board the same way as other IC SMD components.
nanoSOM™ adapts connection technique Flat no-leads packages with external 131
contacts 0,7mm QFN (quad-flat no-leads). It is a surface-mount technology that connect ICs to the surfaces of PCB without through-holes and without expensive
connectors. nanoSOM™ NS01, adds also 28 + 10 contacts (pads) more (named internal
contacts).
Pads at package at bottom side provide electrical connections to external PCB (named
carrier board).
The nanoSOM™ has very compact size (see drawing below) and is not invasive in the
design of the carrier board. The nanoSOM™ has specially thickness of only 2.2 mm max,
almost like the normal IC package, allowing user to create industrial products with very compact and incredible thin profile.
Carrier boardNano SOM with
on board parts
2.2 mm total
nano SOM
module
thickness
Block diagram of nanoSOM™ NS01 is presented below.
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3. Dimensions
23.50
23
.50
25
.40
25.40
Drawing above shows dimension of nanoSOM™ NS01. Dimensions are in mm.
4. Pin out
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Bottom Edge
nanoSOM Top view
Top Edge
Le
ft E
dg
e
Rig
ht E
dg
e
Origin
1
34
3
34 34
341
nanoSOM Rear viewOrigin
4
Le
ft
(View “through” board)
Rig
ht
Top1 1
4 4
1 20
Tamper 8
Tamper 2
Tamper 3
Tamper 7
Tamper 9
Tamper 5
Tamper 0
Tamper 4
Tamper 6
Tamper 1
Picture above shows TOP side view (side of components) and BOTTOM side. Although also BOTTOM side contains components, there are much more components at TOP side.
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BOTTOM side contains mainly some capacitor filters and some minor components, which
due to various reasons, must be located at bottom side.
Note that carrier board for supporting nanoSOM™ NS01 must have HOLE in
central board area.
See below:
nanoSOM NS01
Carrier for nanoSOM Carrier for nanoSOM
Top side of
nanoSOM
Bottom
side of
nanoSOM
Hole in carrier
board
Solder Pads Solder Pads
.
nanoSOM™ NS01 is built around:
Four external (edge)”connectors” (total 131 pins).
Three internal (edge) “connectors” (total 28 pins)
Ten rounded pins for connecting to Tamper pins of CPU at bottom side
Really, these “connectors” are not true connectors, but simple soldering PADS,
with pitch 0.7mm for external and 1mm for internal pads.
Due to intentionally asymmetric shape (TOP LEFT angle is inclined), some pins are “lost”
to have 4x34 =136 pins, so total number of external pins is 131 pins (31 + 32 + 34 +
There are also ten rounded pads connected to Tamper pins 0-9 of CPU.
Note that these pins (tamper pins) are located in one “protected“ area (out of HOLE).
After soldering nanoSOM to carrier, these pins will be “invisible”.
Next chapters shows all pins, located at external and internal “connectors”.
Note that nearly all pins of IMX6UL have more functions. In order to build schematic and PCB, it is selected one default pin mapping, which in the best way covers most of Exor’s
needs. User can select some other using-pin out (for example to have more UARTS, less
SPI, to have Camera input and other combinations). Of course, this change must be followed by support in firmware and BSP. User can change this default pin out, using
PINMUX tool by Freescale and one must be familiar with this, in case of changing.
Some signals (have name GPIO in column) are true GPIO, without some special using.
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All signals can be used also as simple GPIO.
All signals are direct LVCMOS/LVTTL (+3V3) compatible (of course expect
special like USB pairs for example).
4.1. Left connector external
Pin Signal Name Type IMX6UL (Pin name) Pin Comment
3 +3V3S Supply
Supply +3V3, 5%
4 +3V3S Supply
5 +3V3S Supply
6 +3V3S Supply
7 +3V3S Supply
8 GND
9 SCL UART2_TX_D L16 I2C main channel
10 SDA UART2_RX_D K16
11 DIMM/PWM NAND_WP* D6 Video OUT AUX sign, 12 EN_BL UART3_RX_D K15
BOOT_MODE0 and BOOT_MODE1 are two pins of CPU, responsible for BOOT procedure.
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Drawing above shows three BOOT mode signals and correlation between them.
Really, BOOT_MODE_CTRL is only one control signal to provide in assembly or
reparation time access to boot from serial downloader (USB). In normal (application)
mode CPU will always BOOT from mode 00. (BOOT_MODE_CTRL will be high). Note that BOOT_MODE0 and BOOT_MODE1 after finishing BOOT mode can be used as
normal GPIO. Really, it means that using these two signal only as outputs has some
meanings. Using these pins as inputs of course can lead to uncontrollable BOOT procedure.
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POW_GOOD is control out from nanoSOM™ NS01. Signal is generated high when all local supplies inside nanoSOM™ NS01are OK. User should use this signal to enable
supply for I/O peripherals at carrier board. See in the rest of documents more
description for this signal.
RESET_OUT* is system reset, coming from circuits inside nanoSOM™.
Also CPU IMX6UL can generate RESET_OUT* pulling pin RST_OUT_L located in AUX I2C
expander (see in the rest of document in chapter “Some specific signals”).
RES_IN* is (optionally) external RESET input signal (including reset KEY).
(See in the rest of document in chapter “Some specific signals”).
4.5. Left connector internal
Pin Name Type IMX6UL (Pin name) Pin Comment 1 JTAG_RST* JTAG_TRST/ P13
JTAG signals 2 JTAG_MODE JTAG_MOD R13
3 CCM_CLK1_N CCM_CLK1_N U16 Differential
CCM_CLK 4 CCM_CLK1_P CCM_CLK1_P T16
4.6. Top connector internal
Pin Name Type IMX6UL (Pin name) 1 TDO JTAG_TDO R16
Pin Name Type IMX6UL (Pin name) Pin Comment 1 I2C_IO1
GPIO based at I2C 2 I2C_IO2 3 I2C_IO3
4 I2C_IO4
4.8. Tamper pins
At bottom side we have also ten tamper pins. These tamper pins are located in
“forbidden area” in order to hide these tamper pins (if customer prefers it). Position of CPU tamper pins is not linear with tamper pads in PCB. The next table shows
position for all tampers pins.
Pad Name Type IMX6UL (Pin name) 1 Pad 1(first towards TOP) Tamper 1 P6
Tamper pins
2 Pad 2 (NEXT) Tamper 6 R7 3 Pad 3 (NEXT) Tamper 4 P7 4 Pad 4 (NEXT) Tamper 0 R8 5 Pad 5 (NEXT) Tamper 5 P8 6 Pad 6 (NEXT) Tamper 9 P9 7 Pad 7 (NEXT) Tamper 7 N9 8 Pad 8 (NEXT) Tamper 3 P10 9 Pad 9 (NEXT) Tamper 2 N10 10 Pad 10 (first towards BOTTOM) Tamper 8 N8
PAD1
PAD10
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5. Description
nanoSOM™ NS01 is built around SOC (System on chip) ARM A7 single core, Freescale
FBGA 272 pins IMX6UL (case 9 mm x 9 mm).
In next page is presented BLOCK diagram of nanoSOM™ NS01, which contains (main
parts):
1) IMX6UL
2) AUX CIRCUITS (peripherals on board)
3) Power supplies 4) External and internal PADs (“connectors”)
IMX6UL is heart of nanoSOM™ NS01 and with single core ARM A7 processor and
provides (contains cores):
Interface towards DDR3L
Interface towards eMMC USB interface (one OTG channel and two HOST connected to local HUB)
Two Ethernet ports (10/100Mb)
A lot of peripherals (UARTs, SD, CAN, I2C, Audio I2S, Video Out RGB, Video In, SPI…
Simple GPIO /PWM pins
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5.1. IMX6UL and main circuits
5.1.1. Single Core ARM Cortex A7
nanoSOM™ NS01 is based at IMX6UL, single core ARM Cortex-A7, located in SOC, which
operates at speed up to 528 MHz.
5.1.2. Embedded memory controller (DDR3L)
IMX6UL includes embedded memory controller with support for various memory types.
In nanoSOM™ NS01 is used DDR3L (1V35) in 16 bits mode. The footprint for DDRAM3 supports 2 Gb, 4 Gb and 8 Gb packages.
5.1.3. eMMC
IMX6UL supports eMMC (embedded MMC). It is used high speed Nand port in 4 bits
mode for eMMC. In nanoSOM™ NS01 embedded eMMC is used as main OS memory.
Due to reduced space, it is used smaller (153 balls) chip. In the past this package was used up to max. 8GB, but in last time this restriction is overridden.
Attention: eMMC signals are local signals, inside board (not visible at “connectors”).
Table below shows assigning Nand port signals to eMMC memory.
Signal name Signal Name (CPU) Pin
EMMC_D0 NAND_DATA0 D7
EMMC_D1 NAND_DATA1 A9
EMMC_D2 NAND_DATA2 C9
EMMC_D3 NAND_DATA3 C7
EMMC_CLK NAND_RE* D9
EMMC_CMD NAND_WE* A8
Attention: eMMC is connected in 4 bit mode. Although, of course IMX6UL can
support 8 bits mode, due to reduced numbers of pins, is concluded that better
solution is to have one SPI/four GPIO more.
5.1.4. USB support
USB section of IMX6UL contains two OTG controllers with incorporated PHY. In order to maximally use existing USB features, nanoSOM™ NS01 provides the next
structure:
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Two ports
USB HUB
USB2422
IMX
6U
L
US
B O
TG
1U
SB
OT
G2
Load
switchOC*
EN
+5V
VBUS
USB+,USB-,
IDUSB0 port (OTG)
USB1 port (HOST)
USB2 port (HOST)
USB+.USB-,OC*,EN
USB+.USB-,OC*,EN
EX
T. p
ins
EX
T. p
ins
EX
T. p
ins
EN
Practically, USB OTG Port1 is used directly as OTG port (adding some external circuits).
To use this, user doesn’t need to add anything to carrier board
USB Port 2 is used with external (located at nanoSOM™ NS01) dual ports HUB. Of
course, user must to add only external load switch and power supply.
This way, nanoSOM™ NS01 is equipped with:
One OTG port
Two HOST ports (via local HUB)
5.1.5. CAN1 and CAN2
nanoSOM™ NS01 contains two CAN channels.
Signal name Signal Name (CPU) Pin
CAN1_TX UART3_CTS H16
CAN1_RX UART3_RTS H15
CAN2_TX UART2_CTS J17
CAN2_RX UART2_RTS J14
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5.1.6. UART1, UART5 and UART6
IMX6UL contains up to 8 Uarts (some of them only RX, TX pair)
In nanoSOM™ NS01, due to PIN MUXING, only some UARTS are default provided:
UART 1 (RX,TX) UART 5 (RX,TX,CTS,RTS)
UART 6 (RX,TX,CTS,RTS)
There is also UART3 which can be shared with SPI3
Signal name Signal Name (CPU) Pin
RX1 UART1_RX_D L17
TX1 UART1_TX_D L15
RX5 CSI_DATA1 D4
RTS5 CSI_DATA3 D1
CTS5 CSI_DATA2 B2
TX5 CSI_DATA0 C3
RX6 CSI_PIXCLK D5
RTS6 CSI_HSYNC D2
CTS6 CSI_VSYNC D3
TX6 CSI_MCLK C1
5.1.7. SPI1, SPI2, SPI3 and SPI2
IMX6UL contains total 4 SPI controllers.
Unfortunately, no all available features of SPI can be used. All SPI have up to 4 CS*, but mainly (due to PIN MUXING) only one CS* can be used (see below).
In some special configuration, of course, more CS* can be used, reducing other
peripherals.
Practically, available SPI resources (default) in nanoSOM™ NS01 are:
SPI1 (One CS*) SPI2 (One CS*)
SPI4 (One CS*)
SPI3 (Two CS*)
Attention: Momentary SPI3 is shared with UART3 (TBD in final version)
nanoSOM™ NS01 contains more Audio OUT I2S channels.
Due to PIN MUXING nearly all of them are not available in default state. Fortunately,
JTAG port can be used also for this purpose (I2S).
Signal name Signal Name (CPU) Pin
AUDA_TX_BCLK JTAG_TDI P17
AUDA_RX_DATA JTAG_TCK R17
AUDA_TX_DATA JTAG_TRST P13
AUDA_TX_SYNC JTAG_TDO R16
AUDA_MCLK JTAG_TMS R14
5.1.9. I2C
IMX6UL supports up to 4 I2C controllers, but in nanoSOM™ NS01 is used I2C port 4 as system
nanoSOM™ NS01 I2C controller. Note that also UART1 (RX, TX) can be used. It is I2C port 3.
Signal name Signal Name (CPU) Pin
SCL UART2_TX_D L16
SDA UART2_RX_D K16
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5.1.10. SD card
nanoSOM™ NS01 contains one SD controller for external SD card access.
Signal name Signal Name (CPU) Pin
SD_CLK SD1_CLK C5
SD_CMD SD1_CMD C6
SD_D0 SD1_D0 A5
SD_D1 SD1_D1 A4
SD_D2 SD1_D2 B5
SD_D3 SD1_D3 B4
SD_CD* UART1_RTS K14
SD_WP* UART1_CTS L14
5.1.11. Display interface (parallel RGB)
nanoSOM™ NS01 incorporates eLCDIF sysbsystem. The eLCDIF is a general purpose display controller used to drive a wide range of display devices, varying in size
and capability. The eLCDIF is designed to support dumb (synchronous 24-bit Parallel
RGB interface) and smart (asynchronous parallel MPU interface) LCD devices. Parallel video out controller 24bits use LCD_DATA0-LCD_DATA23 lines. This controller supports
8, 16, 18 or 24 bits width.
Table below shows video out (LCD) bits mapping
Bit position Pin Color 16 bits Color 18 bits Color 24 bits
LCD_DATA0 D11 B0 B0 B0
LCD_DATA1 B12 B1 B1 B1
LCD_DATA2 D10 B2 B2 B2
LCD_DATA3 B11 B3 B3 B3
LCD_DATA4 A11 B4 B4 B4
LCD_DATA5 D12 G0 B5 B5
LCD_DATA6 D13 G1 G0 B6
LCD_DATA7 C12 G2 G1 B7
LCD_DATA8 B13 G3 G2 G0
LCD_DATA9 A13 G4 G3 G1
LCD_DATA10 D14 G5 G4 G2
LCD_DATA11 C13 R0 G5 G3
LCD_DATA12 C14 R1 R0 G4
LCD_DATA13 A14 R2 R1 G5
LCD_DATA14 B14 R3 R2 G6
LCD_DATA15 A16 R4 R3 G7
LCD_DATA16 A15 R4 R0
LCD_DATA17 D15 R5 R1
LCD_DATA18 B15 R2
LCD_DATA19 E12 R3
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LCD_DATA20 B17 R4
LCD_DATA21 C16 R5
LCD_DATA22 B16 R6
LCD_DATA23 C17 R7
In addition to standard Data signals, video controller is followed with some additional
control signals:
Signal name Signal Name (CPU) Pin
LCD_ENAB LCD_ENAB A10
LCD_HSYNC LCD_HSYNC B10
LCD_VSYNC LCD_VSYNC C10
LCD_CLK LCD_CLK C11
LCD_RST LCD_RST E10
EN_VDD (*) UART3_TX_D K17
EN_BL (**) UART3_RX_D K15
DIMM (***) NAND_WP* D6
(*) Signal used as enable display supply.
(**) Signal used as backlight enable signal. (***) Signal used as PWM adjustment signal for backlight (dimming).
5.1.12. Ethernet
nanoSOM™ NS01 supports two RMII channels (10/100Mbit) and includes also two additional signals ENET_MDIO and ENET_MDCLK for PHY control.
Signal name Signal Name (CPU) Pin
RMII1_ERROR ENET1_RX_ER G14
RMII1_CRS_DV ENET1_RX_EN G16
RMII1_RD0 ENET1_RX_D0 G17
RMII1_RD1 ENET1_RX_D1 F16
RMII1_TXEN ENET1_TX_EN F15
RMII1_TXCLK ENET1_TX_CK G15
RMII1_TX0 ENET1_TX_D0 E16
RMII1_TX1 ENET1_TX_D1 F13
RMII2_ERROR ENET2_RX_ER H13
RMII2_CRS_DV ENET2_RX_EN D16
RMII2_RD0 ENET2_RX_D0 E17
RMII2_RD1 ENET2_RX_D1 D17
RMII2_TXEN ENET2_TX_EN E15
RMII2_TXCLK ENET2_TX_CK H14
RMII2_TX0 ENET2_TX_D0 E14
RMII2_TX1 ENET2_TX_D1 F14
ENET_MDIO GPIO1_IO6 N15
ENET_MDC GPIO1_IO7 N14
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Table above shows signals included in RMII interface.
5.1.13. GPIO and A/D
Various GPIO are provided, using GPIO pins from IMX6UL.
Under GPIO we consider various generic input/output signals. These signals are available to user as GPIO and are not dedicated to some special interfaces, presented
above. Note that also these “special” interfaces could, in one custom design, be used
also as GPIO. For example, if user has not need for Video input, he could all these pins of Parallel video input use for GPIO, in case of lack of GPIO pins.
Unfortunately, only three GPIO pins remained really free for customer using (not
included in any peripheral above).
Signal name Signal Name (CPU) Pin
GPIO3 GPIO1_IO5 P15
GPIO1/PWM1 GPIO1_IO8 P14
GPIO2/PWM2 GPIO1_IO9 P16
Attention: All these three GPIO can be used also as Analog inputs, connected to
embedded in IMX6UL A/D converter.
Attention: Also tamper pins can be used as GPIO (no analog inputs).
5.2. AUX Circuits
nanoSOM™ NS01 contains some additional circuits.
5.2.1. RTC
For nanoSOM™ NS01 for RTC purpose is used M41T83 RTC chip, although IMX6UL has
own RTC. Solution with M41T83 RTC is much better in power OFF (battery) mode. Chip is supplied (standby mode) with Vbb (Vbattery). Vbb can be in range 2-5.5 V.
Consumption in standby mode is about 400 nA.
5.2.2. SEEPROM
nanoSOM™ NS01 contains one standard I2C SEEPROM (X24C04) with address 0x50.
5.2.3. Additional I2C 8 bits port
Due to lack of GPIO pins, nanoSOM™ NS01 is equipped with one eight bits I2C expander.
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IMX
6U
L
RST_OUT
To generate
RESET_OUT
P0
EX
T. p
ins
P1
P2
P3
P4
P5
P6
P7
PMIC_INT
INT from
PMIC
To generate
RED LED(FAULT)
To generate
GREEN LED(DL)
Simple
GPIO
PCA6408
SCL
SDA
COMM_INT
SCL
SDA
INT
Four pins are used for local, on board activities (P0, P1, P6 and P7)
Four pins (P2-P5) are connected to external pins as simple GPIO for customer using. In schematic these pins are named I2C_I/O1 - I2C_I/O4.
Note that I2C expander contains also output interrupt, connected to one GPIO pin of IMX6UL, so via expander we can control also external interrupts. Signal COMM_INT is
connected to GPIO1_IO3 (pin N16) of IMX6UL.
Signals P6 and P7 are used as standard ERROR and RUN leds (see drawing above)
Signals I2C_IO1 – I2C_IO4 are general purpose I/O. These signal can be used (for
example) as RMII interrupts, coming from PHY. Note that INT* output of PCA6408 (COMM_INT*) goes to GPIO1_IO3 pins of CPU and can be used as interrupt to
CPU.
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Signal P1 (PMIC_INT*) is input, connected to PMIC_INT* pin of PMIC (PF3000).
RST_OUT_L is output with one special feature. It is one optionally RESET_OUT control bit. Via this bit is possible announce external RESET for peripherals (no
power up RESET).
5.3. Power supplies
Power supply for nanoSOM™ NS01 is based at PF3000, power supply companion chip for
IMX6UL.
Input voltage is +3V3, +-5%.
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5.4. Internal and External Pads (“Connectors”)
This and next page show “connectors” for:
Internal connectors (pads) with included tamper pins1s
External connectors (pads)
These drawings port the same info as tables, presented before, and goal of these
drawings is only to give user one compact view and position of signals.
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Internal connectors (pads)
External connectors (pads)
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5.5. Board View
The next two pictures below show TOP and BOTTOM (REAR) side of nanoSOM™ NS01.
Picture above shows TOP side of nanoSOM™ NS01.
Picture below shows BOTTOM side of nanoSOM™ NS01.
Attention: It is board through view (from TOP side view, where TOP side is transparent).
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Take attention to external (at board edges) and internal I/O pads.
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5.6. Support for IMX6ULL
nanoSOM™ NS01 is basically based at IMX6UL and above described peripherals and
features refers to mounted IMX6UL in area of CPU inside board.
In addition to IMX6UL, nanoSOM™ NS01 supports also IMX6ULL processor with some power reduction.
IMX6ULL processor, although pin compatible with IMX6UL, has some constraints (simple some peripherals are not provided).
In other words, version nanoSOM™ NS01 with mounted IMX6ULL doesn’t provide all
features.
Table below depicts differences with mounted MCIMX6Y1CVK05AA (industrial version of
IMX6ULL) respecting standard IMX6UL.
Differences IMX6UL IMX6ULL
1 LCD/CSI (video input-output) Yes (available) No (not available)
2 CAN CAN 1 and CAN 2 Only CAN 1
3 Ethernet Ethernet 1 and Ethernet 2 Only Ethernet 1
4 ADC ADC 1 and ADC 2 Only ADC 1
5 Security Basic and advanced Only Basic
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6. Building carrier board pattern for hosting nanoSOM™ NS01
This chapter shows building nanoSOM™ NS01 pattern (footprint, shape) at carrier board,
where nanoSOM™ NS01 will be soldered.
Building shape is fairly simple because pin positions (IO PADS) are mainly full symmetric
respecting board edges and virtual board center.
Shortly, user must:
Create shape outline for virtual nanoSOM™ NS01 (25.4mm x 25.4 mm) and board hole inside (21.6mm x 21.6mm).
Really TOP_LEFT angle is inclined, so LEFT and TOP edges are 23.50mm.
Create External IO PADS at board edges (TOP 31 + RIGHT 34 + BOTTOM 34 and
LEFT 32). Create Internal IO PADS at hole edges (4 + 20 +4)
Create 10 TAMPER PADS
We strongly suggest to follow this procedure in order to build appropriate
carrier shape for nanoSOM™ NS01:
1) Outline: Draw (outline) rectangle 25.40 mm x 24.50 mm (dimensions of
nanoSOM™), having in mind that TOP-LEFT angle is inclined.
2) TOP ext. connector (pads T4-T34): Place 31 rectangle PADS 0.508mm x 1.041mm (20mil x 41 mil) with distance 0.7mm between them. First PAD center
is 3.25mm right from LEFT edge and 0.075 mm lower of TOP edge of outline.
3) RIGHT ext. connector (pads R1-R34): Place 34 rectangle PADS 1.041mm x
0.508 (41mil x 20 mil) with distance 0.7mm between them. First PAD center is
1.15mm lower of TOP edge and 0.075 mm left from RIGHT edge of outline.
4) BOTTOM ext. connector (pads B1-B34): Place 34 rectangle PADS 0.508mm x
1.041mm (20mil x 41 mil) with distance 0.7mm between them. First PAD center
is 1.15mm left from LEFT edge and 0.075 mm above BOTTOM edge of outline.
5) LEFT ext. connector (pads L3-L34): Place 32 rectangle PADS 1.041mm x
0.508 (41mil x 20 mil) with distance 0.7mm between them. First PAD center is 2.55mm lower of TOP edge and 0.075 mm right from LEFT edge of outline.
6) LEFT int. connector (pads IL1-IL4): Place 4 rectangle PADS 1.0mm x 0.7mm (39.4mil x 27.6 mil) with distance 1mm between them. First PAD center is 1.4mm
right from LEFT edge and 3.20mm lower of TOP edge of outline.
7) TOP int. connector (pads IT1-IT20): Place 20 rectangle PADS 0.7mm x 1.0mm (27.6mil x 39.4 mil) with distance 1mm between them. First PAD center is
3.20mm right from LEFT edge and 1.4 mm under TOP edge of outline.
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8) RIGHT int. connector (pads IR1-IR4): Place 4 rectangle PADS 1.0mm x
0.7mm (39.4 mil x 27.6 mil) with distance 1mm between them. First PAD center is 1.40mm left from RIGHT edge and 3.20 mm under TOP edge of outline.
9) TAMPER pads (Tamper 1-10). Place 10 circle PADS, D=30mil (0.762mm) with
distance 1mm between them. First PAD is located: 1.20mm from LEFT edge and 10.83 mm from TOP edge of outline.
10) PCB hole: Provide PCB hole 21.60mm x 21.60mm. Note that PCB hole is full symmetric in X and Y axis, respecting virtual board center. TOP side of
carrier (under microSOM™) can be used for routing (of course where is
available).
11) Provide some arrow at silk screen near LEFT TOP angle for board
orientation (origin).
For external, internal and tamper IO pads:
Make Solder mask shape 4 mils bigger of PAD (all PADS). Make Solder past shape the same as PAD.
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0.075mm
0.075mm
3.25mm
0.7mm
1.0mm
1.4
mm
1.0
mm
0.7
mm
2.5
5m
m
3.20mm
1.4mm
3.2
0m
m
T4
IT1
IL1
L3
0.075mm
0.7mm 1.15mm
T34
R1
1.1
5m
m0
.7m
m
IT20
IR10.075mm
3.20mm
1mm
1.4
mm
3.2
0m
m
1m
m
1.4mm
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Two drawings above are detailed drawings for building internal and external pins (except
TAMPER pads). It is presented LEFT_TOP angle as specific one (some PADS are missing) and
TOP_RIGHT angle. Other two angles are not presented because are full symmetric with
TOP_RIGHT angle (only different orientation).
Really these two drawings are only for some additional verification. If customer strongly follows procedure presented above (1-11). Shape creation shouldn’t be any problem.
Building TAMPER PADS is also very simple. Customer should start with first TAMPER PAD (see dimensions and position above) and simple add adjacent PADS with pitch 1mm.
6.1 One Important addition for internal pads
Procedure above, presents building all PADS for nanoSOM™ NS01 as simple TOP only SMD pads. Initial idea was not to complicate creation immediately with special shapes
for internal PADS. Really, internal PADS are not so simple.
Practically, customer must take special attention to internal PADS only (not external and not Tamper) and this chapter explains it.
Practically, due to more reasons simple only TOP SMD PADS for internal PADS (total 4 + 20 + 4) must be modified:
Reason 1. There is no sufficient space at carrier board for access to internal PADS
via using normal VIAs Reason 2. Creating these PADS with metallization offers possibility to better
control soldering of these internal PADS.
Drawing below shows in which way internal PADS must be modified.
TOP layer holds original dimensions and position (0.7mm x 1.0 mm) with adding ARC at hole edge
All other signal layers must have “COOPER” and ARC like TOP layer, but can be
really smaller respecting TOP PAD. For example 0.5 mm x 0.7 mm is one good
choice. Customer can hold all signal layers the same as TOP layer, but there is no any sense to lose precious PCB space.
Simple
SMD
PAD
Modified
SMD
PAD
Modified
SMD PAD(other signal layers)
(TOP layer)
Hole edge
1m
m
1m
m
0.5
mm
0.7mm 0.7mm 0.7mm
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It is very important that “ARC” side of PADS is metalized.
This way, we have:
1) PADS connection to all layers without classic hole.
2) Possibility of (optionally) manual resoldering if there is need.
This chapter describes procedure for building this complex PAD in PCAD6 tool.
(PCAD6 doesn’t allow directly built this type of PAD, but with some explanation for PCB manufactures it can be resolved).
Some newest tools probably provides direct this way of PADS building.
1) Create normal “through hole” PADS with rectangle shapes (explained above)
with rectangle 0.7mm x 1mm at TOP layers for 20 pin horizontal internal PADS
and 1mm x 0.7 mm for total 8 vertical internal PADS also at TOP layer. For other signal layers create “smaller” PADS 0.7mm x 0.5 mm (0.5mm x 0.7mm).
2) Create these PADS with “virtual” hole 1mils in PAD center.
3) In production file (GBR) inform PCB manufacturer to change “virtual” hole
1mm with real hole D=27mils and to move them 29mils toward board center.
4) After metallization process and removing central rectangle hole from board, we
will have these complex PADS, where part of ARC (see drawing below) will be
metallized.
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6.2 Some specific signals
This chapter describes some specific signals (system signals), important in carrier board
building. Drawing below shows typical using these signals:
nanoSOM™ NS01 is supplied by +3V3S (system) supply (+3V3 +- 5 %)
Used for carrier
circuits supply
DC/DC
24V/3V3
Pow_good
+3V3
In Load switch
Or P-CH
mosfet
+3V3S nanoSOM
supply
Out
DC/DC
24V/3V3
PFAIL
Detection
(optionally)
PFAIL_IN*INT
RESET_IN
circuits
(optionally)
RESET_inRes_in*
Res_out*
(optionally)
(optionally)
SYS_RESET_OUT*(optionally)
Battery or
Super CAPVbb
2V-5.5V
24V
na
no
SO
M
(active HIGH)
1) VBB is input for connecting to some Battery source, used for RTC. Typical are
used Lithium battery, Lithium rechargeable or Super CAP. Range is 2V-5.5V.
In case of using rechargeable battery or Super CAP, user must provide additional circuits at carrier board.
2) RES_OUT* is standard RESET_OUT* signal for resetting external circuits, located
at carrier board. See picture below. Note that RES_OUT* follows
local on board main reset (signal CPU_RST). In addition, also CPU (IMX6UL) can
independently create RES_OUT* via signal RST_OUT_L (see chapter 5.2.3 –Adding I2C 8 bits port).
3) RES_IN* is optionally RESET_IN* (Max +3V3, active 0) signal for whole system, coming from carrier board. For example can be used external standard CPU
supervisors, or simple manual RESET key. Using external circuits is optional,
because nanoSOM™ NS01 contains embedded power on RESET circuits.
4) PFAIL_IN* is optionally PFAIL_INTERRUPT*, for interrupting CPU in case of early
power supply power detection. Really, there is not dedicated PFAIL_IN* pin in
nanoSOM™ NS01. It is only presented one idea for using any of available INT
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(really GPIO). It could be important for backup some critic application, where
early power down event can be used for file or application closing. Typical using for this is connecting this signal to some comparator which controls
main power supply.
5) POW_GOOD is one mandatory signal (out from nanoSOM™ NS01, active high) to enable supply auxiliary circuits at carrier board. nanoSOM™ NS01 is supplied
by +3V3S (system) from carrier board, but supply for circuits at carrier must be
controlled by this signals to respect power up procedure for CPU at nanoSOM™ NS01.
External circuits, connected to I/O pins of nanoSOM™ NS01 shouldn’t be supplied before POW_GOOD is asserted (see drawing above).
Drawing below show RESET*_OUT and RES_IN* circuits in nanoSOM™ NS01.
Drawing below shows connection for some specific signals.
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6.3 Using FRAM with nanoSOMTM
nanoSOM™ NS01 doesn’t contain FRAM (on board), but due to fact that FRAM can
be often used, it is reserved SPI channel for direct support at user’s carrier board.
It means that user must connect FRAM always in this way (see below) in order to
have direct FRAM support. By the way, the same connection is applied in Evaluation board for nanoSOM™ NS01.
It is used SPI3 channel. Note that SPI3 channel is with two CS*. CS0* is reserved for FRAM and CS1* is free for user (see bottom using TPM
module). This way, SPI3 channel remains free (using CS1*) for user.
See two drawings below.
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6.4 Using TPM module with nanoSOMTM
In case that nanoSOM™ NS01 is used for Trusted zone application, good solution is
using with TPM (Trusted Platform Module) SLB9670. Module SLB9670 exists in version TPM 1.2 and TPM 2.0, which are fully compatible with
hardware view point.
The best solution is to connect to, above mention SPI3 channel, using free CS1*.
Practically, using FRAM and TPM module SLB9670 SPI3, channel is full occupied for
these two system functions.
Picture below shows using TPM SLB9670 module with nanoSOM™ NS01:
It is provided also interrupt from SLB9670. Solution for interrupt can be to use one of
four free I2C I/O, In this case I2C extender behaves exactly as one simple interrupt
controller.
Of course, it is possible also use some of free GPIO as interrupt destination, but in some
complex boards these inputs will probably be occupied by its natural peripherals.
