NASA TECHNICAL REPORT...039-00-00-00-72 11. Contract or Grant No. 13. Type of Report and Period...

N A S A T E C H N I C A L R E P O R T

. . A DIGITAL-TO-ANALOG CONVERSION CIRCUIT USING THIRD-ORDER POLYNOMIAL INTERPOLATION

by Willium P. Dotson and Joe H. Wilson

Manned Spacecru, Center Houston, Texus 77058

N A T I O N A L AERONAUTICS A N D SPACE A D M I N I S T R A T I O N W A S H I N G T O N , D. C. FEBRUARY 1972

-

I. Report No. 2. Government Accassion No.

1. Title and Subtit le

NASA TR R-382 -

3. Recipient's Catalog No.

5. Report Date February 1972

5. !Supplementary Notes

7. Author(s1 William P. Dotson and Joe H. Wilson, MSC

9. Performing Organization Name and Address

Manned Spacecraft Center Houston, Texas 77058

2. Sponsoring Agency Name and Address

6. Abstract

Zero- and third-order digital-to-analog conversion techniques are described, and the theoretical e r r o r performances are compared. The design equations and procedures for constructing a third-order digital-to-analog converter by using analog design elements are presented. Both a zero- and a third-order digital-to-analog converter were built, and the performances a r e compared with various signal inputs.

8. Performing Organization Report No.

MSC S-272 10. Work Unit No.

039-00-00-00-72 11. Contract or Grant No.

13. Type of Report and Period Covered

Technical Report

17. Key Words (Suggested by Authoris) ).

Digital- to- Analog Conversion * Interpolation e Interpolation Circuits * Telemetry Systems . Third-Order Interpolation Circuits ' High-Order Interpolation Circuits ' Digital-to-Analog Converters

I 19. Security Classif. (of this report)

None 20. Security Classif. (of this page) 21. NO. of Pages 22. Price

62 $3 -00 ~~~ . . - ~.

18. Distribution Statement

For sale by the National Technical Information Service, Springfield, Virginia 22151

I

I

CONTENTS

Section

SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THEORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. BASIC ANALOG DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONCLUDING REMARKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . .

APPENDIXA-ERROREQUATIONS . . . . . . . . . . . . . . . . . . . . . . APPENDIX B - SPECIFIC DESIGN FORMULAS . . . . . . . . . . . . . . . . . APPENDIX C -SCALING COMPUTATIONS . . . . . . . . . . . . . . . . . . . APPENDIX D - CALIBRATION PROCEDURES . . . . . . . . . . . . . . . . .

Page

1

1

2

4

9

13

35

35

36

42

46

50

iii

FIGURES

Figure Page

1 Analog- to-digital encoding

(a) Analog signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 (b) Pulse-amplitude- modulation signal . . . . . . . . . . . . . . . . . 4 (c) Pulse-code-modulation signal (eight quantization levels) . . . . . . 5

2 Zero- and third-order DAC outputs

(a) Zero order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 (b) Third o r d e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Reconstruction e r ro r s for a zero-order DAC

(a) Geometry for calculating cb . . . . . . . . . . . . . . . . . . . . . 5 5

(c) Error as a function of normalized sampling rate . . . . . . . . . . 6

(b) Geometry for calculating E . . . . . . . . . . . . . . . . . . . . . P

4 Reconstruction e r r o r s for a third-order DAC

(a) Geometry for calculating eb . . . . . . . . . . . . . . . . . . . . . 6 (b) Geometry for calculating E . . . . . . . . . . . . . . . . . . . . . 6

P (c) Error as a function of normalized sampling rate . . . . . . . . . . 7

5 Third-order PAM version of the analog signal . . . . . . . . . . . . . 7

6 Sample-delay-circuitry block diagram . . . . . . . . . . . . . . . . . . 9

7 Flow chart for the use of circuitry with digital logic elements . . . . . 9

8 Flow chart for the use of circuitry with analog logic elements . . . . . 9

9 Initial- condition- circuitry block diagram . . . . . . . . . . . . . . . . 10

10 Integrator-circuitry block diagram . . . . . . . . . . . . . . . . . . . 11

11 Third-order DAC block diagram . . . . . . . . . . . . . . . . . . . . . 1 2

1 2 Example data and clock sequence

(a) Sample-and-hold reconstruction of an example analog-data word sequence at TP1 . . . . . . . . . . . . . . . . . . . . . . .

(b) Data-clock (or track) signals at TP2 . . . . . . . . . . . . . . . . 12 (c) Signal from figure l2(a) phased with the clock signal . . . . . . . . (d) Signal from figure 12(c) delayed one sampling period . . . . . . . .

1 2

13 1 3

iv

Figure Page

(e) Signal from figure 12(c) delayed two sampling periods . . . . . . . 1 3 ( f ) Signal from figure 12(c) delayed three sampling periods . . . . . . 1 3

1 3 Results of a 0.05-hertz square-wave input (p = 20 samples/cycle) as a function of time

14

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . . 14 (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . . 1 4

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

(d) -CT /4. initial-condition output . . . . . . . . . . . . . . . . . . . 14

(e) D T / ~ . initial-condition output . . . . . . . . . . . . . . . . . . . . 14

(f) -3B-r /8 output or 'ir' . . . . . . . . . . . . . . . . . . . . . . . . 14 (g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . 14

(h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . 14

2

3

14 Results of a 0.1-hertz square-wave input (p = 10 samples/cycle) as a function of time

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

(d) . CT /4 initial-condition output . . . . . . . . . . . . . . . . . . . 15 (e) D7/4. initial-condition output . . . . . . . . . . . . . . . . . . . . 15

(f) -3B'r /8 output o r 'Y . . . . . . . . . . . . . . . . . . . . . . . . 15

(g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . 15 (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . 15

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . . 15 (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . . 15

2

3

15 Results of a 0.2-hertz square-wave input (p = 5 samples/cycle) as a function of time

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

(c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . . 16

(e) D7/4. initial-condition output . . . . . . . . . . . . . . . . . . . . 16

(f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . . 16

(g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . 16


(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . . 16

(d) . CT /4. initial- condition output . . . . . . . . . . . . . . . . . . . 16 2

3

V

Figure Page

16 Results of a 0.01-hertz sine-wave input (p = 100 samples/cycle) as a function of time

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 (a) Input 18 18

18 . . . . . . . . . . . . . . . . . . . . 18 (e) B / 4 , initial-condition output

18

18

18

(b) Third-order DAC output (1 sample/sec) (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . . (f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . . (g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . 2

... 3 ..


. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 (a) Input 19

19

19 19

19

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 19

(d) - CT /4, initial- condition output . . . . . . . . . . . . . . . . . . . (e) B / 4 , initial-condition output . . . . . . . . . . . . . . . . . . . . 19

(f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . . (g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . .

2

... 3

18 Results of a 0.03-hertz sine-wave input (p = 33. 33 samples/cycle) as a function of time

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 (a) Input 20 (b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 20 (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 20 (d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 (e) D7/4, initial-condition output

20 (f) -3B7 /8 output or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 (g) Y integrator output


2

... 3


. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 (a) Input 21 21

21

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . . 2

vi

Figure Page

(e) D T / ~ , initial-condition output . . . . . . . . . . . . . . . . . . . . 21

(f) -3BT /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . . (g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . .

... 21 21

21

3

20 Results of a 0. 07-hertz sine-wave output (p = 14. 3 samples/cycle) as a function of time

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 (b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 22 (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 22

(d) - CT /4, initial- condition output . . . . . . . . . . . . . . . . . . . (e) D T / ~ , initial-condition output . . . . . . . . . . . . . . . . . . . . 22 (f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . . (g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . .

22

22 22 22

2

... 3

21 Results of a 0.1-hertz sine-wave input (p = 1'0 samples/cycle) as a function of time

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

(d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . .

(f) -3B7- /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . .

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 23 (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 23

23 (e) D T / ~ , initial-condition output . . . . . . . . . . . . . . . . . . . . 23

23 23

23

2

... 3

(g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . Results of a 0.2-hertz sine-wave input (p = 5 samples/cycle) 22

as a function of time

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

(c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 24


24 24 '24

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . 24

(d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . .

(f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . .

2

... 3

(g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . .

vii

I

Figure Page

2 3 Results of a 0. 3-hertz sine-wave input (p = 3. 33 samples/cycle) as a function of time

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 (a) Input 25 25

25 25

25

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (c) Zero-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . .

(f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . . . (g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

(e) D7/4, initial-condition output . . . . . . . . . . . . . . . . . . . . ... 3 ..

(h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . Results of a 0.4-hertz sine-wave input (p = 2. 5 samples/cycle)

25

24 as a function of time

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 (a) Input 26 26


26

26

26

(b) Third-order DAC output (1 sample/sec) . . . . . . . . . . . . . . (c) Zero-order DAC output (1 sam'ple/sec) . . . . . . . . . . . . . . (d) -CT /4, initial-condition output . . . . . . . . . . . . . . . . . . .

(f) -3B7 /8 output o r Y . . . . . . . . . . . . . . . . . . . . . . . .

2

... 3

(g) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . . (h) Y integrator output . . . . . . . . . . . . . . . . . . . . . . . . .

25 Sinus bradycardia

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 (a) Input .. . 27 27 27

(b) Third-order DAC output (1 00 samples/sec) . . . . . . . . . . . . (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . .

26 Normal sinus

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 (a) Input 27 (b) Third-order DAC output (1 00 samples/sec) . . . . . . . . . . . . 27 (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . 27 (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . .

27 Sinus tachycardia

(a) Input 28 28 28 28

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (b) Third-order DAC output (1 00 samples/sec) . . . . . . . . . . . . (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . .

viii

Figure

28

Page

First-degree block

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (b) Third-order DAC output (100 samples/sec) . . . . . . . . . . . . (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . .

28 28 28 28

29 Second-degree block

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (b) Third-order DAC output (100 samples/sec) . . . . . . . . . . . . (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . .

29 29 29 29

Third-degree block 30

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (b) Third-order DAC output (1 00 samples/sec) . . . . . . . . . . . . (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . .

30 30 30 30

31 Atr i a l flutter


30 30 30 30

32 A t r i a l fibrillation

31 31 31 31


33 Ventricular tachycardia

31 31 31 31


34 Ventricular fibrillation


32 32 32 32

ix

Figure Page

35

36

37

38

39

A- 1

A- 2

A- 3

A- 4

Asystole

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 (b) Third-order DAC output (1 00 samples/sec) . . . . . . . . . . . . 32

(d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . . 32 (c) Zero-order DAG output (100 samples/sec) . . . . . . . . . . . . . 32

Expanded view of normal sinus rhythm

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 (b) Third-order DAC output (1 00 samples/sec) . . . . . . . . . . . . 33 (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . 33 (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . . 33

Expanded view of second-degree block

(a) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 (b) Third-order DAC output (100 samples/sec) . . . . . . . . . . . . 33 (c) Zero-order DAC output (100 samples/sec) . . . . . . . . . . . . . 33 (d) Zero-order DAC output (200 samples/sec) . . . . . . . . . . . . . 33

Plot of sampling frequency required for a third-order DAC to equal the performance of a zero-order DAC at the base-line crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Plot of sampling frequency required for a third-order DAC to equal the performance of a zero-order DAC at the waveform peaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Geometry for calculating eb for a zero-order DAC . . . . . . . . . . 36

Geometry for calculating E for a zero-order DAC . . . . . . . . . . 37 P

b

P

Geometry for calculating E for a third-order DAC . . . . . . . . . . 38

Geometry for calculating E for a third-order DAC . . . . . . . . . . 40

X

A DIGITAL-TO-ANALOG CONVERSION C I R C U I T U S I N G

THI RD-ORDER POLYNOMIAL INTERPOLATION

By W i l l i a m P. Dotson a n d Joe H. W i l s o n M a n n e d Spacecraf t C e n t e r

SUMMARY

This report describes the basic design for a circuit that is capable of reconstruct- ing digitized analog signals by interpolating between given sample points with a third- order polynomial. design equations a r e developed and implemented on an analog computer.

From an analytical description of the circuit inputs and outputs,

The theoretical e r ro r performance of the third-order digital-to-analog converter is developed from the analytical description, and the e r ro r performances a r e compared with experimental results. digital-to-analog converter, and these results a r e compared with results of the third- order digital-to-analog converter.

The same is done for a zero-order (sample and hold)

Both theoretical and experimental comparisons of third-order and zero-order digital- to-analog converters show a markedly superior performance of the third-order digital-to-analog converter. From these results, it is shown that the use of third- order digital- to-analog converters for analog-data reconstruction will allow a signifi- cant decrease in the bandwidth required for digital telemetry systems that transmit analog data, with no decrease in the quality of the data.

INTRODUCTION

In most telemetry systems in use today, digital-to-analog conversion is performed by zero-order (sample and hold) interpolation circuits. ive feature of relative simplicity. disadvantage of these circuits is frequently overlooked. higher than necessary sampling rates must be used in the digital encoding of the analog signal. The use of higher sample rates increases the bandwidth necessary to transmit the signal and thereby imposes additional cost and complexity on the remainder of the telemetry system. The design and performance of a digital-to-analog converter (DAC) that uses a third-order polynomial interpolation between sample points a r e presented in subsequent sections of this report; use of such a DAC permits lower sampling rates without decreasing the accuracy of the reconstructed analog signal. However, if the need to reduce the sampling rate (bandwidth) does not exist', the use of such a DAC will significantly improve the data quality.

Such circuits have the attract-

This disadvantage is that However, because of this attractiveness, the basic

The theoretical and practical design and performance of a high-order (third order) interpolation circuit for digital-to-analog conversion of telemetry data are discussed in this report. The study described was initiated in an attempt to relieve the bandwidth problems in the NASA Manned Space Flight Network telemetry system that occur as a result of the high- sampling- rate biomedical data (i. e. , electrocardiograms (EKG' s ) ) , and, at the same time, to maintain the present accuracy level of the data.

SYMBOLS

A

cf

G c

e

e in

e out

F, G, H

f

K = ZJZi

L

m

amplitude

constant coefficients of polynomial te rms

feedback capacitance

initial- condition voltage applied to the circuit

voltage

input voltage

output voltage

scale factors

frequency, Hz

cut-off frequency, Hz

sampling frequency, samples /sec

root- mean- square spectrum of g(t)

time function

integrators

integrator gain, 1/ RiCf

ratio of the spectrum cut-off ra te of the signal to 6 dB/octave

2

P', Q', R', S', T'

P

R

Rf

Ri

'17 '2

S

T

t

TP1, TP2

Y

i. .. Y ... Y

'i

E

b E

E P

P

r

w

waveform segments of an EKG signal

normalized sampling rate, samples/cycle

resistance

feedback resistance

input resistance

switches

Laplacian operator

period, l / f , sec

time, sec

test points

reconstructed signal, V

f i rs t derivative of Y with respect to time

second derivative of Y with respect to time

third derivative of Y with respect to time

analog signal as a function of time, V

analog reconstruction of y(t)

feedback impedance

input impedance

e r ror , percent o r pulse code modulation (PCM) counts

instantaneous e r ro r measured near the base-line crossing, percent

instantaneous e r ro r measured at the peaks, percent

reset time, sec

sampling period, sec

angular frequency, rad/sec

3

I

Subscripts :

ic initial condition

n = 0, 1, 2, 3, . . .

THEORY

The analog-to-digital encoding used in the Apollo telemetry system is described as follows and is illustrated in figure 1.

1. The analog signal (fig. l(a)) is sampled for i ts amplitude value at time inter- vals spaced T seconds apart (fig. l(b)), where T is the inverse of the sampling rate.

2. The amplitude values are then pulse code modulation (PCM) encoded (fig. l (c)) before transmission.

In zero-order digital-to-analog conversion, the PCM signal (fig. l(c)) is accepted and converted to a pulse amplitude modulation (PAM) signal (fig. l(b)), which is then fed to a holding circuit that provides an output curve similar to the curve shown in figure 2(a). A third-order DAC wizl also accept PCM signals, convert them to PAM signals, and then compute and output a third-order polynomial, which is a function of time, to fit the transmitted signal samples (fig. 2(b)). The reconstruction e r ro r s that result from this and other processes have been found analytically by previous work (ref. 1). Some of the results of that work, along with experimental checks performed in this study, are shown in appendix A.

The purpose of this report is to describe a method of designing a circuit on the analog computer for the third- and zero-order DAC's described in reference 1. The geometries for calculating the e r ro r s for the third- and zero-order DAC's a r e presented in figures 3 and 4. The use of the design method would allow an experimental verification of the e r ro r analysis shown in figures 3(c) and 4(c) and also would provide the basic design for a prototype of the third-order DAC.

I I I I 0 5s 10s 15s

Time, t

I

2% I I I I 1

57 10 T 15 T 202

Time. t

(a) Analog signal. (b) Pulse-amplitude-modulation signal.

Figure 1. - Analog-to-digital encoding.

4

t 0

22 3r 4 r 50

6 r 7r 87 9r lor llr 127 134 14s 15s 16 r 177

- r

PCM signal 011 100 101 100 011 010 011 100 101 110 111 011 010 010 011 100 100 100

(c) Pulse - code - modulation signal (eight quantization levels).

Figure 1. - Concluded.

I I I I I I I 1 I 0 7 2s 3T 4s 5s 6 s 7 2 8+

2 Time, t

c H t l l l l I l l l l I l l l l l l l l I , - 0 5s lo+ 15s 207

lime. t

(a) Zero order.

> i ar > . a - - m c - ._

E 1 1 1 1 I I 1 1 1 1 1 . 1 I I I I I 1 I I - 0 5s 10s 15s 20s E I 1 1 1 1 I I 1 1 1 1 1 . 1 I I I I I 1 I I - 0 5s 10s 15s 20s

l ime, t

(b) Third order. Figure 2. - Zero- and third-order

DAC outputs.

I- T I

P' (a) Geometry for calculating eb. (b) Geometry for calculating E

Figure 3. - Reconstruction e r ro r s for a zero-order DAC.

5

I

I I I I -7 0 T 2r -37 - -

2 -

2 2 2 Time, t

(a) Geometry for calculating eb.

-31 2 - z

2 T - 2

Time, t

37 2 - 5s

2 -

P' (b) Geometry for calculating E

(c) Error as a function of normalized sampling rate.

Figure 3. - Concluded. Figure 4. - Reconstruction e r r o r s for a

third- order DAC .

The development of the design equations for a third-order DAC proceeds as follows. The development is facilitated by initially assuming the existence of a PAM version of the analog signal, such as that shown in figure 5. At t = 0, the circuit must compute and output a signal that is described by a third-order polynomial that would connect the input PAM signal points Y1-n, Y2-n, Y3-,, and Y4-n. The output actu-

ally s tar ts at t = 0, n = 0 (or Y2) and continues only until t = T, n = 0 (or Y3), s o

that only the central two points of the given four a r e connected. This completes one cycle of operation. 2 t = T, n = 1 (or Y3). This cycle could be visualized as sliding the data points leftward

past a fixed time scale, s o that time, for the circuit, is always between 0 and T. At the same time, the circuit, in an abstract sense, has both memory and precognition, because the circuit must have knowledge of the samples Y1-n and Y4 - n.

The next cycle begins a t t = 0, n = 1 (or Y ) and continues until

6

30 1

20 I

Normalized sampling rate, p. samplesfcycle

(c) E r ro r as a function of normalized sampling rate.


Y1-"

- 3 r - 2 7 -7 0 r 2 7 3 7 4 r 55

Time, t

Figure 5. - Third-order PAM version of the analog signal.

This knowledge is necessary because the circuit output between t = 0 and t = T

must be described by

(1) 3 2

y(t) = Bt + C t + Dt + E

which is a third-order polynomial. there are four unknowns (B, C, D, and E) in equation (l), the signal voltages (Y 1, Y2, Y3, and Y ) must be given at four sample t imes (-7, 0, 7, and 27, respec- tively) (fig. 5). The coefficients B, C, D, and E may be evaluated from the following equation set .

Because

4

3 2 + C(-7) Y(-T) = B(-T) + D(-T) + E = Y1

(3) 2 Y(O) = ~ ( 0 ) ~ + c(o) + D(O) + E = y2

3 Y(7) = B(7) + C(7)' + D(T) + E = Y3 (4)

(5)

7

As a result of solving equations (2) to (5)

-Y1 + 3Y2 - 3Y3 + Y 4 B = n

67 '

Y1 - 2Y2 + Y 3 C = n

27 '

-2Y1 - 3Y2 + 6Y3 - Y4

67 D =

E = Y2

The initial conditions of the output signal may also be calculated. If

then

3 2 Y(t) = Bt + Ct + Dt + E

2 ?(t) = 3Bt + 2Ct + D

Y(t) = 6Bt + 2C

... Y(t) = 6B

Y(0) = E

Y ( 0 ) = D

Y ( 0 ) = 2 c

... Y(0) = 6B

8

. . .

BAS IC ANALOG DES I GN

Digital-data words

Equations (6) to (17) in the preceding section are sufficient for the design of an The equations that specify

C, D, and analog circuit that will perform the desired interpolation. the initial conditions (eqs. (14) to (17)) of the circuit are in te rms of B, E, which are in te rms of Y1 to Y4 (eqs. (6) to (9)).

samples, in proper time sequence, must be accessed simultaneously for computation of the initial conditions each time a new sample is received by the circuit.

The implication is that four

Sample-and- hold digital- to- analog conversion

This delay can be readily implemented with a device similar to a shift register

=Y2, and Yl-n=Y1. The next (fig. 6). hold, from top to bottom, Yqen=Y4, Y3-,=Y3, Y2-n

The operation of this arrangement is as follows. If n = 0, then the registers

Clock c

I nit ial-condit ion computation c i rcu i t ry

Figure 6. - Sample-delay-circuitry block diagram.

Serial-data words

telemetry and serial-to-

lronverter

data value Y5 register by a clock pulse which will incre- ment n by 1. Now the top register holds

= Y , the next register holds Y4 = Y5-n 4 - Y3, then Y3-n=Y2, and Y2-n=Y1. The initial-condition circuitry is then ready to compute a new set of initial conditions. sample-delay circuitry that was discussed in the preceding section may be physically implemented with either analog o r digital logic elements. in figures 7 and 8.

will be read into the top -

The

Block diagrams are shown

Serial-data words. Sample-and- parallel bits hold digital-

parallel to-analog converter conversion

Figure 8.- Flow chart for the use of c i r - cuitry with analog logic elements.

9

The initial-condition circuitry, which is driven by the sample-delay circuitry, is formed of summing amplifiers designed according to equations (6) to (9) and amplitude-scaling constraints. Consideration of full-scale values for Y

of various sampling rates indicates that the initial-condition circuitry will operate well if scaled according to the following equations, which are taken directly from equations (6) to (9). The equations are developed in appendix B.

to Y4 and

The initial-condition circuitry should have the following four outputs.

3 1 16 (- Y1 + 3Y2 - 3Y3 +Y4) 3B-r - - - _ - - 8

2 1 2 3)

- T - - s ( Y 1 - 2 Y c-r - + Y

(20) ) 2 Y 1 - 3 Y 2 + 6 Y 3 - Y 4

The shown initial-condition-circuitry in figure 9. (A more extensive design is dis- -y1Z;>

< 38T3 ._ cussion of the use of the initial-condition circuitry can be found in appendixes C and D. ) Different scaling factors may be

+y2

- 8

10 0.1 -y3 16

- chosen, of course, provided appropriate +y4 16 +ylzFTp < cg

rescaling in the following portions of the circuit is also completed.

._ 4

2 -Y The remainder of the interpolation

circuit consists of integrators that are driven by the initial-condition circuitry. If equations (17) and (18) are examined simultaneously, it is clear that

- +y3 8

E 4 3 -Y

3 7 3 16 y(o) (22)

3B-r - - - _ - - 8

Figure 9. - Initial-condition-circuitry block diagram.

10

3 Therefore, i f -3B7 /8 is input to an integrator with a gain of -2/7, the output will be T ~ Y / ~ . This output requires an initial condition of

2 ~ C T ~ - C 7 8 8 4 2 7 -. - y(0) = - - -

which is provided by the initial-condition circuitry, as specified by equations (16) and (19).

Equation (19) involves not + C T ~ , but - C T ~ , because integrators invert their initial condition. initial conditions on each integrator initial- condition input appropriate to that integrator output.

This procedure is continued through two more integrations, with

The final result is shown in figure 10.

Figure 10. - Integrator-circuitry block diagram.

The circuit discussed in this report requires three timing signals. One signal is a clock (or track) signal that is synchro- nous with the data. The other two signals (a hold signal and an integrator-reset signal) a r e derived from the clock signal.

The track and hold signals a r e necessary only fo r the track and hold pairs that are used in a shift-register-like arrangement and may be eliminated if the sample- delay circuitry is implemented with digital logic. edge of the clock pulse, and the duration of the track signal is 0. 017. The integrator- reset signal must occur after the clock pulse s o that the signals have completed shifting before the resetting of the integrators. reset signal reinitializes the integrators each time a new sample value enters the circuit. The complete circuit is shown in figure 11 with track and hold amplifiers in the sample-delay circuit. Example analog- data and data-clock sequences are shown in, figure 12.

The track signal occurs at the leading

The

11

Digital-data words

Sample-and-hold digital -tO-analog conversion

Differentiator Track signal, TP2 Data clock

I I

I I words

Analog-data

I

h--:ty4 I I

I ,

"I, G: 2'

(TPl

38s - - -Y 8

ty1;z9 -Y 2

tyl$-p

-- C T 2 4

+y3 118

+ y 2 DT 4 -

3 - Y

+y4 10124

- E

0.1

38 T3 - 8

DT 4 -

Figure 11. - Third-order DAC block diagram.

e

0 5s 10s Time, t

- 1 5 s

(a) Sample-and- hold reconstruction of an example analog-data word sequence at TP1.

A-

N

(b) Data-clock (or track) signals a t TP2.

Figure 12. - Example data and clock sequence.

12

-2

I I I ~ I I I I I I J

5s 10s 15s 57 10s 15r Time, t Time, t

(c) Signal from figure 12(a) phased (d) Signal from figure 12(c) delayed with the clock signal. one sampling period.

m1 5s 10s I 15s I L I ~ I ~

5s 10s 15s Time, t l i m e , t

(e) Signal from figure 12(c) delayed (f) Signal from figure 12(c) delayed two sampling periods. three sampling periods.


EXPER I MENTAL RESULTS

The digital-to-analog conversions made in this experiment were carried out on an analog computer. A function generator was used to obtain the sinusoidal and square- wave inputs, and a polyrhythm generator was used to obtain the complex EKG analog inputs. recorder.

The outputs of the system were displayed on an eight-channel strip-chart

To check the initial-condition- circuitry outputs, a square-wave input w a s used to simulate a step-function input. zero outputs, because the mathematical derivative of a step function is zero. functions 'Y, Y , and $ are shown to be zero in figures 1 3 and 14. The 0.2-hertz input in figure 15 did not yield derivative values of zero because the sampling rate was only 5 samples/cycle, o r 2. 5 sampledhalf-cycle. Four o r more samples/half-cycle a r e required in order for the derivatives to settle to zero, because this would require that Y1 = Y2 = Y3 = Y This relationship can be seen by examining equations (6), (7), and (8). If By Cy and D are identically zero, then Y(t) = Y(t) = Y(t) = 0. puts were obtained with no adjustments to the theoretical gains of the initial-condition circuitry. dures and were found to agree exactly with the theoretical values.

The initial-condition circuitry was then checked for The

which implies that B = C = D = 0. 4'

(See eqs. ( l l ) , (12), and (13). ) These zero-derivative out-

The integrator gains were checked with respect to the calibration proce-

13

-- I f

i I

I I I I I I I T

100 50

= o 8 -50 -100

VI / I 1 ITr I l l

1 . 1 I I I I I I I I I ! I I I ! ! I 1 - 4 - 1 I I I I ! ;'i - - + - I I I I I I I 1 / 1 1 *i i I I I I I I I I I I I I I I r

11 I

I 1 ilkt I I I I I I I / / / / / / I i i / I l l I

1 1 TT / I I

100 50

= o B -50

- 100

v)

- - I - - t l - - I t I I I l l 1

"I -- I

t - H t I I l I I I I l l 1 ' lil~ 11 1 i

~

i I I I I I I I ! I I I I I

i i l

J 11 T

I I , , , ! ! ! I I I I I

40 20

= o -20 -40

m

B

- + I I

- 1 N - t

4 I- ! sec Time - Figure 13. - Results of a Q. 05-hertz square-wave input

(p = 20 samples/cycle) as a function of time.

14

100 50 0

-50 - 100

“ c s

40 20

- 20 -40

“ 0 s

100 50

VI g o -50

- 100

100 50 0

-50

“ s

- 100

I I I I I 1;- t +

1

i i n 1 4

ii 111 II I- . .

I I I I I I I I i c H

I I I t *

I I 1 1 . 1 I I I I if--l

Figure 14. - Results of a 0.1-hertz square-wave input (p = 10 samples/cycle) as a function of time.

15

100

- 5 0 z o

-50 -100

I I I I I I I I I

I I I I I I I I

I I I I I I I I

Figure 15. - Results of a 0.2-hertz square-wave input (p = 5 samples/cycle) as a function of time.

16

To obtain the peak and base-line crossing e r rors , a comparison of the third-order DAC and the zero-order DAC was obtained by the method shown in figures 3 and 4. The results obtained with sinusoidal inputs of 0.01, 0.02, 0.03, 0.05, 0.07, O..l, 0.2, 0. 3, and 0.4 hertz are shown in figures 16 to 24. The e r r o r analysis is shown in figures 3(c) and 4(c). The accuracy of the results is 1 2 . 5 percent. Because these data were obtained from the strip-chart recordings (figs. 16 to 24), the smallest scale obtainable was 5 volts. The experimental e r r o r s obtained were less than the theoretical e r r o r s in some cases, partly because of the *2. 5-percent accuracy and the inability to re- produce exactly the base-line crossings and peaks of the theoretical analysis. A s shown in figures 3(c) and 4(c), the theoretical and experimental e r r o r s closely agreed, and the general trends were the same. cuitry, the third-order DAC output lagged the input waveform by two sampling periods (2 seconds in this case) in figures 16 to 24.

Because of processing delays within the cir-

Figures 25 to 35 show a comparison of the EKG input from the polyrhythm generator, the third-order DAC output at 100 samples/sec, the zero-order DAC output at 100 samples/sec, and the zero-order DAC output at 200 samples/sec. The zero-order DAC output was artifically delayed two sample periods to permit accurate phase adjustments for e r r o r calculations based on comparisons of both zero- and third-order DAC outputs with the original data. Because the input was from the polyrhythm generator, the analog data were stable from cycle to cycle. in the DAC outputs w a s caused by reconstruction e r r o r s within the digital-to-analog conversions.

Therefore, any variation

Of the expanded versions of two of the inputs, the third-order DAC output most closely approximates the analog input (figs. 36 and 37). present in the Q wave in both figures on the third-order trace. The Q'-to-R' peak transition approximates a step function, and a step function with sharp corners requires an infinite number of te rms to f i t the curve. The third-order DAC generates ordy the first four t e rms of fiat series. (fig. 37).

However, a slight e r ro r is

The zero-order DAC is also in e r ro r at this point

It has been shown from both the analytical and the theoretical standpoints that a third-order DAC is more accurate than a zero-order DAC. put is much smoother because the output is piecewise continuous.

The third-order DAC out-

Figures 38 and 39 (cross plots of figs. 3(c) and 4(c)) show that, for normalized sampling frequencies above 5 samples/cycle, it is advantageous to use a third-order DAC instead of a zero-order DAC at twice the rate. This procedure results in a 2: 1 advantage. This ratio becomes increasingly larger as p is increased for the zero-order DAC. third-order DAC allows reduced sampling rates to be used with no degradation in accuracy and allows a substantial reduction in the bandwidth required to transmit the EKG's.

This advantage is of major importance for two reasons. U s e of the

17

VI i 8

VI

8

+ + L t t l I I l I I I I I l I I I I '

100 50 0

- 50 - 100

100 50 0

-50 ,100 I 4 I I I 1 1 . 1 I I I I I I I I I 1 8 '

40 20

r " 0 8 - 20

-40

100

VI 50 0 0

- 50 - 100

>

I i I I / i I I I I Ilil I i inm WIlI I I ! T I 1 I / I 1 1 1 1 I 2 i i i i i l l I I

:d) -CT /4, initial-condition output. --H t t I

Time - Figure 16. - Results of a 0. 01-hertz sine-wave input


18

L 100

-100

100 I 8 01

-100 1 VI 5 0 , 1

-50

I

100

50 I * 0

-50 1 40 20

2 2 0 -20 -40

100 50 0

-50

- 100

100 50 0

-50 -100

40

s -100 I

I

v)

s

v) r 9

I

-40, I

100 I 1

I I I I I I I I I I I I I I H - . I I I l l I I I I I I

l1 i i l i I ,

I I I l l 1 1 1 I l l t i - I I I I I I I

I I I I I I I + (c) Zero-order DAC output (1 sample/sec). I I I I 1 1 1 l l k t

t 1 1 1 dition I T ' i output. I 1 1 1 1 , I I I I l l 1 1 1 1 1

, , I , , , I , , J / , , L . u _ , , , . . . I I I I I I , I I I I I I I I I I (e) &/4, initial-condition outwt. I I I I I I I l l l l l l l l l l l l l l l t

i l ... l l Y.

I l l 1 1 / 1 1 I l l 1

. I 1 I 1

I l l I l l

I l l 1 l l l l l l l l l l l f - H 1 / 1 1

/ I 1 1

I 1 I i i lT

I I l l i i i m

rator output. 1 1 1 1 1 / 1 1 in1

UI I I I I T 1

I ! I I l l integrator output.

Figure 17. - Results of a 0.02-hertz sine-wave input (p = 50 samples/cycle).as a function of time.

19

4 I--1 sgc

I II I I I I I I I t t I I I ! I I I I I I I

100

5 0 - 50

-100 +t I I I I I I I I I I I

100 50

= o 5 VI

-50 -100

+ i l I l I I I 1 I I I I (c) Zero-order DAC output (1 sample/sec). U i I I I I I I I I I I I

l~ I , IIIII I r i l l . 2 I

I I I I I (d) -CT /4, initial-condition outnut. i t t I I I I I I I I I I I I I I

I I I I I ,

I i l I I l IIlII I l l t i

i I 1 I / -condition output. + + + I I I I I I I I I I I I I I

100

VI 50 $ 0

-50 - 100

- 1 I I I I I I I I I I I I I I

l l i l

la output l l l l l l l l l l l l l l l l

I l l I l l

40 20

= o 9 - 20 -40

VI

i t i I I I I I I I I I I l ~ l l l l l I I I I I I I I I I I 1 1 1 1 integrator output.

~~ -~~

100

VI 50 9 0

- 50 - 100 w 4 I- 1 sec

Figure 18. - Results of a 0.03-hertz sine-wave input (p = 33.33 samples/cycle) as a function of time.

20

I I

> -50

-100 I 100 H)

0

- 50 - 100

" r 2.

I I I I I I I

40

20

- 20 -40

" 0 9

I I I I I I I

I I I I I I ,

I I I I I I I

I I I I I I

c- I !I *LA- -

1 I I I I I I I I I I I I I t+( Input. I I I I I I I I I I I

1

3 B ~ ~ / 8 H utput

t -. I I I I I I I I I

Time - Figure 19. - Results of a 0.05-hertz sine-wave input


~

I I I I I I ++

I I l I I I + t

I I I I I I t +

2 1

100

" s o i

- 50 -100

100 50

= o 8 -50

-100

VI

c 1 1 I I I I I

H t l I I I l

100

v1 50

s o c -

-50 -100 - 4 I - 1 sec

Figure 20. - Results of a 0.07-hertz sine-wave input (p = 14.3 samples/cycle) as a function of time.

22

I

r"r' I I I I I

100 t I

i I

1 -100;-

I I 1-1- I I I I I I

100 I

-100

loo M i VI

01

- -50 100 i

I I I I I I II 11 IT

40 1 20 ~

VI = 0 -- - 20 8 - 40

-100 1 1 1 1 1 1

40 20

VI oy 8 1 -20 1 -40 j

1 1 1 1 1 1 1 1 1 1 1 1 1 1

Time - sec

Figure 21. - Results of a 0.1-hertz sine-wave input (p = 10 samples/cycle) as a function of time.

23

100 50

-50 - 100

= " 0 s

I I

Time -+

Figure 22. - Results of a 0.2-hertz sine-wave input (p = 5 samples/cycle) as a function of time.

24

c I h L A

1 I "I I

* L h l - ' - ' 1 I j - l

' -501 -100 '

l l I I I I I I ++ I I I I I

I Y I I 111 I I \ I I I I l l I I \ I I I v I I h I I I I I I \ l I I 1 1 1

I I I I I I I I I I I I I I t * I

VI

5

- 100 / I l l I

40 20

I -40

loo I

-50 -100

I , I I I I , I I I I I , + (e) b / 4 , initial-condition output. I I , , I I I / I / , , , I , I I I I I i I I I 1 - 7 -

~ -

I + t- l l l l l

4 i VI 2o I_ 01

- M I

-40 I

100 I I I I I I I I I I I t l t t l

4

I J sec

4 1

tc Time +

Figure 23. - Results of a 0. 3-hertz sine-wave input (p = 3. 33 samples/cycle) as a function of time.

25

-1 hl h I. Ll h I 'M 100

50

-50 - 100

100

E o 9

- 5 0 3 0 r

- 50 -100 I

(b) Third-order DAC output (1 samolP/s, i 1 1 1

I I I I I I I l I I ! l I

I I I I I I I I 1 1 1 1 rl I 1

2o 0 - w 100 50 0

- 50

- 100

v)

r s

l l l l l l l l l l

tl 100 50

v)

g o > -50

- 100

40 20

= o - 20 9

-40

v)

100

v ) W 2 j o

-50 -100

- I - I h

4 t- 1 sec Time -

Figure 24.- Results of a 0.4-hertz sine-wave input (p = 2. 5 samples/cycle) as a function of time.

26

:ill! il I 'I

[ w I O

--c (e) Zero-order DAC output (100 eamples/sec). I

6! ! I : : !

! I + I I , I I I I I , I I I e t + (d) Zero-order DAC output (200 samples/sec). I I , I I i I I I I I I I I I I I I I 1 I T I I I I I I I I I I I I I I I I I I I I I I I I 1

Time - Figure 25. - Sinus bradycardia.

I

Time -.

Figure 26. - Normal sinus.

27

Figure 27. - Sinus tachycardia.

, , , , , , I , , I , , I I (d) Zero-order DAC output (200 samples/see). + , I I I I I I I I I I I 8 I I I 4 I

I I I I I I I I I I I I 1 . 1 I I I I I I I I I I I I I I I I I 1 I L i T r 1 . l I I I I I I I I I I I I I I I 1 I Time-

I I I I I I I I I I I I 1 . 1 1 ' 1 ' 1 I I I I I I I I i 1 . 1 I 1 1 . 1 I l i T r 1 . I 1 I I I I I I I I I I I I I I 1 I

, . ( ' b) Third-order DAC output (100 s

. 1 . , , (d) Zero-order DAC output (200samples sec). + * , 1 * A * ? I ! # > ; I rrrii i i i i i I ~ i i i i i ~ i i

Time -+

Figure 28. - First-degree block.

28

: I l l 1

I I I I I

I I I I I

I I I I I I;; ‘

I

I I I I I I

l l l l l t

I I I I I I I ( I I I I I

AC output (100 samples/sec).

(d) Zero-order DAC output (200 samples/sec). 2 ~- -- ~- . . : : ? I I I I - ; I ; : - I I I 1% I n , I I 1 - 1 I

I I Time - -I 1 sec I--

Figure 29. - Second-degree block.

29

m r P

* 4 1 sec I-

bl Thmd-order DAC outllvt (100 samples/s

c ) Zero-order DAC output (100 sampies./sec). t:

I

Time-

Figure 30. - Third-degree block.

, _ . , . . -z--A (d) Zero-order DAC output (200 samples 'SPY).

-? i . & % . . , 7 , , ,

1 1 sec +- Time-

Figure 31. - Atrial flutter.

30

I " ' : ' ' : ' , . . .

Figure 32. - Atr i a l fibrillation.

31

Time - 34. - Ventricular fibrillation.

/ I l l ! I / I ! , i i i i i l l l l l '

I I l l I / I /

b) Third-order DAC output (100 ~ a m r

i l l I l l

1 1 I / I I

I I I I I I I l l l l l l l i i i i i i i i I1 I ! 1 I 1 I , , , ,

d) Zero-order DAC output (ZOO sample _.- - i I I , I , j I L I L.

'. ' ' ' I

Time -t

Figure 35. - Asystole.

32

l I l l l l l l l l l / l l l l l / l I

Figure 36. -

i i l l l l l l l l l l l l l l l - l I I l l l l l l l l l l l l l l l l 1 I l l Time -+

Expanded view of normal sinus rhythm.

f > -

",PIPS sec).

ii- .i r

I I-1 I I

Time - Figure 37. - Expanded view of second-degree block.

33

. 3

1 1 I 1 1 1 1 1 1 1. 1 1 ' 1 1 1 1 1 I 1 I 1 I 1 1 1 1

0 2 4 6 8 10 20 40 M) 80 100 200 400 Mx) 800 IWO Normalized sampling frequency (zero-order OAC), p, sampleslcycle

Figure 38. - Plot of sampling frequency required for a third-order DAC to equal the performance of a zero-order DAC at the base-line crossing.

S I

I I I I 1 1 1 1 1 1 ~ ~~ L I U - L I I 1

2 4 6 8 10 20 40 60 80100 1

200 1 1

400 1 1 1 1 1 1

600 8001ooo Normalized sampling frequency (zero-order OACI. p , sampleslcycle

Figure 39. - Plot of sampling frequency required for a third-order DAC to equal the performance of a zero-order DAC at the waveform peaks.

34

CONCLUDING REMARKS

The experimental results of sample data that were processed by the third- and zero-order digital-to-analog converters indicate a markedly superior performance on the part of the third-order digital- to-analog converter. The experimental results are in close agreement with the results predicted by the theory.

It has been shown that the use of a third-order digital-to-analog converter will allow substantial reductions in the transmission bandwidth, with no decrease in the data quality. If no reductions in transmission bandwidth are necessary, then the use of a third-order digital-to-analog converter will greatly improve the quality of the reconstructed data.

Manned Spacecraft Center National Aeronautics and Space Administration

Houston, Texas, October 14, 1971 921-10-00-00-72

REFERENCE

1. Dotson, William P., Jr. : Dynamic Reconstruction Errors in Digital-to-Analog Systems with Biomedical Applications. NASA TN D-6296, Apr. 1971.

35

APPENDIX A

ERROR EQUATIONS

The equations for the peak e r ro r E and the base-line crossing e r ro r $ for a P

zero- and a third-order DAC were derived in reference 1 and are shown as follows. The zero ordinate of each figure was shifted to make the e r r o r equations as simple as possible.

ZERO-ORDER DAC

Figure A-1 is used to find the instantaneous e r ro r midway between two sample points for a zero-order DAC. This e r r o r is near the base-line crossing. The instantaneous e r ro r at t = 7/2 for the sample-point locations shown in figure A-1 is

_I

1 1 1 -J 0 1 T Zr 3r 4s 5 7 67 l r 8r 97

2 Time. 1

Figure A-1. - Geometry for calculating cj, for a zero-order DAC.

= A Ymax

y(t) = A sin (ut) (Alb)

y’(t) = A sin [w(O)] 0 5 t < 7 (Alc)

2T b - T E - 100 sin (w ;) w = -

y(;) = A sin (w 3

T P

7 = -

y’(;)= 0

where p = normalized sample rate in samples/cycle

36

(A2) a

Eb = 100 sin - P

Figure A-2 is used to find the instantaneous e r r o r at the peaks for a zero-order DAC. The instantaneous e r r o r at t = 0 for the sample-point locations shown in fig- u r e A-2 is

I T

y(t) = A sin b(t +:I (A3b)

y'(t) = A sin [o(: +:,] - i < t < - ' (A3c) 2 - 2

Time. t

Figure A-2. - Geometry for calculating E for a zero-order DAC.

y(0) = A sin k(o + g)] = A (A3d) P

~ ' ( 0 ) = A sin [ (-;+;! = A Ymax

E = loo[ - sin [.(-;+gj\ o=- 2n P T

T P

r = -

P

37

By using trigonometric identities, the equation

E = l o o k - cos ;) P

can be obtained. Equations (A2) and (A4) are plotted in figure 3(c).

THI RD-ORDER DAC

Figure A-3 is used to find the instantaneous e r ro r midway between two sample points for a third-order DAC. This e r ro r is near the base-line crossing. taneous e r ro r at t = 0 for the sample-point locations shown in figure A-3 is

The instan-

-7 0 T 3r 2 2 2 2

- - -37 -

l i m e , t

Figure A-3. - Geometry for calculating $ for a third-order DAC.

y(t) = A sin [ut + z + (A5b)

3 2 y'(t) = Bt + Ct + Dt + E

y( 0) = A sin [w(; + $1 (A5d)

'ma, = A (A 5f)

eb = 100 { sin [ E w - -I- - y - q

38

To find E, solve the set

By using trigonometric identities, the equation

(A81 P

can be obtained.

39

I ~~

Figure A-4 is used to find the instantaneous e r r o r at the peaks fo r a third-order DAC. The instantaneous error at t = 0 for the sample-point locations shown in fig- u r e A-4 is

(A94

-F) a 2 I / y(t) = A sin [w(t +:I (A9b) - ._ - CL

E a

3 2 - y'(t) = Bt + Ct + Dt + E

- , 4 - 1 1 1 -37 z - 7 - 37 - 57

2 2 2 2 2 3T (A9c) -

Time, t

Figure A-4. - Geometry for calculating E for a third-order DAC.

6494 P

E P = l O O ( 1 - g)

To find E, solve the set

3 2 y(- g) = B(- g) + C(- g) +D(- g) + E = A sin [w(: - $1

T T 3 2 p(- i) = B(- i) + C (- i) + D(- i) + E = A s in [ w ( ~ - 1)1

y'($ = B(iY + C ( i r + D(i) + E = A sin [w(: + ;)I

(Alla)

(A1 lb)

(A1 1 c)

40

y'(g) = B(gY + C!($)2 + D(g) + E = A sin [ w (: - +- "27)l which results in

(Alld)

(Alle)

where w = 27r/T and T = T/p. By using trigonometric identities, the equation

P P 3=1 P E = 1 O O F - ;(9 cos - - cos - 7r

can be obtained.

A comparison of the e r ro r s obtained with a third-order DAC and a zero-order DAC can be determined by cross plotting the normalized sampling rate of each and in- dicating the percent e r r o r s at various points, as is done in figures 38 and 39. The figures show that for normalized sampling frequencies above 5 samples/cycle, it becomes advantageous to use a third-order DAC instead of a zero-order DAC. In figure 39 - the worst case of the two - for p = 10 on the zero-order DAC, p M 5 on the third-order DAC for the same accuracy.

41

APPENDIX B

SPECIFIC DESIGN FORMULAS

The basic design element in analog circuitry is the high-gain amplifier, which is indicated by the following symbol.

Ideally, the high-gain amplifier has infinite open- loop gain, infinite input impedance, and zero output impedance. Normally, the gain is also assumed to be negative; that is, the amplifier inverts the signal. Under these conditions, for the following circuit configuration, equation (B 1) is applicable.

eout - - - & ein = -Ke. in

1

The gain for this circuit configuration, then, is a function of only Z and Z.. f 1 Rather than always drawing in the impedance elements, a new symbol is usually defined

42

where K is the ratio of the feedback impedance to the input impedance. Summing amplifiers a r e easily constructed from the previous configuration and have output voltages given by equation (B2).

R f R i ,I

el- R i ,2

e2 - en

0 0 0

- -> R i ,n

e = -(Klel + K e + . . . +Knen) out 2 2

Integrators are formed by changing the feedback element to a capacitor and have output voltages given by equation (B3).

The te rm l/s is a Laplacian operator that indicates integration. The te rm l/RiCf controls the gain involved in the integration. The previous configuration may be abbreviated to

where L = l/RiCf.

43

Integrators can also be configured to form the integral of summed inputs.

Initial conditions must be known before solutions to integrals can be found. Known initial conditions can be placed on integrator outputs by appropriately charging the capacitor in the feedback loop. The time in which this capacitor is being charged is called the reset time. Integrators, then, have additional circuitry that is used for setting or resetting the initial conditions on output. One possible circuit follows.

e in eout

Reset

Operate

Because of the assumed infinite gain of the amplifier, the point A is at a virtual ground; theref ore

e ic eout

Ric Ric -+-

Equation (B4) can be written as follows by using Laplace-transform notation.

e @ic +- out + ~ [ I s e f out - e out (0) I -o SRic Ric

44

or

+ Cfeout(0) ic

It should be apparent that a definite time interval is required to set the initial conditions on the integrator output. At t = 5RicCf, the output will have reached 99-1/3 percent of its correct value. After this time has elapsed, the integrator may be switched to the operate mode. The reset time then should be

For a duty cycle of 99 percent (operate-to-reset ratio), p" 0.017, where T is the time interval between samples. A further constraint on the integrator circuitry is in its gain. The integrator gain L is

1 1 L=-=- T RiCf

45

APPENDIX C

SCALING COMPUTATIONS

The scaling equations are developed by conjecturing a normalized full-scale sine-wave input sampled at a very high rate so that, in the limit, the sequential values of E (fig. 11) approach Y. That is

lim P - *

E - Y = sin u t

The first three derivatives of Y can then be found.

+ = w cos w t

2 Y = -w sin wt ..

... . 3 Y = -w cos ut

If equations (8) and (15) from the text a r e equated

?(O) = D = - -2Y1 - 3Y2 + 6Y3 - Y4) - w COS w t 6: ( If equation (C5) is manipulated and multiplied by the scale factor F

F67?(0) = F67D = F 2Y1 - 3Y2 + 6Y3 - Y4) - F ~ T W COS w t (- (C6)

If sin w t is a full-scale output, then F67w is chosen such that F67w cos ut is one- half full scale. (One-half full-scale output is chosen arbitrarily to avoid both of two common e r ro r sources in analog devices, which are (1) the nonlinearity e r ro r s at full- scale voltage outputs and (2) noise e r ro r s at voltage outputs near zero. ) Therefore

46

and

F=- 1 12TW

Because w = 27~f, 7 = l/fs, and p = fs/f,

Equation (C9) implies that the scale factor depends on the lowest samples/cycle desired. If a rate of oily T samples/cycle is desired, p = T and F = 1/24. The initial condition on Y should then be scaled to be

67P( 0) - TP( 0) - D7

so that

D 7 - 1 - 3Y2 + 6Y3 - Y4) 4 - 24 (-2y1

Similarly, the scale factor G on Y ( 0 ) can be found.

Y ( 0 ) = 2 c = - 1 Y - 2Y2 + Y 3 ) 2 ( 1

7

where

lim z ( ~ l 1 - 2 y 2 +y3)- - w 2 sin Ut p - m 7

and

GT~Y(o) = 2G7 " c = G y1 - 2 y 2 + y3>

(C 13)

47

where

2 2 l im G(Y1 - 2Y2 + Y3) - - GT w sin wt P--O0

2 2 Because GT w =1/2

1 G=- 2 2 2w T

and

2 1 G = -

2 fS

For p = n-, G = 1/8. Thus

T2Y(0) - CT 2 2.. GT Y(0) = - - - 8 4

and

4 CT2 = d Y 1 1 - 2Y2 +Y3)

where

Similarly, the sca le factor H on Y(0) can be found.

48

1 ... Y(0) = 6 B = 3 (-Y1 + 3Y2 - 3Y3 + Y 4 )

7

-y + 3Y - 3Y3 +Y4) - -w 3 cos wt lim 3( 1 2

p - m T

and

where

Because

H T ~ Y ( O ) = ~ H T 3 B = H Y1 + 3Y2 - 3Y3 +Y4) (-

for p = 77, then H = 1/16. Thus

3 3 1 z HT w =

and

where

3

1677 H = 3 P

3... 73 ... 6 ~ 7 ~ 1 4)

HT Y(0) = Y(0) = - = - (-Y1 + 3Y2 - 3Y3 + Y 16 16

~ B T ~ 1 8 == (-Y1 + 3Y2 - 3y3 +y4)

49

APPENDIX D

CALI BRATION PROCEDURES

The initial-condition circuitry shown in figure 9 computes numerical approxima- tions to successive derivatives of the original waveform. The derivatives are then used to drive the integrator circuitry. Obviously, if the derivative calculations a r e in e r ror , the final output will also be in e r ror .

One means of calibrating the initial-condition circuitry is to put a sampled func-

The easiest function to work with in this instance is a step tion with known derivatives into the total circuit and then examine the outputs of the initial-condition circuitry. input, so that in the steady state, all derivatives a r e zero. With this input, the outputs of the initial-condition circuitry should be identically zero; if they a r e not, the potentiometers in front of the summing amplifiers require adjustment.

The integrator gains may also require adjustment. gain 1/r may not be realized because of tolerance limits on the feedback capacitors, input resistors, et cetera. For this reason, potentiometers were included in front of each integrator for fine adjustments.

Their theoretically required

From an inspection of the circuit shown in figure 11, it should be clear that the integrator chain serves only to fill in estimates of data values within the given sequence of data values Yz, which is the initial-condition input of the final integrator. It is in-

tuitively obvious, then, that the potentiometers in front of each integrator should be adjusted so that the final output is piecewise continuous. A sampled sine-wave input is easiest to work with in this instance.

The outputs of the three integrators can be checked to see if they a r e piecewise continuous as follows. output of the first integrator (11) can be determined by

First, the output of the integrator will be determined. The

3 2 I1 = -1- T ( ; ) d t 3Br 2 +%

or

2 3Br2 CT 4 4 I1 = - (t) +-

50

The output can be checked to determine if it is piecewise continuous by evaluating

That is, the continuity can be checked by asking whether and comparing the result with the initial condition at the next set of data values.

t=T

After solving, it is determined that

Y2 - 2Y3 + Y 4 = Y2 - 2Y3 + Y 4

Therefore, the output of I1 is piecewise continuous.

or

The output of integrator two (12) can be

2 I2 = -/(% +

found as follows .

4 cT2)2 - d t - - DT 7 4

The output of I2 can be checked for piecewise continuity by asking whether

or

51

When equation (D8) is solved, it is found that

Therefore, the output of I2 is not necessarily piecewise continuous.

The output of integrator three (13) is

or

(D11) 3 2 I3 = Bt + C t + D t + E

The output of I3 can be checked for piecewise continuity by determining whether

1 3 1 ~ ~ ~ = E' (D12)

or

(-Y1 + 3Y2 - 3Y3 +Y4) ( 3 ) T 3 +(yl - 2y2 +y3)($) 67

When equation (D13) is solved, it is found that Y3 = Y3. Therefore, the output of I3 is piecewise continuous.

52 NASA-Langley, 1972 - 7 S-272

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