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CNM-IMB Presentation

NATIONAL MICROELECTRONICS CENTRE(CNM)

Microelectronics Institute of Barcelona(IMB)


CNM Organisation Chart

SPANISH COUNCIL FOR SCIENTIFIC RESEARCH

(CSIC)Board of Trustees

NATIONAL MICROELECTRONICS

CENTER (CNM)D+T Microelectrónica, A.I.E.

MICROELECTRONICS INTITUTE OF

BARCELONA (IMB)

MICROELECTRONICS INSTITUTE OF MADRID (IMM)

MICROELECTRONICS INSTITUTE OF SEVILLA (IMSE)

LARGE SCALE FACILITY

(Integrated Clean Room)


CNM-IMB Organisation Chart

Administration

General Services

Management

Departments

Micro-nanosystems

Systems Integration

Large Scale Facility

Integrated Clean Room

Technological Support Units

Maintenance

DirectionDirection

Vice-direction


2008 Budget: 20 M€External Funding: 32.7 %

External Funding Splitting:

EU: 18%National: 55%Industry: 27%

CNM-IMB

STAFF (2008)

• Researchers 63• Students 41• Clean Room 33• Support Services

Management, Administration & General Services 21

• Visitors 3________________________________

Total 179


CNM-IMB Research Lines

Micro-nanosystems Department• Silicon-based Micro and Nanotechnologies• Micro and Nano-devices• Application Specific Micro and Nanosystems Development

Systems Integration Department• Power Devices and Systems Integration• Microelectronic Circuits and Systems Design and Packaging• Biomedical Technologies, Devices and Systems


The Large Scale Facility


Clean Room

• 1,450 m2

• House in house structure• Class: 10-10,000


CMOS Clean Room• 11 furnaces: dry and wet oxidation, Al annealing,

Boron diffusion …• CVD equipments: LPCVD, PECVD-TEOS, PECVD, • ALD, RTCVD • Implanter 10-200keV: Ar, N, Si, As, P, B• New implanter: Al,B… 0-500ºC, 2keV-200keV• Metallization : 3 sputterings (Al, AlSi, AlCu) and

1 e.gun (Al)• 3 optical photolithography (single/double face)• 1 Stepper g-line 0.6um (1 new stepper i-line 0.35um)• 2 wafer bonders• RTA (max 1150ºC, max 1900ºC) • 2 RIE, 2 ICP• Wet etch, cleaning, drying• CMP• In line measurements: ellipsometer, nanospec,

profilometer, FTIR, 4 probes, SEM…

CNM FACILITIES


• 4 "contaminated" resistive furnaces:PECVD, RTCVD

• Metallization : 2 sputtering (Al, Ni, Ti, W, Si, Cr, Pt) (Ni, Ti, Au) and 1 e.gun (all)

• 2 optical photolitography equipments(simple/double face)

• 1 RIE, 1 ICP• 1 maskless lithography equipment• 2 Electron beam lithography: Leo 1530 +

Raith Elphy plus and Raith 150-two (10nm-20nm)

• 1 Nano Imprint litography Obducat NIL 4” + 1 NPS300 from SET

• 1 FIB• In line measurements: ellipsometer,

nanospec, • Profilometer, FTIR, 4 probes, SEM…• 2 AFM

Nanotechnologies and non-CMOS

CNM FACILITIES


TECHNOLOGY TYPE CHARACTERISTICS APPLICATION

CNM - CMOS CMOS 2 Poly - 2 Metals Analog / Digital

CNM POWER Lateral and vertical DMOS Double Diffusion Power Devices

SiC

Power Diodes, JFETs, MOSFETs, MESFETs. High Temperature Sensors

Planar and MESA Technology(2.0 µm)

Power, High Temperature and Biomedical Devices

CNM μSiSTEMS Si Sensors and Actuators

Bulk and Surface micro-machining Microsystems

CNM μSiSTEMS Pressure Sensors Piezo-resistive Low Pressure Measurements

CNM - ISFET NMOS Floating Gate FETs Chemical Transducers

MCM Si Substrates Active Substrates and flip-chip Multi-chip Modules

CNM - TOI Si Integrated Optics Technology Dielectrics and Polymers Integrated Optical

Components

NANO-FABRICATION

Si Nano-mechanical Structures

Surface Nano-machining. Minimum feature size:

100nm

Nano-mechanical and Nano-electro-mechanical

Systems

Technologies


Technological Support

Electrical Characterisation

• Device Characterisation and parameter extraction (SPICE)

• Equipment maintenance and set up• Production wafer parametric test• Test structure design and

characterisation• New measurement techniques

development• Application specific system design

and development (demonstrators)• On-wafer electrical characterisation


Electrical Characterisation Equipment

• High performance DC measurement system

• Power device measurement system• Dynamic and functional digital

characterisation equipment• Special equipment dedicated to sensor

characterisation• Other specialised equipment



Design and CAD

• VHDL/Verilog to ASIC/FPGA: Modelling, simulation and synthesis of circuits, IPs and growing to systems on chip

• Support and training to users, purchases and general management of CAD

• CAD development for internal use• Libraries and design kits development for

internal and external technologies• Management of external kits• Back-end: P&R, delay extraction /

backannotation and post layout functional and fault simulation



Power Devices and Systems


• Si power devicesNew designs and concepts of high voltage IGBTs, low resistive LDMOS transistors for RF applications, super-junction LDMOS devices aimed at automotive applications, thin SOI Smart Power technology and advanced protecting devices like TVS (Transient Voltage Suppressors).

• Wide Band Gap SemiconductorsModelling and set up of optimized technologies for Wide Band Gapsemiconductor (SiC, GaN) processing, design and implementation of novel power devices based on the materials (diodes, transistors MOS, DMOS, JFET, BJT, IGBT...).

• Power Systems IntegrationNew methods for the design, modeling, development and characterization (thermal and electrical) of power integrated systems. New interconnection and packaging techniques. Reliability analysis of power devices and systems. Technologicalprocesses addressed to functional integration, intelligent powermodules and smart power ICs.

Power Devices and System Integration


Si Devices


Low Voltage VDMOS Transistor

30V-VDMOSRON=5 mΩ @ 10 A

Rg=200 mΩRON=4.4 mΩ


Fast Switching MOS-Thyristor Devices

P+-DiverterP-Body

N+

P+

GATE

CATHODE

SHORTED-ANODE

N+

Rb

Base Resistance MOS-Controlled Thyristor (BRT)

On-State Voltage Drop (V)

Vg=15 V

Epitaxied

Shorted Anode


Single cell LDMOSMulti-finger LDMOS

GATE

DRAIN

SOURCE

SOURCE

DRAINGATE

Silicon RF LDMOSDesign and fabrication of 80 V LDMOS for RF applications


Silicon RF LDMOSDesign and fabrication of 80 V LDMOS for RF applications

• Set-up of individual technological process steps• Set-up of the whole process technology

DRAINSOURCE

GATEN+TiSi2 P-Epilayer


Single-RESURF LDMOS

Maximum VBR.

VBR very sensitive to N-drift dose.

Thick-SOI substrateSDD & DDD LDMOS

BOX

Gate

P substrate

N NN-drift N-driftYj

N NP-body P-body

Gate

LLDD LLDD

Drain

LPoly LPoly

P epi

Drain Source

NWD LDMOS

dr

P substrate

P sinker

SDD structure

NWD structure

VBR very sensitive to the LPoly.

RON-sp reduction by increasing LPoly

The VBR2/RON-sp FOM improves by

decreasing LPoly

DDD structure

Best RON-sp/VBR trade-off

1

2

3

4

5

0 1 2 3 4 540

50

60

70

80

90

VB

R (V

)

N-Drift dose (1×1012) (cm-2)

SDD DDD NWD

( LPoly = 1.5 μm) NWD

( LPoly = 2 μm)

RON-sp

VBR = 80 V

VBR

SDD DDD NWD


(LPoly = 2 μm)

RO

N-s

p (mΩ×c

m2 )


Single-RESURF LDMOSThick-SOI substrate

SDD & DDD LDMOS

BOX

Gate

P substrate

N NN-drift N-driftYj

N NP-body P-body

Gate

LLDD LLDD

Drain

LPoly LPoly

P epi

Drain Source

NWD LDMOS

dr

P substrate

P sinker

N-drift integrated charge:

1

2

3

4

5

0 1 2 3 4 540

50

60

70

80

90

Qopt NWDQopt DDD

VB

R (V

)

N-Drift dose (1×1012) (cm-2)

SDD DDD NWD


( LPoly = 2 μm)

RON-sp

VBR = 80 V

Qopt SDD

VBR

SDD DDD NWD


(LPoly = 2 μm)

RO

N-s

p (mΩ×c

m2 )

SDD: QNdr=1.37×1012 cm-2

DDD: QNdr=1.7×1012 cm-2

NWD: QNdr=1.31×1012 cm-2

( )drj

Ndr dr0

YQ N y dy= ∫Optimal QNdr

MAX 12 -2Ndr 1 4 10 cmQ .≈ ×

RON limited by RESURF technique


GateSource

TBOX

TSOI

Drain Gate Source

BOX

N NNP PN-drift

P epi

P-substrate

P-body P-body


IGBTs Fabricated at CNM

TO-247P TO-220

TO-3


600V IGBTs

0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,00

2

4

6

8

10

12

14

16

18

20

After H+

irradiationBefore H+ irradiation

600V IGBT5.5mm x 5.5mmVGE = 15V

I C (A

)

VCE (V)

I(V) characteristics

Turn-off processafter irradiation

Turn-off processbefore irradiation

(Collaboration withthe CTU- Prague)


• Low losses structure combining

advantages of low on-state voltage

drop and short current tail

• 600V Bi-IGBTs designed and fabricated

at CNM

Monolithically integratedslow and fast IGBTs


6.5 kV basic cellsimulation

Simulation of 6.5kV IGBT termination

6.5 kV IGBT fabrication and optimisation: basic cell and termination• RONxS optimisation• Floating guard rings with field plate

Detail of a fabricated 6.5 kV

cellular IGBT

Top view of afabricated

6.5 kV diode

6.5 kV IGBTs


6.5 kV core IGBT

OCTSC3 OCTSC4 OCTSC7 OCTSC8 OCTSC11 OCTSC12

OCTSC1 OCTSC2 OCTSC5 OCTSC6 OCTSC9 OCTSC10

OCTSC14

OCTSC13

HEXHEX3 HEXHEX4

HEXHEX1 HEXHEX2 HEXHEX5

HEXHEX6ST3 ST4

ST1 ST2

I(V) of 6.5 kV IGBTs (Vg=15 V)StrippedIGBT

Cellular IGBT

0 2 4 6 8 10 12 14 16 18 20Voltage drop (V)

0

25

50

75

100

125

150

175

200

Curren

tden

sity

( A/c

m²)

dev1

dev2

dev3

dev4

dev5

dev6

dev7

dev9

dev10

dev11

dev12

dev13

dev14

dev15

dev16

dev17

dev18

dev19

dev20

dev21

dev22

dev23

dev24

6.5 kV IGBT monitor chip


N

Al

SiO2

Poly Si

P +

Junction supportingforward bias

Body-P

Epitaxy -N

Substrate-P

Substrate-P

+

+

-

Junction supportingreverse bias

• 600V RB-IGBT has been designed and fabricated at CNM

• Additional protection of IGBT periphery: trench isolation

(patent pending)

• Applications: Current inverters,

resonant converters, Matrix converters, BDS

RB-IGBT Cross-section

RB-IGBT chip layout

Preliminary results

Reverse Blocking IGBT

-800 -600 -400 -200 0 200 400 600 800-1,25-1,00-0,75-0,50-0,250,000,250,500,751,001,25

I C (m

A)

VCE (V)

RB-IGBT(G-E short)

3328-RBI Wafer 11 Bidirectional Blocking Capability

-700 -600 -500 -400 -300 -200 -100 0-1,0x10-4

-8,0x10-5

-6,0x10-5

-4,0x10-5

-2,0x10-5

0,0

Col

lect

or c

urre

nt (A

)Collector-emitter Voltage (V)

Vge=0V Vge=2V Vge=4V Vge=6V Vge=8V

3328-RBI Wafer 11 Reverse Blocking capability


• Design of monolithically integrated

overvoltage sensors with high voltage

IGBTs

• 3.3 kV devices aimed at traction

applications

3.3 kV IGBTs with integratedanode voltage sensor


Protection DevicesBOD

TVS


WBG Semiconductor Devices


SiC

Power Rectifiers

oxide

Source GateDrain

VSVGS

VDS

L

n+ n+XOX

W

P-type Epitaxy

n-channel

VBSub

0 100 0 2 000 3000 4000 500 0-400

-300

-200

-100

0

100

200

300

400

500

0

200

400

600

800

1000

1200

1400

0

2

4

6

8

10

12

14

t(s )

ΔV(

μV)

p p m C O

p p m N O 2

High Temp. MOSFET Power JFETs Power MOSFETs

RF MESFETs

SiC Technologies

MEMS-NEMSBiomedical devices

300ºC gas sensors


1.2kV & 3.5kV 25mm2 SiC Schottky Diodes

VAK= 1.78V @ 50A (25mm2 diode)

1.2kV diodes: estimated epilayer resistance, Repi = 1.5 mΩ.cm2

In any case, for these diodes areas, high quality starting material is compulsory.

Starting material from CREE: 3” ultralow micropipes 4H substrate

Unipolar power devices: 300V-3500V

Wafer ∅ 75 mm


High temperature (300ºC) SiCSchottky Diodes

0.0 0.5 1.0 1.5 2.00.00

0.02

0.04

0.06

0.08

0.10

25ºC 50ºC 100ºC 150ºC 200ºC 250ºC 300ºC

I A (A

)

VAK (V)

Temperature


•• --170170ººCC toto 270270ººCC operationoperation temperaturetemperature

•• ApplicationApplication: ESA : ESA missionmission BepiColomboBepiColombosolar panel solar panel protectionprotection

1,9

1,95

2

2,05

2,1

2,15

2,2

2,25

0,0 100,0 200,0 300,0 400,0 500,0

T ime (hours)

Forw

ard voltag

e (V)

Ni Schottky diode withhermetic sealing

W Schottky diode

Forw

ard

volta

ge(V

)

Vf at 5A and 270ºC

Time (hours)1,9

1,95

2

2,05

2,1

2,15

2,2

2,25

0,0 100,0 200,0 300,0 400,0 500,0

T ime (hours)

Forw

ard voltag

e (V)

Ni Schottky diode withhermetic sealing

W Schottky diode

Forw

ard

volta

ge(V

)

Vf at 5A and 270ºC

Time (hours)


1.2 kV large area diodes = 2.56 mm2

Stressed in DC at 8A (312 A.cm-2) during 50 hours

1.2kV JBS Diodes: stability

No degradation observed: no stacking faults propagation

JBS in Schottky+bipolarmode conduction


0 1 2 3 40

5

10

15

20

0

195

391

586

781

D5LP = 2 μmLN = 3 μm

D6 LP = 3 μm, LN = 4 μm

I A (A

)

VAK (V)

T0 T0+10H T0+20H T0+30H T0+40H T0+50H

JA (A

.cm-2)

Wafer ∅ 50 mm


Bipolar power devices: 3500V-6500V

Anode

P+-type

P- JTE P- JTE

Cathode

4H-SiC N- -epilayer : 6×1014 cm-3

45 μm

4H-SiC N+-type Substrate

Detch 6 μm

Anode

P+-type

P- JTE P- JTE

Cathode

4H-SiC N- -epilayer : 6×1014 cm-3

45 μm

4H-SiC N+-type Substrate

Detch 6 μm

MESA technology with epitaxied anode Low stacking fault generationHigher conductivity modulation

SiC 4kV PiN Diodes

• Especially prepared material for low BPD density by Norstel• Also done on on-axis material from Linkoping Univ. • LowLow StackingStacking faultsfaults densitydensity afterafter stressstress• Confirm the low impact of our technological process on degradation

3.5kV SiC Diodes comparison

0 1 2 3 4 5 6 70

100

200

300

400

T = 25ºC

JBS LP = 2 μm, LN = 3 μm JBS LP = 3 μm, LN = 4 μm

J A (A

.cm

-2)

VAK (V)

Bipolar diode Schottky diode

T = 100ºC


SiC Power MOS transistors

CNM 3.5KV MOSFET


12µm

1µm

33.5µm

11.5µm4µm12µm

1µm

33.5µm

11.5µm4µm

0.15 0.20 0.25 0.30 0.35 0.40

1011

1012

1013

TEOS + RTA N2O

TEOS + N2

O2 + TEOS +O2

O2 + TEOS + Ar

100 nm TEOS

Inte

rfac

e D

ensi

ty S

tate

s [c

m-2eV

-1]

EC-ET [eV]

N2O + TEOS

Cross section made by M. Buzzo and M. Ciappa from ETH Interface density state in the SiC gap near the conduction band

•• Optimization of the gate dielectricOptimization of the gate dielectric•• Novel processes for higher channel mobilityNovel processes for higher channel mobility•• Reliability of the gateReliability of the gate•• 3 terminals devices 3 terminals devices -- gate controlgate control•• 11 11 photolitographicphotolitographic mask levelsmask levels•• 22μμm minimum feature sizem minimum feature size•• Initiated in ESCAPEE EU project Initiated in ESCAPEE EU project


•• JFET unipolar vertical JFET unipolar vertical powerpower devicedevice•• 3 3 terminalsterminals devicesdevices -- gategate controlcontrol•• 8 8 photolitographicphotolitographic maskmask levelslevels•• 22μμm minimum feature sizem minimum feature size•• PatentedPatented withwith Schneider Schneider electricelectric

JFETs for Current Limiting


530 µm × 530 µm530 µm × 530 µm

gate

source

passivation

Drain metalization

gate metalization

source metalizationCNM/Ampère


Large area SiC transistor


CNM/Ampère•• ACCUMOS vertical ACCUMOS vertical powerpower devicedevice•• 5mmx5mm 5mmx5mm transistorstransistors•• 2 2 oror 3 3 terminalsterminals devicesdevices•• 7 7 photolitographicphotolitographic maskmask levelslevels•• 22μμm minimum feature sizem minimum feature size


Bipolar switches: 3500V-6500V

SiC Bipolar Transistor

0 1 2 3 4 50,0

0,2

0,4

0,6

0,8

0

16

32

48

63

JC (A

.cm-2)I C

(A)

VCE (V)

IL2

0 25 50 75 1000

5

10

15

20

25

30

β max

IC (mA)

IS1 IS2 IS3 OS1

Epi N+

Epitaxy P

Epitaxy N-

Substracte N+

Collector

Base

Emitter

Epi P+

LE LBLEB

W’etch

W’N+

WP

WN-

0.3 µm

1

Epi N+

Epitaxy P

Epitaxy N-

Substracte N+

Collector

Base

Emitter

Epi P+

LE LBLEB

W’etch

W’N+

WP

WN-

0.3 µmEpi N+

Epitaxy P

Epitaxy N-

Substracte N+

Collector

Base

Emitter

Epi P+

LE LBLEB

W’etch

W’N+

WP

WN-

0.3 µm

1

•• HighHigh voltagevoltage vertical vertical powerpower devicedevice•• 3.5kV 3.5kV toto 5kV5kV•• Novel reNovel re--epitaxiedepitaxied base base technologytechnology•• 9 9 photolitographicphotolitographic maskmask levelslevels•• 22μμm minimum feature sizem minimum feature size•• ESA ESA projectproject withwith EADS & EADS & NorstelNorstel


GaN Technology: Ohmic Contact Formation

Physical CharacterizationTi/Al based Ohmic contact to GaN

Contact resistance in the order of 5x10-6 – 2x10-5 Ωcm2

GaN technology: unipolar 600V

•• HighHigh voltagevoltage lateral lateral powerpower devicedevice (up (up toto 600V)600V)•• LowerLower costcost thanthan SiCSiC whenwhen growngrown onon SiSi•• Performances Performances competitivecompetitive forfor lowlow--mediummedium

powerpower andand voltagesvoltages


Gate oxide: Deposited SiO2 from TEOSChannel mobility ~20 cm2/Vs

GaN Technology: MOSFET

Mature technology for MOSFET fabrication

Temperature behavior modeling

GaN technology: unipolar 600V

•• HighHigh voltagevoltage vertical vertical powerpower devicedevice•• LowerLower costcost thanthan SiCSiC whenwhen growngrown onon SiSi•• Performances Performances competitivecompetitive forfor lowlow--

mediummedium powerpower andand voltagesvoltages•• HEMT: HEMT: limitedlimited breakdownbreakdown voltagevoltage andand

normallynormally--onon•• MOSFET: Experimental MOSFET: Experimental higherhigher channelchannel

mobilitymobility thanthan SiCSiC0 1 2 3 4 5

0.0

0.2

0.4

0.6

0.8

1.0

1.2

0 1 2 3 4 50.0

0.5

1.0

1.5

2.0

2.5

ΔVg=1 V

Vg=22 V

Dra

in C

urre

nt [m

A]

Drain-Source Bias, Vds [V]

L=2 μm W=150 μm

tox=100 nm

T=25 oC

T=50 oC

T=100 oC

T=150 oC

T=200 oC

150 200 300 400 500 600 7000.1

1

10

100 Experimetal Data Theoretical Fit

Eox=1.5

Eox=1.1

Eox=0.5 MV/cm

Fiel

d-ef

fect

Mob

ility

, μFE

[cm

2 /Vs]

Temperature, T [K]


Graphene growth on SiC


•• Promising Promising nanonano--material for CMOS and sensors applicationsmaterial for CMOS and sensors applications•• Obtained by Si sublimation on Obtained by Si sublimation on monocrystalinemonocrystaline SiCSiC bulkbulk•• Annealing: Annealing: FewFew stepssteps at 1050at 1050°°C C andand 11501150°°C C toto removeremove anyany trace trace ofof

nativenative oxide oxide andand toto reorganisereorganise thethe surfacesurface + + sublimationsublimation stepstep betweenbetween1450 1450 andand 1750 1750 °°C C fromfrom 5 5 toto 30min.30min.


Wide isolated FLG flake

C face On-axis 6H-SiC Semi-insulatinglayers Up to 500um long !!


Graphene FET transistor

Graphene processing


Power Systems Integration


Power Systems Integration ActivitiesPower Systems Integration research activities are focused on the development of new technologies and methods allowing the implementation of semiconductor power devices in power electronics systems with higher levels of integration.



The main research topics are:

Thermal management: Design of new packages and modules for high efficiency cooling, based on 3D thermal simulation. Thermal characterization of the developed systems and thermal parametersidentification.

Packaging technologies: Design and development of new packages and modules for high- power, high-temperature and high levels of integration power systems. New interconnection technologies.

Electro-thermal characterization: Advanced measurement set-ups based on optical methods, IR and liquid crystal thermography for the precise electro-thermal characterization at chip or system level.

Reliability: New methodologies for the analysis of the reliability limits of advanced power systems and devices (high temperature, wide band gap).

Power Systems Integration Activities



Wire-bonding

Analysis of gate finger influence

• Study of new housing concepts for WBG semiconductors (SiC, GaN…)• Main goal: Minimize thermal resistance of the package• Thermal design based on CFD simulations (FLOTHERM)• Space applications: High temperature (300ºC), high frequency, high power…• Thermal simulations from chip to system level

Flip-Chip Study the use of thermal via holes

21 mm multichip housing

Thermal ManagementAdvanced package thermal design: WBG housings

Analysis ofdifferent chipconfigurations


1.2mm GaN HEMT with gate-to-gate 50 µm

2500 2600 2700 2800 2900 3000 3100 320030

40

50

60

70

80

90

100

110

120

130

140

150

160

Tem

pera

ture

(ºC

)

X distance (µm)

Finger pitch: 50/50 Tmax=163.2ºC


Infrared thermographyshowing the module

temperature distribution

Thermal simulation of the water-cooledpower module. Temperature distribution

600V-400A IGBT water-cooledpower module for electric vehicle


Thermal Management High power modules thermal design, simulation and test

• Thermal design of high power IGBT modules for electric vehicle applications• Integrated micro-channel structure for water-cooling


FLOTHERM modelsMOSFET and Diode

Infrared Thermographyvalidation

Face A Face B

Definition of a general methodology for coupling electro-thermal simulationsThermal models development:

From SMD power devicesUp to multilayer PCB

Electrical Model Thermal model

Thermal Management Coupled electro-thermal simulation: High integration density DC/DC converter



Poly-Si Heating resistor stripes Pt sensing resistor

0 5 10 15 20 25 30 350

10

20

30

40

50

60

70

80

90

DBC Al2O3 RTH = 0,63 K/W

IMS-2 RTH = 2,03 K/W

Del

ta T

(ºC

)

Power (W)

IMS-1 RTH = 2,46 K/W

Comparison between two IMSs and a DBC substrate

Thermal resistance and impedance measurements

020406080

10002468

-0,5 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 4,50

102030405060

ΔT chip 9 (inactive)

ΔT chip 20 (active)

Heating element: chip 20

P ch

ip 2

0 (W

)

Time (sec)

ΔT

chip

20

(ºC

)

ΔT

chip

9 (º

C)

Test module

Thermal Management:Thermal Test Chip for thermal assessment of substrates

Si chip showing similar thermal behavior than typical power devices



Sample

HeatSource

Pressure

Thermal Management:Thermal conductivity measurement of power substrate materials

Method 1: RTH measurement set-up ofbare material samples to derive the KTH

Method 2: Minimization of test modules RTH error between measurement and simulation, adjusting KTH


0,9 1,0 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,90,0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

Err

or(R

TH)

(K/W

)

IMS-1 Composite Thermal Conductivity (W/mK)

Test module with TTC

Test module simulation

RTH measurement set-up


Electrical design

Layout design

Thermalsimulation

Bare IMS substrate

Copper etching

Component placement

Solder reflow

Finished module Thermal characterisationElectrical test


Packaging Technologies: Power Modules Development

4

AUT OD OOR - IMS H-Bridge and c urrent measu rement

C NM Au thors: X. Jo rda, J . Bausells

A4

1 1Tuesday, D ecember 12, 2000

Title

Size Doc ument Number Rev

Dat e: Sheet o f

TD340

123456789

10 11121314151617181920VBAT

VOUTRESETCW DWDSTBYTEMPIN1IN2CF GND

L1L2S2H2

CB2S1H1

CB1OSC

Q2HST B60NE03L-10

32

1

Q2LST B60NE03L-10

32

1

Q1HSTB60NE03L-10

32

1

Q1LSTB60NE03L-10

32

1

C7220n

J H10

Sens Out

11

JH 11

XTAL1

1 1

JH 12

XTAL2

1 1J H13Vregin

11

J H14

VregIn

11

J H15

VregOut

11

J H16

VregCont

11

J H17PW Min

11

C3270pJH 5

IN 2

11 + C1

10uF

R6 10k

R7 22k

R8 47k

R9 47k

R10

10k

R11 47k

R12 47k

R13 10

R14 47k

R1 22

R2 22

R3 22

R4 22

+

C6100u

+

C9100u

JH 2

Vout

11

C5 47n

JH 1

Vbat

11

JH 4

IN 1

11

JH 3

TEMP

11

JH 6

GND

11

+

C8100u

J H9

Out 2

1 1JH 8

Out 1

1 1

JH 7

PW R_GN D

11

R15 0

R16 0

R17 0R55.6k

C4 47n

C2

220n

AMS GI AN A

123456789

1011121314 15

161718192021222324

2627

25

28VcntRrefVddVssVdddDcl kDIOBrOClkResIntMS OFIVss h Vddh

PTCAnl

Tes tPWMXtal 2Xtal 1

Gi nB rl

Vs s

VdhV h

Gout

SC


-

600V-400A IGBT water-cooledpower module for electric vehicle


Packaging Technologies: Module and package examples

48V – 20A Si-VDMOS + SiC Schottky diodes200ºC converter for common-rail engine injectors

150V – 10A H-bridge converter with VDMOS+driver MCM flip-chip assemblies

AlGaN/GaN HEMTs RF package for 300ºC

SiC Schottky diodes TO-257 with BeO for 270ºC

VDMOS

driver

Si-VDMOS

SiCSchottky

Al2O3DBC

200ºCSMDs


S2 D2Rg2

Dz2C2

Opto2

Rg1

Opto1

C1 Dz1

S1 D1

DC/DC

D 1riv

D 2riv

Vcc1

Vcc1

Ref2

- 2Vcc

- 2Vcc

In

Vcc

Isign

Ref1C3

O1

XTL

G1

T1

T2

R1

R2O2 G2

-4 -3 -2 -1 0 1 2 3 4-20

-15

-10

-5

0

5

10

15

20

In = 0VIn = 0V

In = 5V

I IBD (

A)

VIBD (V)

In = 5V

Ch1: 5V/div Ch4: 20V/div Ch2: 5V/div Ch3: 20V/div T: 2µs/div

In

Isign

VGE(S1)

VGE(S2)

Ch1: 5V/div Ch4: 20V/div Ch2: 5V/div Ch3: 20V/div T: 2µs/div

In

Isign

VGE(S1)

VGE(S2)

BDS static I-V curve IGBT commutation sequence depending on the current sign

Powerstage

Controlcircuitry

Packaging TechnologiesIntelligent Power Module implementing a Bidirectional Switch


• Hybrid IPM performing the power BDS function, including the appropriate commutation strategyof the IGBTs (PIC), gate drivers, floating voltage power supplies and protections


Packaging TechnologiesShadow-masking metallization method

Technology for selective metallization of power devices and substratesDefinition of tracks and pads on ceramic substratesMetallization of power devices allowing advanced interconnection techniques

Application example:Double-side cooling of IGBTs with

power bumps avoiding wire-bondings

Shadow-masks Metallized power devices

Metallizedceramics

Power bumps


Heatsink

Heatsink


• Advanced optical techniques for depth-resolved electrothermal characterization:• Free-carrier absorption: free-carrier concentration measurements,• Internal infrared laser deflection: thermal gradients determination (heat flux)• Fabry-Perot thermometry: temperature measurements

Transient free carrierconcentration measurement

in a PIN diode

Electro-thermal CharacterizationAdvanced optical techniques for reliability studies


0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.00

5

10

15

20

25-1.5-1.0-0.50.00.51.01.5

(b)

ΔT

[K]

Time [s]

(a)

Inte

rfer

ence

sign

al [a

.u.]

Heating Cooling

Fabry-Perot ThermometryThermal gradient measurements

Laser beam

IGBT

Inspection depth

Laser beam


• Structure failure signature determination in power devices under working conditions• Reliability studies on new emerging technologies (SiC, GaN…) at chip and package level• Use of advanced optical techniques for reliability purposes (FCA, IIR-LD, etc).

Hot spot detection in ICs by heat flux sensing

ReliabilityPower Device Failure Analysis

Structural failure signature in an IGBT


SiC Schottky diode damage after surge current and power

cycling tests

Melted Area


Power Devices and Systems Group

Specific Facilities


Software

- Technological simulation:- SYNOPSIS (Athena)- Avanti (tsuprem4, suprem3)- Montecarlo based software

- Electrical simulation:- SYNOPSIS (Atlas)- Avanti (Medici)

- Thermal simulation:- Flotherm

- Circuit Design and electrical sim.:- Orcad Layout- Pspice

- Mask design:- Cadence Framework

- Device Characterization and analysis:- Metrics Technology (ICS, IC/V)- LabView- Matlab- Origin


Power Devices & Systems Characterisation Lab• Static characterization of components:

• Semiautomatic wafer probers with hot chuck (300ºC) • Source-measurement units (up to 1100V – 10A)• CV measurement equipment• Curve tracers (up to 3300 V – 400 A)• Instrumentation controllers (GPIB bus)

• Dynamic characterization of components:• Specific measurement circuits for:

Switching timesPower switching lossesShort-circuit characterizationGate driving characteristics

• ESD and surge characterization equipments

• Equipment for the design, development and characterization of power systems

• Multichip power modules and packaging fabrication and inspection facilities (reflow oven, C-SAM acoustic microscope)


• Infrared Thermography measurement equipment:

• AGEMA Thermovision THV-900

• Macroscopic and microscopic lenses

• Lock-in thermography set-up

• Liquid Crystal Thermography system (ThermVIEW)

• Surface temperature mapping using LCs up to 160ºC

• Spatial resolution up to 0.5 µm using ultra 20x zoom lens

• Thermal conductivity measurement system

• KTH measurement of materials involved in power packages

• Depth-resolved Electrothermal characterization

• Measurement of internal temperature and free carrier concentration

• Thermal resistance measurement system

• Measurement of RTH using TSP (Thermo sensitive parameters)

Thermal Characterisation Laboratory


- Polytechnical University of Madrid (UPM)-Polytechnical University of Catalonia (UPC)- University of Oviedo (UO)- University of Vaencia (UV)- University of Zaragoza (UZ)- University of Santander- LAAS-CNRS - Ampère Lyon- GES Montpellier- CRHEA Nice- LMI Lyon- INPG Grenoble- Linkoping University- De Montfort University Leicester- KTH Sweden- Lamel IMM Bologna- Cambridge University- ETH Zurich- Swansea University- Warwick University- Thessaloniki University- Polytechnical University of Bucharest

Academic partners

Collaborations

Industrial partners

- SpainMIERAstrium-CRISAAISMALIBAR GHGas Natural TecnológicaFagor ElectrónicaIKERLAND INASMETASESA

-- EuropeAlstom Schneider FerrazST IBS AirbusEADSSemelab PlcDynex SemiconducorsThalesArevaSelexPhilipsENIAC platform


CNM Power Group

Date post:	28-Jun-2018
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