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Enforcing Safety of Real-Time Schedules

on Contemporary Processors using a

Virtual Simple Architecture (VISA)Aravindh Anantaraman*, Kiran Seth†,

Eric Rotenberg*, Frank Mueller‡

Center for Embedded Systems Research (CESR)*Electrical & Computer Eng./ ‡ Computer ScienceNorth Carolina State University† Qualcomm. Inc

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Complexity in Hard-Real-Time Systems

• Worst-case execution time (WCET) crucial for schedulability analysis

• Contemporary processors are extremely complex– Branch prediction, pipelining, out-of-order

execution – Improve average case performance– WCET unknown

• Complex processors not used in real-time systems

Anantaraman © 2004

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Virtual Simple Architecture (VISA)

Simple Processor

Complex Processor

Task X WCET = 10

ms

Task X WCET = ?? (unreliable) Virtual

Simple Architecture: give illusion

of simple processor

Task X WCET = 10 ms

• Novel non-literal approach to static timing analysis – Use simple processor as proxy for complex processor– Dynamically guarantee WCET

Anantaraman © 2004

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NC STATE UNIVERSITY

Virtual Simple Architecture (VISA)

Simple Processor

Complex ProcessorWorst-case

equivalent systems

Task X WCET = 10

ms Virtual Simple

Architecture: give illusion

of simple processor

Task X WCET = 10 ms

100%

proc

esso

r ut

iliza

tion

worst case

100%pr

oces

sor

utili

zatio

n

worst case

dynamic slack

actual exec. time = 8 ms

actual case

Exploit dynamic slack for power/energy savings, other functionality

actual case

actual exec. time = 3 ms dynamic

slack

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Previous Approaches1. Avoid complexity

– VISA allows complex processors to be used

2. Disable complexity during hard-real-time tasks

– VISA disables complexity only when problematic

3. Continue research in timing analysis– WCET of simple proxy improved

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VISA Overview

• Provides real-time guarantees for contemporary processors

• Approach– Execute tasks optimistically on

complex mode – Gauge interim progress– Safe back-up mode for anomalous

scenarios

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Dual-Mode VISA Processor

Dynamic branch predictor

Static prediction

Dynamic branch predictor

Static prediction

Complex mode

- dynamic branch prediction

- superscalar

- out-of-order execution

Simple mode

- static branch prediction

- scalar

- in-order execution

Complex mode

- dynamic branch prediction

- superscalar

- out-of-order execution

Simple mode

- static branch prediction

- scalar

- in-order execution

Anantaraman © 2004

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NC STATE UNIVERSITY

VISA in Action

WCEC1

23

4

chk1

chk2

chk3

chk4

WCEC’1

23

4

dynamic slack

Non-speculative simple mode

Successful speculation in complex mode headstart

1Misspeculation in complex mode

23

4

(2)

WCET preserved in spite of

missed checkpoint

$$$ cash back!

simple modecomplex mode

Anantaraman © 2004

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Contributions• Minimize headstart overhead• Novel zero-overhead VISA approach

– dynamic headstart accrual

• Extend VISA to multi-tasking systems

• Energy evaluation in multi-tasking systems

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Headstart Assessmentchk1

chk2

chk3

chk4

headstart1

WCEC3 WCEC4WCEC2

WCEC1PEC1

chk1

chk2

chk3

chk4

headstart3

PEC1 PEC2 PEC3WCEC3 WCEC4

WCECWCECWCECPECPECheadstarts

ki

ikk

k

i

ik

1

1

1

simple modecomplex mode

Anantaraman © 2004

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Explicit Padding Approach

ksk

headstartWCECWCEC

1

' max

•Pad task WCEC with max headstart amount

•Give padded WCEC to schedulability analysis

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Dynamic Headstart Accrual

kskx

headstartslack

max

•Harness naturally occurring dynamic slack in simple mode as headstart

• switch to complex mode

Anantaraman © 2004

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Dynamic Headstart Accrual

12

34

Non-speculative simple mode

WCEC

12

34

WCECSuccessful

speculation in complex mode

chk3

chk4Misspeculati

on in complex mode

(3) 34

dynamic slack

accrued slack > max (headstart2,3,4) ?

NO

simple modecomplex mode

accrued slack > max (headstart3,4) ?

YES• First simple mode, then complex mode

• No explicit headstart padding

Anantaraman © 2004

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Dynamic Headstart Accrual

12

34

Non-speculative simple mode

WCEC

12

WCEC

chk3

chk4Flexible:

fluidly switch between simple and complex

(3) 34

accrued slack > headstart4 ? YES

simple modecomplex mode

Re-enable speculation after missed checkpoint

accrued slack > max (headstart3,4) ?

YES

Anantaraman © 2004

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NC STATE UNIVERSITYExplicit Padding vs. Dynamic Headstart

Accrual• Explicit padding

+Guaranteed speculation– Inflated WCETs Unschedulable task-

sets• Dynamic headstart accrual

+Schedulability unaffected+Flexible switching – Dependent on dynamic slack in simple

mode

Anantaraman © 2004

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VISA in Multi-Tasking Systems

• Gauging mechanism (watchdog counter) disrupted

• Adapt for multi-tasking– Interruption save watchdog counter– Resumption restore watchdog counter

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Easy Integration in Multi-Tasking Systems

• System software components depend on WCET

•EDF scheduler, DVS scheduler, etc.

•VISA preserves WCET abstraction

• We demonstrate VISA in a hard-real-time system with Look-Ahead EDF-DVS [Pillai&Shin’00]

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Look-Ahead EDF-DVS in VISA

Simple processor

VISA (Explicit padding)

VISA (Dynamic headstart accrual)

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Experimental Methodology

• Cycle-accurate microarchitecture simulator

• Wattch power models to measure power/energy [Brooks01]

• 6 C-lab real-time benchmarks

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Energy Savings

0%

10%

20%

30%

40%

50%

60%

70%

ACL AMS ASC ASF ASL CLS LCF LFM LMC MSL

% e

ner

gy

savi

ng

s w

.r.t

. sim

ple

pro

cess

or

VISA processor (explicit padding)

VISA processor (dynamic headstart accrual)

Anantaraman © 2004

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Average Frequencies

0

100

200

300

400

500

600

700

800

900

1000

ACL AMS ASC ASF ASL CLS LCF LFM LMC MSL

aver

age

fre

qu

ency

(M

hz)

simple processor

VISA processor (explicit padding)

VISA processor (dynamic headstart accrual)

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High Utilization Task-sets

• Worst-case utilization (unpadded WCETs) = 1.0– Cannot use explicit padding task-set

unschedulable– Dynamic headstart accrual works!

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Energy Savings (U = 1)

0%

10%

20%

30%

40%

50%

60%

ACL AMS ASC ASF ASL CLS LCF LFM LMC MSL

% e

ner

gy

savi

ng

s w

.r.t

. si

mp

le p

roce

sso

r VISA processor (dynamic headstart accrual)

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Coarse-grained vs. fine-grained sub-tasks

Coarse-grained sub-tasks 1

1 2 3 4 5 6 7 8

2 3 4

Fine-grained sub-tasks

Anantaraman © 2004

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Fine-grained vs. coarse-grained sub-tasks

0%

10%

20%

30%

40%

50%

60%

70%

ACL AMS ASC ASF ASL CLS LCF LFM LMC MSL

% e

ner

gy

savi

ng

s w

.r.t

. si

mp

le p

roce

sso

r

dyn. headstart accrual (coarse-grained sub-tasks)

dyn. headstart accrual (fine-grained sub-tasks)

Anantaraman © 2004

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Summary• VISA enables use of complex processors

in safe real-time systems• Headstart calculation• Novel zero-overhead VISA speculation

technique – dynamic headstart accrual

• VISA extended to multi-tasking systems• 19% – 58% energy savings with respect

to explicitly-safe simple processor

Anantaraman © 2004

RTSS–25

NC STATE UNIVERSITY

Questions?