A

Seminar On

-Ve Capacitance FET Prepared By:PATEL HARDIK3146504Embedded System design

NATIONAL INSTITUTE OF TECHNOLOGY,KURUKSHETRA(School Of VLSI Design and Embedded System)

Contents: Motivation

History

Why negative capacitance???

Negative capacitance

FE-FET

Advantages

Applications

Conclusion

Refenreces

Motivation:

Why low power? Approx. 1/3 of green house effect is caused by electronics 1/3 of green house effect is caused by transportation Remaining is from other sources

Because of continuously increasing performance demand of electronics high power dissipation takes place. This leads High effort for cooling Increasing operating cost Reduced reliability & mobility Higher weight (Batteries) etc.

Because of above mentioned problems we are forced to looking for low power techniques to solve these.

History:

Salahuddin & Datta proposed that “the switching energy of a device can be reduced by replacing traditional insulating material with Ferroelectric materials”

This was the first direct observation of a long-hypothesized but elusive phenomenon called “Negative Capacitance.”

Capacitance is the ability of a material to store an electrical charge. Ordinary capacitors—found in virtually all electronic devices—store charge as a voltage is applied to them.

Q=CV

Q α V

Why negative capacitance??? Dennard Scaling of planar, Si field-effect transistors (FETs) guided

the scaling of integrated circuits technology until the early 2000s Roughly states that “Though transistor get smaller , power density

stay constant” But because of continuous increase in performance requirement i.e.

continuous scaling leads to Increase leakage current Increase heat up Thermal runaway

Dennard Breakdown happens To overcome this many solutions came forward i.e

Multicore processing Strained-Si(improve mobility) High-k dielectric(reduce leakage) FinFET(reduce short-channel effects) etc.

All above solutions adopted for scaling but doesn’t effect sub-threshold swing(S).

NEGATIVE CAPACITANCE Negative Capacitance???

" the applied voltage is increased, the charge goes down. Hence its name, negative capacitance." (vice-Versa).

Some groups proposed that use of negative capacitance gate in FET will reduce Subthreshold Swing (S). Which in turn defines the lower limit of power dissipation.

Subthreshold swing :change in gate voltage (VG) required to change the drain current (IDS) by one order of magnitude.

Lowering S would results in

reduce the power supply voltage

energy dissipation

improve static noise margin

minimum energy point voltage for ultralow power circuits

NC-FET (Why ???)

Two different approaches to reduce S: 1. modifying the current transport in the channel (e.g., tunnel-FETs

and impact ionization FETs) 2. gate-to-channel coupling with negative capacitance (NC) gate

insulators. (i.e. NC-FET)

Also it is well known that the subthreshold swing (S) associated with FETs cannot be reduced below the Boltzmann limit of 60 mV/decade(SB Z ), which in turn defines the lower limit of power dissipation.

Then question (?) arises that… Whether there is lower limit of “S”? If it is so then what is the remedy?

The solution for above problem is NC-FET(proposed by S. Salahuddinand S. Datta, ECE, Purdue University, CA ,USA)

Gate-to-channel coupling with negative capacitance (NC) gate insulators

Two types of NC gate insulators are there1.The ferroelectric FET (FE-FET)

-uses ferroelectric material as gate insulator

2.suspended-gate FET (SG-FET)

- uses air as gate insulator

In above proposed devices Negative Capacitance seen in certain region of their operation

In this NC region gate insulator are thermodynamically unstable

To make it stable “positive series capacitor”(Cs) is used

Interestingly this stabilization provides necessary voltage amplification to reduce “S” below SBZ

When an FET is operated between gate voltage VG1 < VG < VG2, writing subthreshold swing (S) as

ΔΨ :change in surface potential

S is the product of two factors

Transport factor (n)

body factor (m)

Tunnel-FETs and impact ionizationFETs operate by modifying transport factor (n).

NC-FETs address the second factor m

Using the capacitor divider model of an FET the parameter m can be written as

Cs(Q):channel depletion capacitance Cins(Q):capacitance of the gate insulator Q is charge on the gate Q1 , Q2 correspond to VG1, VG2, respectively

And m can be calculated to m=1+Cs/Cins In a classical FET, gate insulator, such as SiO2

exhibits positive capacitance, i.e., Cins > 0, which results in m ≥ 1 . So S cannot be lower than SB Z =60 mV/decade

in NC-FET if Cins < 0 with Cs > 0, m would be less than one and S would be less than SBZ

Fig 1: Equivalent capacitor divider model of FET

Ref: A.Jain, M.A.Alam,IEEE transactions on electronic devices,VOL.61,NO.7,JULY 2014

The overall gate capacitance,

CG(Q)−1 = Cs (Q)−1 +Cins(Q)−1

must still be positive at all charges for hysteresis-free stable operation. (must always greater than zero)

This stability requirement puts a fundamental constraint on Cs (Q), that is

Cs (Q)−1 ≥ − Cins(Q)−1

which should hold throughout the NC regime.

Then we would get “m< 1”

Then ultimately we get “S” less than SBZ Fig 1: Equivalent capacitor divider model of FET

Ref: A.Jain, M.A.Alam,IEEE transactions on electronic devices,VOL.61,NO.7,JULY 2014

FE-FET

Ref :A.Jain, M.A.Alam,IEEE transactions on electronic devices,VOL.61,NO.7,JULY 2014

Fig 2:FE-FET with a ferroelectric material as the gate insulator

A phenomenological model is proposed on “LANDAU GINZBURG THEORY” that a MOSFET with FE layer integrated in the gate stack could have non-degraded or even improved “S” and transconductance even though histerysis window is reduced

It is well know that ferroelectric materials are pyroelectric and piezoelectric and hence temperature is crucial parameter for understanding their physical behaviour .

FE-FET architecture shown in figure was fabricated on fully depleted (FD) SOI substrate , implementing a gate dielectric stack of 40nm of “VINYLIDENE FLOURIDE TRIFLOURETHYLENE[ P(VDF-TrFE)] 70%-30% on the top of 10nm of SiO2.

Fig 3:Minimum achievable subthreshold swing in various FETs: classical-FET (), FE-FET with BaTiO3 (♦)

Ref :A.Jain, M.A.Alam,IEEE transactions on electronic devices,VOL.61,NO.7,JULY 2014

Fig 4:(a)Voltage drop across the ferroelectric (VFE)

(b) Ferroelectric capacitance (CFE) and channel depletion capacitance (Cs ) asa function of gate charge (Q) in

FE-FET.

Ref :A.Jain, M.A.Alam,IEEE transactions on electronic devices,VOL.61,NO.7,JULY 2014

(a)

(b)

Advantages: Reduce subthreshold swing

Low power dissipation

Low threshold voltage

Voltage gating

Improve static noise margin

Reduce power supply voltage

Limitations: It remains to be seen if ferroelectric negative

capacitance does indeed lower the switching energy of practical transistors.

Negative capacitance has been observed in different systems such as electrolyte electrode interfaces, semiconductor Schottky barriers and metal–insulator–metal structures, but in all these cases energy had to be ‘pumped’ into the system from another source.

Applications: High Density Storage Devices

Super capacitors

Coil free oscillators

Coil free resonator

Harvesting energy from environment

Conclusions: The subthreshold swing cannot be arbitrarily lowered in

NC FETs.

As discussed in previous slides by lowering subthresholdswing we can lower the power dissipation

The minimum value of S depends on the specific FET design

Discussed points also highlight the need for the optimization of Cs to further reduce subthreshold swing

The arguments presented here are very general and should be applicable to any field-effect based semiconducting device.

Referneces: “Stability Constraints Define the Minimum Subthreshold Swing of a

Negative Capacitance Field-Effect Transistor” A.Jain, M.A.Alam,IEEEtransactions on electronic devices,VOL.61,NO.7,JULY 2014

“Use of negative capacitance to provide a sub-threshold slope lower than 60 mV/decade” Sayeef Salahuddin and Supriyo Datta School of Electrical and Computer Engineering and NSF Center for Computationan Nanotechnology (NCN), Purdue University, West Lafayette, IN-47907

G. A. Salvatore, L. Lattanzio, D. Bouvet, I. Stolichnov, N. Setter, and A. M. Ionescu, “Ferroelectric transistors with improved characteristics at high temperature,” Appl. Phys. Lett., vol. 97, no. 5, p. 053503,Aug. 2010

S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Lett., vol. 8, no. 2, pp. 405–410, Feb. 2008.

R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. 9, no. 5, pp. 256–268, Oct. 1974.

D. Salvatore, G. A. Bouvet, and A. M. Ionescu, “Demonstration of subthrehold swing smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack,” in Proc. IEEE IEDM, Dec. 2008,pp. 1–4.

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