Network on Chip (NoC) An Overview

Table of contents

• Motivations

• Topologies of NoC

• An example of NoC

• Emerging Interconnect technics

Introduction

• Evolution of SoC:

▫ More and more transistors

▫ More and more resources

Motivations

• Scalability

• Reuse of usual network technics

• Predictability

Motivations - Scalability

• We will follow 3 criterias:

▫ Performance:

How increasing the count of resources affect performances of the interconnect?

▫ Complexity:

How increasing the count of resources affect the complexity of the chip?

▫ Design:

How increasing the count of resources affect the interconnect design?

Motivations – Scalability

• Let’s compare with other solutions:

Fully Connected Buses Network

One Chip

Motivations – Scalability

• N: resources count

Fully Connected Buses Network

Scalability Performances

The Best Not dependent of

N

Decreasing a lot with N

In the middle

Scalability Complexity

~ N² Not depending of N

~N

Scalability Design

Easily scalable Redesign it for each N

Easily scalable

Motivations - Reuse of usual network technics

• Application of all technics already approved in hardwired network:

▫ Fault detection

▫ Channel

▫ Multicast/Broadcast, etc…

• But capability of NoC to have bigger data wires:

▫ Ethernet: 8 wires

▫ An example of NoC: 256 data wires

Motivations - Predictability

• Communication performance:

Regular geometry can potentially make communication performance more predictable.

Use of bandwidth policies like pre-schedule channels.

Motivations - Predictability

• Predictable electrical parameters:

▫ Reduced wire length

Low noise and design constraints

Reduced delays constraints

▫ Regularity

Topologies of NoC

• 2D Mesh

• 2D Taurus

• Ring

• Star

Topologies of NoC – 2D Mesh

• Good complexity scalability

• Simple switch

Topologies of NoC – 2D Taurus

• 2D Mesh like

• Increase complexity

• Increase performance

Topologies of NoC – Ring

• Low complexity

• Low performance

Topologies of NoC – Star

• Huge complexity in the middle

• High performance

• Add a bottleneck

An example of NoC

• Design by:

William J. Dally and Brian Towles

• From:

Stanford University

An example of NoC

• 12x12mm chip

• 0.1 μm CMOS

• 0.5 μm wires

• 16 3x3mm tiles

• Different resources:

▫ Processors, DSP, Memory, etc…

• Tiles use only Network to communicate

• Use of 2D-Taurus

An example of NoC - Interface

• Each tiles have an interface

• Input: tile => Network; Output: Network => tile

• 5 inputs/outputs per tiles: N, S, E, W and Tile.

Resource

West

East

North

South

Tile

MSB

MSB

MSB

MSB

An example of NoC - Interface

• One input buffer and state for each virtual channel

• The controller then schedule packets to the 4 outputs (N, S, E, W)

• There is one output buffer by output

• Controller schedule them to the tile node

Tile Network

Network Tile

An example of NoC - Datagram

• 256-bits data field

• 38-bits control field for input

▫ Type (2bits)

▫ Size (4 bits)

▫ Virtual channel (8 bits)

▫ Route (16 bits)

▫ Ready (8 bits)

• 22-bits control field for output (like input without route)

An example of NoC – How it’s done

• 8 wires from tile i to j need to be logically connected

• Whenever the state change, input port inject a packet of 16 bits in the network.

• 8 bits hold state of wires

• 8 bits identify it as containing logical wire

• Others applications possible: r/w memory, flow-controlled data stream, etc…

An example of NoC – Results

• Routers uses only 6.6% of the tile area

• Also use 3000 of the 6000 available wiring tracks on the top two metal layers.

• But we don’t need drivers, receivers, repeaters and wires for global signals

An example of NoC – Additional advantages

• Use fault-tolerant wiring

▫ Add one wire to a bus

▫ After test, fuses are blown to identify faulty bits

▫ Shift all bits to avoid the faulty one

• Use fault-tolerant protocol

▫ Like hardwire network: Parity bit, etc…

▫ But adding delays

An example of NoC – Additional advantages

• Pre-scheduled and dynamic traffic

▫ Enabling reservation of bandwidth

▫ Example: video stream, speech stream, etc…

Emerging Interconnect technics

• Photonic

• Wireless

• 3D Networks

Emerging Interconnect technics – Nano-

photonic Interconnection

• Advantages: ▫ High speed optical devices

and links increase the bandwidth

▫ Negligible power dissipation in optical data transport

• Drawbacks: ▫ Temperature sensitivity

of photonic components ▫ Integration of on-chip

photonic components

Emerging Interconnect technics – Wireless NoC

• Advantages:

▫ Direct point-to-point wireless links.

▫ Lower power dissipation due to multi-hop path changed by single hop.

• Drawbacks:

▫ Noisy wireless channel

▫ Need low power mm-wave transceivers

Emerging Interconnect technics – 3D

• Advantages: ▫ Higher connectivity and less hop count. ▫ Lower power dissipation due to shorter average path

length ▫ Can be combined with others

• Drawbacks: ▫ Heat issues due to high

power density ▫ Vertical via failure ▫ Heavier switch

(from 5 to 7 I/O)

Summary

=> Became essential for chip with a very large count of resources.

Questions ?