A New Digital Current Sensing Technique Suitable for Low Power Energy Harvesting Systems Mostafa Ibrahim 1 , Ayman Eltaliawy 1 , Hassan Mostafa 1,2 and Yehea Ismail 1 1 Center of Nanoelectronics and Devices, The American University in Cairo, Cairo, Egypt 11835 2 Electronics and Communication Engineering Department, Cairo University, Giza, Egypt 12613 Email : [email protected], {aeltaliawy, hmoustafa, y.ismail}@aucegypt.edu Abstract—Solar energy harvesting captures the greatest at- tention among the available self-powered systems recently. This paper presents a new control technique based on digital current sensing. The idea is based on sensing the output current through a series resistance, the current sensor is a simple analog circuit, and it generates a pulse of width that is directly proportional to the rate of change of current. A pulse-to-digital converter is designed to convert the input pulse to a thermometer code. The code is then used to control a low supply digital controlled oscillator, it generates a clock that control the charge pump that searches for the maximum power of the solar cell. This design features a hill climbing maximum power search embedded inside the pulse-to-digital converter. A low dropout regulator with resistive ladder is used to control the supply of the oscillator, the oscillator supply is used as control knob for the frequency of the charge pump. The proposed control unit exhibits low power consumption, since it works at lower supplies than the energy buffer. The design can reach a power efficiency of 58.2% up to 3mW available photovoltaic power. The measured power consumption is 36.33μW . The system is designed using Global Foundries (GF 65nm). I. I NTRODUCTION Energy harvesting is considered a very hot topic in the power management. The applications of self-powered systems are getting larger everyday starting from wearable electronics passing through biomedical section. The applications are also expanding to environmental measurements, navigation and wireless sensor nodes. This research area dictates careful design of the harvester, since most of the available power at the transducer side has to be transferred to the load with minimum power loss. The goal of this paper is to provide a CMOS custom design of a solar energy harvester, since solar energy is the most dense power source among different energy transducers. Solar energy harvesting techniques are based on maximum power point search of the photovoltaic cell. There are different algorithms for maintaining the cell at its maximum power ca- pability. The most widely used techniques are the hill climbing technique [1] and perturb/observe technique. Both techniques exhibit the procedure in finding the maximum power. The idea is based on perturbing the frequency of the power converter, then a power reading is sampled. Another perturbation is done, and another power reading is also sampled. A comparison This research was partially funded by Zewail City of Science and Tech- nology, AUC, Semi-Conductor Research Cooperation, Global Foundries, the STDF, Intel, Mentor Graphics and MCIT PV Cell SC Charge Pump Current Sensor Hill-Climbing Pulse -To- Digital Converter Digital Controlled Oscillator Clock Driver Energy Buffer load 20 bits 4 bits 4 bits 5 sense R 2 bits Fig. 1. The proposed block diagram of the energy harvester between the two samples is done, and a decision is taken to increase or decrease the frequency. This task is repeated forever as long as the harvester is powered on. The two techniques are different in the type of design. The hill climbing technique is implemented in full custom flow, whereas the perturb/observe technique is realized through FPGA flow or microcontrollers programming in the digital domain. This paper presents a new control technique based on the hill climbing algorithm. Fig. 1 shows the generic block diagram of the harvester. The solar cell is a compact verilog- A model [2]. The power converter is a 4-stage SC (switched capacitor) charge pump [3], each stage flying capacitor value is 500pF . The idea is based on placing a small series resistance in the power path between the charge pump output and the energy buffer. This current sensor is a simple analog circuit that detects a current change in the power path according to the charge pump frequency. The current sensor generates a periodic impulse, its period is inversely proportional to the current change. The pulse-to-digital converter is able to detect the period of this impulse through an embedded counter, it then manages the counter readings through a hill climbing algorithm. This block is designed using a synthesized verilog code. The pulse-to-digital converter is giving its decision in a thermometer decoding format to a digital controlled oscillator. The driver is boosting the voltage to a higher level in order to increase the driving capability needed by the power converter. This paper is organized as follows; Section (II) presents the design of the important blocks in the system. Section (III) displays the system integration and the simulations results. Section (IV) shows the conclusion and future work.
Transcript
A New Digital Current Sensing Technique Suitablefor Low Power Energy Harvesting Systems
Mostafa Ibrahim1, Ayman Eltaliawy1, Hassan Mostafa1,2 and Yehea Ismail11Center of Nanoelectronics and Devices, The American University in Cairo, Cairo, Egypt 118352Electronics and Communication Engineering Department, Cairo University, Giza, Egypt 12613
Abstract—Solar energy harvesting captures the greatest at-tention among the available self-powered systems recently. Thispaper presents a new control technique based on digital currentsensing. The idea is based on sensing the output current througha series resistance, the current sensor is a simple analog circuit,and it generates a pulse of width that is directly proportionalto the rate of change of current. A pulse-to-digital converteris designed to convert the input pulse to a thermometer code.The code is then used to control a low supply digital controlledoscillator, it generates a clock that control the charge pumpthat searches for the maximum power of the solar cell. Thisdesign features a hill climbing maximum power search embeddedinside the pulse-to-digital converter. A low dropout regulator withresistive ladder is used to control the supply of the oscillator,the oscillator supply is used as control knob for the frequencyof the charge pump. The proposed control unit exhibits lowpower consumption, since it works at lower supplies than theenergy buffer. The design can reach a power efficiency of 58.2%up to 3mW available photovoltaic power. The measured powerconsumption is 36.33µW . The system is designed using GlobalFoundries (GF 65nm).
I. INTRODUCTION
Energy harvesting is considered a very hot topic in thepower management. The applications of self-powered systemsare getting larger everyday starting from wearable electronicspassing through biomedical section. The applications are alsoexpanding to environmental measurements, navigation andwireless sensor nodes. This research area dictates carefuldesign of the harvester, since most of the available powerat the transducer side has to be transferred to the load withminimum power loss. The goal of this paper is to provide aCMOS custom design of a solar energy harvester, since solarenergy is the most dense power source among different energytransducers.
Solar energy harvesting techniques are based on maximumpower point search of the photovoltaic cell. There are differentalgorithms for maintaining the cell at its maximum power ca-pability. The most widely used techniques are the hill climbingtechnique [1] and perturb/observe technique. Both techniquesexhibit the procedure in finding the maximum power. The ideais based on perturbing the frequency of the power converter,then a power reading is sampled. Another perturbation is done,and another power reading is also sampled. A comparison
This research was partially funded by Zewail City of Science and Tech-nology, AUC, Semi-Conductor Research Cooperation, Global Foundries, theSTDF, Intel, Mentor Graphics and MCIT
PV Cell SC Charge Pump
Current Sensor
Hill-ClimbingPulse-To-
DigitalConverter
Digital Controlled Oscillator
Clock Driver
Energy Buffer
load
20 bits 4 bits
4 bits
5senseR
2 bits
Fig. 1. The proposed block diagram of the energy harvester
between the two samples is done, and a decision is takento increase or decrease the frequency. This task is repeatedforever as long as the harvester is powered on. The twotechniques are different in the type of design. The hill climbingtechnique is implemented in full custom flow, whereas theperturb/observe technique is realized through FPGA flow ormicrocontrollers programming in the digital domain.
This paper presents a new control technique based onthe hill climbing algorithm. Fig. 1 shows the generic blockdiagram of the harvester. The solar cell is a compact verilog-A model [2]. The power converter is a 4-stage SC (switchedcapacitor) charge pump [3], each stage flying capacitor value is500pF . The idea is based on placing a small series resistancein the power path between the charge pump output and theenergy buffer. This current sensor is a simple analog circuitthat detects a current change in the power path according tothe charge pump frequency. The current sensor generates aperiodic impulse, its period is inversely proportional to thecurrent change. The pulse-to-digital converter is able to detectthe period of this impulse through an embedded counter, itthen manages the counter readings through a hill climbingalgorithm. This block is designed using a synthesized verilogcode. The pulse-to-digital converter is giving its decision in athermometer decoding format to a digital controlled oscillator.The driver is boosting the voltage to a higher level in order toincrease the driving capability needed by the power converter.
This paper is organized as follows; Section (II) presents thedesign of the important blocks in the system. Section (III)displays the system integration and the simulations results.Section (IV) shows the conclusion and future work.
senseR
senseR
25MΩ
10MΩ
1MΩ
5MΩ 50pFstart_bar
ddV
sense_out
1M
2M
1S
2S
Fig. 2. Block diagram of the current sensor
II. THE PROPOSED ENERGY HARVESTER DESIGN
In [1], the design is based on sensing the output currentthrough a power hungry current sensor, then cascading with adecision generation circuit. This technique is consuming a lotof power in the control unit. The proposed design is based onlowering the supply voltage of the control unit, also it is basedon searching for the maximum power in a digital manner tosave the power consumption. The next subsections shows thedesign of each block to reach the best performance.
A. Current Sensor Design
The design of the current sensor is based on transformingthe output current to a voltage through a series resistanceRsense. The voltage drop on this resistor represents the changein the SC charge pump output current. The current of thecharge pump is proportion to the applied frequency. Fig. 2shows the block diagram of the design. The PMOS deviceM1 acts as a switch. It is normally OFF, however it goes ONwhen the charge pump ejects high current to the energy bufferduring switching. Part of the injected current is responsible forcharging the 50pF capacitor. Accordingly, when the currentincreases, the capacitor is charged fast. When the currentdecreases, the capacitor is slowly charged. The switch M2 isresponsible for discharging the capacitor for the next currentsample. The comparator is used to compare between thetwo branches S1,S2, it produces an impulse whose period isproportional to the current direction. If the current increases,the impulse period decreases as the capacitor will be chargedfast. Conversely, if the current decreases, the impulse periodincreases as the capacitor will be charged slowly. When thecomparator voltage go high, the signal startbar goes high toreset the capacitor.
B. Hill Climbing Pulse-to-Digital Converter Design
The Pulse-to-Digital converter is a state machine thatsearches for the maximum power of the solar cell. The ideaof operation is simple. It is based on counting a numberof a fast clock cycles (20MHz) during the window of theimpulse period. Accordingly, if the current sample increases,this means that the counted cycles goes down. On the contrary,if the current sample decreases, this means that the countedcycles goes up. The decision of increasing or decreasingthe frequency is based on Fig. 3 , where the value of the
01 10
00
RR=count RL=count
RC=count
RR
≤ R
C
f = f+1R
C = R
R
Initial Step
RR > RC
f = f-1RC = RR
RL ≤
RC
f =
f-1
RC
= R
L
RL > RC
RC = RLf = f+1
Fig. 3. The state machine of the proposed hill climbing pulse-to-digitalconverter
last two successive counter readings are stored in registersand compared to each other. The algorithm has 3 states:00, 01, 10, state (00) is started as an initial state to recordthe center point (RC), it records the counted cycles of thefirst sample only at the system power up. State (01) has twoconditional decisions, it represents increasing the frequencybased on comparison (i.e. rising the power hill from left). Itcompares the successive counted cycles of the last two samples(RR,RC), if (RR ≤ RC), the state remains constant andthe frequency increases. Whereas, if (RR > RC), the statechanges from 01 to 10 and the frequency decreases. State(10) has two conditional decisions, it represents decreasingthe frequency based on comparison (i.e. rising the power hillfrom right). It compares the successive counted cycles ofthe last two samples (RL,RC), if (RL ≤ RC), the stateremains constant and the frequency decreases. Whereas, if(RL > RC), the state changes from 10 to 01 and the frequencyincreases. The decision is translated to a thermometer decodeddigital word controlling the digital controlled oscillator.
C. Digital Supply-Controlled Oscillator
The digital supply-controlled oscillator design (DSCO) isshown in Fig. 4. The control knob of the oscillator is the supplyvoltage, this voltage is controlled by a low drop-out regulator(LDO). The LDO output voltage is controlled through theresistor R1 [4], where R1 is resistance switch box shown inFig. 5. It is based on cascading a stack of equal resistance Ra,each resistance has a shunt PMOS switch that turns it ON orOFF. The switch box is controlled by 20 thermometer decodedbits S < 0 : 19 >. When a PMOS device is switched OFF,a resistance Ra is added to the stack and the supply voltageincreases. The reference voltage of the LDO is based on the2-transistor design [5]. Fig. 6 shows the design of the 4-phasering oscillator used in this work.
D. Clock Driver Design
Figure 7 shows the design of the clock driver. The circuitis divided to two parts. The left part is a supply level boosterbased on [6], since the frequency oscillator works at lowersupply. Also, the SC charge pump needs a supply that is equalto the energy buffer voltage, so that the pass-transistors canwork perfect. The right side of the driver is a cascaded buffers.
1R
2R
Resistance Switch
Box1
1
2
2
ddV
hvt
lvt
1M
2M 3M
20 bits
Fig. 4. Digital supply-controlled oscillator design
Fig. 8. Available power for different lighting conditions (a)Solar cell powerversus terminal voltage (b)Solar cell power versus frequency (charge pumpconnected) (c)Energy buffer power versus frequency (charge pump connected)
Since the pass transistors of the SC charge pumps are large insize, tapered-size buffers are designed in order to drive thosetransistors.
III. SIMULATION RESULTS OF THE PROPOSED DESIGN
This section presents the simulation results of the proposedsystem. First, initial simulations are done in order to char-acterize each block in the system. Then, a closed systemsimulations are done to report the performance metrics of thewhole design.
The solar cell used is a compact verilog-A model, the opencircuit voltage VOC is in the range of 0.7V . Fig. 8(a) showsthe available power curves across different light conditions.It can be shown that each light condition has a maximumpower point available at certain voltage. The target of theclosed loop is to search for the maximum power point of eachlighting condition. Fig. 8(b) displays the power curves acrossthe charge pump frequency for different light conditions, it canbe shown that the maximum power of each light conditionoccurs at certain clock frequency. Fig. 8(c) highlights theenergy buffer available power without control unit losses.It can be shown that the output power is smaller than theavailable power, this is due to the switching/conduction lossesinside the SC charge pump.
Since the frequency oscillator is digitally controlled, the dy-namic range determines the performance of the whole system.The performance of the frequency oscillator is determined bytwo metrics. The first metric is the frequency range which isthe range between minimum and maximum frequencies theoscillator can support. The second metric is the frequencystep which is the frequency difference between two successiveinput codes, this metric determines the steady state oscillationaround the maximum power point. Fig. 9 shows the dynamicrange of the digital supply-controlled oscillator versus theinput digital code.
During the circuit operation, important signals in the designshould be ported in order to check the system functionality.Fig. 10 shows different signals in the system at one lightingcondition. Fig. 10(a) shows the internal signals of the current
0.55
0.6
0.65
0.7
0.75
0.8
0 2 4 6 8 10 12 14 16 18 20
DC
O S
uppl
y Vo
ltage
(V)
Input Digital Word
DCO Supply Voltage
23456789
1011
0 2 4 6 8 10 12 14 16 18 20
DC
O F
requ
ency
(MH
z)
Input Digital Word
DCO Frequency
(a) (b)
Fig. 9. Digital supply-controlled oscillator dynamic range across digital inputcode (a)Supply voltage (b)Output frequency
Fig. 10. System important signals at one lighting condition (a)Current sensorinternal signals (b)Shared signals between current sensor and pulse-to-digitalconverter (c)Internal signals of pulse-to-digital converter
sensor. It can be shown that when S2 voltage reaches S1
voltage, S2 resets to 0V . Fig. 10(b) shows the signals betweenthe current sensor and the pulse-to-digital converter. The resetsignal go high when S2 = S1, accordingly startbar goeshigh also to force S2 = 0. The slwclk signal positive edgeresets the counter and startbar for the next sample. Fig. 10(c)shows the transition between different digital codes to maintainthe maximum power capability. RC register represents thereading of the counter every sample. Phase signal representsthe current state of the pulse-to-digital converter based oncomparison of the successive samples. It can be seen also thatthe digital code rises in the early samples, then it oscillatesaround the maximum power point.
Three different light conditions are simulated for the wholesystem. Fig. 11(a) shows the transient simulation of the solarcell voltage across different lighting conditions. Fig. 11(b)shows the frequency of the charge pump at each lighting case.It can be shown that changing the input light will change theoperating point of the charge pump frequency and the solar cellvoltage as well in order to maintain maximum power transfer.
Table I shows the summary of the simulation results atdifferent lighting conditions. It can be seen that the averagesolar cell voltage and the average charge pump frequencyare equal to the expected values at Fig. 8. Efficiency valuesare almost equal. The maximum consumed power is below
(a) (b)
0.640.660.68
0.70.720.740.760.78
0.80.82
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Sola
r ce
ll vo
ltage
(V)
time (ms)
557.2 LUX solar cell voltage852.2 LUX solar cell voltage1156.9 LUX solar cell voltage
40µW . The expected power consumption of the pulse-to-digital converter is around 10µW for a supply voltage of 1.2V .
IV. CONCLUSION AND FUTURE WORK
This paper presents a new circuit design approach forsolar energy harvesting. The control technique is based onsensing the output current, then performing the hill climbingalgorithm in a semi-custom flow. The design features verylow power consumption and efficient tracking. Future workcan be summarized in enhancing the design of the frequencyoscillator to support a smaller frequency step, also the pulse-to-digital converter can be implemented with the technologystandard cells.
REFERENCES
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